Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * PowerPC64 port by Mike Corrigan and Dave Engebretsen | |
3 | * {mikejc|engebret}@us.ibm.com | |
4 | * | |
5 | * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com> | |
6 | * | |
7 | * SMP scalability work: | |
8 | * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM | |
9 | * | |
10 | * Module name: htab.c | |
11 | * | |
12 | * Description: | |
13 | * PowerPC Hashed Page Table functions | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License | |
17 | * as published by the Free Software Foundation; either version | |
18 | * 2 of the License, or (at your option) any later version. | |
19 | */ | |
20 | ||
21 | #undef DEBUG | |
3c726f8d | 22 | #undef DEBUG_LOW |
1da177e4 | 23 | |
1da177e4 LT |
24 | #include <linux/spinlock.h> |
25 | #include <linux/errno.h> | |
26 | #include <linux/sched.h> | |
27 | #include <linux/proc_fs.h> | |
28 | #include <linux/stat.h> | |
29 | #include <linux/sysctl.h> | |
30 | #include <linux/ctype.h> | |
31 | #include <linux/cache.h> | |
32 | #include <linux/init.h> | |
33 | #include <linux/signal.h> | |
34 | ||
1da177e4 LT |
35 | #include <asm/processor.h> |
36 | #include <asm/pgtable.h> | |
37 | #include <asm/mmu.h> | |
38 | #include <asm/mmu_context.h> | |
39 | #include <asm/page.h> | |
40 | #include <asm/types.h> | |
41 | #include <asm/system.h> | |
42 | #include <asm/uaccess.h> | |
43 | #include <asm/machdep.h> | |
44 | #include <asm/lmb.h> | |
45 | #include <asm/abs_addr.h> | |
46 | #include <asm/tlbflush.h> | |
47 | #include <asm/io.h> | |
48 | #include <asm/eeh.h> | |
49 | #include <asm/tlb.h> | |
50 | #include <asm/cacheflush.h> | |
51 | #include <asm/cputable.h> | |
1da177e4 | 52 | #include <asm/sections.h> |
d0f13e3c | 53 | #include <asm/spu.h> |
aa39be09 | 54 | #include <asm/udbg.h> |
1da177e4 LT |
55 | |
56 | #ifdef DEBUG | |
57 | #define DBG(fmt...) udbg_printf(fmt) | |
58 | #else | |
59 | #define DBG(fmt...) | |
60 | #endif | |
61 | ||
3c726f8d BH |
62 | #ifdef DEBUG_LOW |
63 | #define DBG_LOW(fmt...) udbg_printf(fmt) | |
64 | #else | |
65 | #define DBG_LOW(fmt...) | |
66 | #endif | |
67 | ||
68 | #define KB (1024) | |
69 | #define MB (1024*KB) | |
70 | ||
1da177e4 LT |
71 | /* |
72 | * Note: pte --> Linux PTE | |
73 | * HPTE --> PowerPC Hashed Page Table Entry | |
74 | * | |
75 | * Execution context: | |
76 | * htab_initialize is called with the MMU off (of course), but | |
77 | * the kernel has been copied down to zero so it can directly | |
78 | * reference global data. At this point it is very difficult | |
79 | * to print debug info. | |
80 | * | |
81 | */ | |
82 | ||
83 | #ifdef CONFIG_U3_DART | |
84 | extern unsigned long dart_tablebase; | |
85 | #endif /* CONFIG_U3_DART */ | |
86 | ||
799d6046 PM |
87 | static unsigned long _SDR1; |
88 | struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT]; | |
89 | ||
8e561e7e | 90 | struct hash_pte *htab_address; |
337a7128 | 91 | unsigned long htab_size_bytes; |
96e28449 | 92 | unsigned long htab_hash_mask; |
3c726f8d BH |
93 | int mmu_linear_psize = MMU_PAGE_4K; |
94 | int mmu_virtual_psize = MMU_PAGE_4K; | |
bf72aeba PM |
95 | int mmu_vmalloc_psize = MMU_PAGE_4K; |
96 | int mmu_io_psize = MMU_PAGE_4K; | |
1189be65 PM |
97 | int mmu_kernel_ssize = MMU_SEGSIZE_256M; |
98 | int mmu_highuser_ssize = MMU_SEGSIZE_256M; | |
584f8b71 | 99 | u16 mmu_slb_size = 64; |
3c726f8d BH |
100 | #ifdef CONFIG_HUGETLB_PAGE |
101 | int mmu_huge_psize = MMU_PAGE_16M; | |
102 | unsigned int HPAGE_SHIFT; | |
103 | #endif | |
bf72aeba PM |
104 | #ifdef CONFIG_PPC_64K_PAGES |
105 | int mmu_ci_restrictions; | |
106 | #endif | |
370a908d BH |
107 | #ifdef CONFIG_DEBUG_PAGEALLOC |
108 | static u8 *linear_map_hash_slots; | |
109 | static unsigned long linear_map_hash_count; | |
ed166692 | 110 | static DEFINE_SPINLOCK(linear_map_hash_lock); |
370a908d | 111 | #endif /* CONFIG_DEBUG_PAGEALLOC */ |
1da177e4 | 112 | |
3c726f8d BH |
113 | /* There are definitions of page sizes arrays to be used when none |
114 | * is provided by the firmware. | |
115 | */ | |
1da177e4 | 116 | |
3c726f8d BH |
117 | /* Pre-POWER4 CPUs (4k pages only) |
118 | */ | |
119 | struct mmu_psize_def mmu_psize_defaults_old[] = { | |
120 | [MMU_PAGE_4K] = { | |
121 | .shift = 12, | |
122 | .sllp = 0, | |
123 | .penc = 0, | |
124 | .avpnm = 0, | |
125 | .tlbiel = 0, | |
126 | }, | |
127 | }; | |
128 | ||
129 | /* POWER4, GPUL, POWER5 | |
130 | * | |
131 | * Support for 16Mb large pages | |
132 | */ | |
133 | struct mmu_psize_def mmu_psize_defaults_gp[] = { | |
134 | [MMU_PAGE_4K] = { | |
135 | .shift = 12, | |
136 | .sllp = 0, | |
137 | .penc = 0, | |
138 | .avpnm = 0, | |
139 | .tlbiel = 1, | |
140 | }, | |
141 | [MMU_PAGE_16M] = { | |
142 | .shift = 24, | |
143 | .sllp = SLB_VSID_L, | |
144 | .penc = 0, | |
145 | .avpnm = 0x1UL, | |
146 | .tlbiel = 0, | |
147 | }, | |
148 | }; | |
149 | ||
150 | ||
151 | int htab_bolt_mapping(unsigned long vstart, unsigned long vend, | |
1189be65 PM |
152 | unsigned long pstart, unsigned long mode, |
153 | int psize, int ssize) | |
1da177e4 | 154 | { |
3c726f8d BH |
155 | unsigned long vaddr, paddr; |
156 | unsigned int step, shift; | |
1da177e4 | 157 | unsigned long tmp_mode; |
3c726f8d | 158 | int ret = 0; |
1da177e4 | 159 | |
3c726f8d BH |
160 | shift = mmu_psize_defs[psize].shift; |
161 | step = 1 << shift; | |
1da177e4 | 162 | |
3c726f8d BH |
163 | for (vaddr = vstart, paddr = pstart; vaddr < vend; |
164 | vaddr += step, paddr += step) { | |
370a908d | 165 | unsigned long hash, hpteg; |
1189be65 PM |
166 | unsigned long vsid = get_kernel_vsid(vaddr, ssize); |
167 | unsigned long va = hpt_va(vaddr, vsid, ssize); | |
1da177e4 LT |
168 | |
169 | tmp_mode = mode; | |
170 | ||
171 | /* Make non-kernel text non-executable */ | |
3c726f8d BH |
172 | if (!in_kernel_text(vaddr)) |
173 | tmp_mode = mode | HPTE_R_N; | |
1da177e4 | 174 | |
1189be65 | 175 | hash = hpt_hash(va, shift, ssize); |
1da177e4 LT |
176 | hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP); |
177 | ||
c30a4df3 ME |
178 | DBG("htab_bolt_mapping: calling %p\n", ppc_md.hpte_insert); |
179 | ||
180 | BUG_ON(!ppc_md.hpte_insert); | |
181 | ret = ppc_md.hpte_insert(hpteg, va, paddr, | |
1189be65 | 182 | tmp_mode, HPTE_V_BOLTED, psize, ssize); |
c30a4df3 | 183 | |
3c726f8d BH |
184 | if (ret < 0) |
185 | break; | |
370a908d BH |
186 | #ifdef CONFIG_DEBUG_PAGEALLOC |
187 | if ((paddr >> PAGE_SHIFT) < linear_map_hash_count) | |
188 | linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80; | |
189 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
3c726f8d BH |
190 | } |
191 | return ret < 0 ? ret : 0; | |
192 | } | |
1da177e4 | 193 | |
1189be65 PM |
194 | static int __init htab_dt_scan_seg_sizes(unsigned long node, |
195 | const char *uname, int depth, | |
196 | void *data) | |
197 | { | |
198 | char *type = of_get_flat_dt_prop(node, "device_type", NULL); | |
199 | u32 *prop; | |
200 | unsigned long size = 0; | |
201 | ||
202 | /* We are scanning "cpu" nodes only */ | |
203 | if (type == NULL || strcmp(type, "cpu") != 0) | |
204 | return 0; | |
205 | ||
206 | prop = (u32 *)of_get_flat_dt_prop(node, "ibm,processor-segment-sizes", | |
207 | &size); | |
208 | if (prop == NULL) | |
209 | return 0; | |
210 | for (; size >= 4; size -= 4, ++prop) { | |
211 | if (prop[0] == 40) { | |
212 | DBG("1T segment support detected\n"); | |
213 | cur_cpu_spec->cpu_features |= CPU_FTR_1T_SEGMENT; | |
f5534004 | 214 | return 1; |
1189be65 | 215 | } |
1189be65 | 216 | } |
f66bce5e | 217 | cur_cpu_spec->cpu_features &= ~CPU_FTR_NO_SLBIE_B; |
1189be65 PM |
218 | return 0; |
219 | } | |
220 | ||
221 | static void __init htab_init_seg_sizes(void) | |
222 | { | |
223 | of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL); | |
224 | } | |
225 | ||
3c726f8d BH |
226 | static int __init htab_dt_scan_page_sizes(unsigned long node, |
227 | const char *uname, int depth, | |
228 | void *data) | |
229 | { | |
230 | char *type = of_get_flat_dt_prop(node, "device_type", NULL); | |
231 | u32 *prop; | |
232 | unsigned long size = 0; | |
233 | ||
234 | /* We are scanning "cpu" nodes only */ | |
235 | if (type == NULL || strcmp(type, "cpu") != 0) | |
236 | return 0; | |
237 | ||
238 | prop = (u32 *)of_get_flat_dt_prop(node, | |
239 | "ibm,segment-page-sizes", &size); | |
240 | if (prop != NULL) { | |
241 | DBG("Page sizes from device-tree:\n"); | |
242 | size /= 4; | |
243 | cur_cpu_spec->cpu_features &= ~(CPU_FTR_16M_PAGE); | |
244 | while(size > 0) { | |
245 | unsigned int shift = prop[0]; | |
246 | unsigned int slbenc = prop[1]; | |
247 | unsigned int lpnum = prop[2]; | |
248 | unsigned int lpenc = 0; | |
249 | struct mmu_psize_def *def; | |
250 | int idx = -1; | |
251 | ||
252 | size -= 3; prop += 3; | |
253 | while(size > 0 && lpnum) { | |
254 | if (prop[0] == shift) | |
255 | lpenc = prop[1]; | |
256 | prop += 2; size -= 2; | |
257 | lpnum--; | |
258 | } | |
259 | switch(shift) { | |
260 | case 0xc: | |
261 | idx = MMU_PAGE_4K; | |
262 | break; | |
263 | case 0x10: | |
264 | idx = MMU_PAGE_64K; | |
265 | break; | |
266 | case 0x14: | |
267 | idx = MMU_PAGE_1M; | |
268 | break; | |
269 | case 0x18: | |
270 | idx = MMU_PAGE_16M; | |
271 | cur_cpu_spec->cpu_features |= CPU_FTR_16M_PAGE; | |
272 | break; | |
273 | case 0x22: | |
274 | idx = MMU_PAGE_16G; | |
275 | break; | |
276 | } | |
277 | if (idx < 0) | |
278 | continue; | |
279 | def = &mmu_psize_defs[idx]; | |
280 | def->shift = shift; | |
281 | if (shift <= 23) | |
282 | def->avpnm = 0; | |
283 | else | |
284 | def->avpnm = (1 << (shift - 23)) - 1; | |
285 | def->sllp = slbenc; | |
286 | def->penc = lpenc; | |
287 | /* We don't know for sure what's up with tlbiel, so | |
288 | * for now we only set it for 4K and 64K pages | |
289 | */ | |
290 | if (idx == MMU_PAGE_4K || idx == MMU_PAGE_64K) | |
291 | def->tlbiel = 1; | |
292 | else | |
293 | def->tlbiel = 0; | |
294 | ||
295 | DBG(" %d: shift=%02x, sllp=%04x, avpnm=%08x, " | |
296 | "tlbiel=%d, penc=%d\n", | |
297 | idx, shift, def->sllp, def->avpnm, def->tlbiel, | |
298 | def->penc); | |
1da177e4 | 299 | } |
3c726f8d BH |
300 | return 1; |
301 | } | |
302 | return 0; | |
303 | } | |
304 | ||
3c726f8d BH |
305 | static void __init htab_init_page_sizes(void) |
306 | { | |
307 | int rc; | |
308 | ||
309 | /* Default to 4K pages only */ | |
310 | memcpy(mmu_psize_defs, mmu_psize_defaults_old, | |
311 | sizeof(mmu_psize_defaults_old)); | |
312 | ||
313 | /* | |
314 | * Try to find the available page sizes in the device-tree | |
315 | */ | |
316 | rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL); | |
317 | if (rc != 0) /* Found */ | |
318 | goto found; | |
319 | ||
320 | /* | |
321 | * Not in the device-tree, let's fallback on known size | |
322 | * list for 16M capable GP & GR | |
323 | */ | |
0470466d | 324 | if (cpu_has_feature(CPU_FTR_16M_PAGE)) |
3c726f8d BH |
325 | memcpy(mmu_psize_defs, mmu_psize_defaults_gp, |
326 | sizeof(mmu_psize_defaults_gp)); | |
327 | found: | |
370a908d | 328 | #ifndef CONFIG_DEBUG_PAGEALLOC |
3c726f8d BH |
329 | /* |
330 | * Pick a size for the linear mapping. Currently, we only support | |
331 | * 16M, 1M and 4K which is the default | |
332 | */ | |
333 | if (mmu_psize_defs[MMU_PAGE_16M].shift) | |
334 | mmu_linear_psize = MMU_PAGE_16M; | |
335 | else if (mmu_psize_defs[MMU_PAGE_1M].shift) | |
336 | mmu_linear_psize = MMU_PAGE_1M; | |
370a908d | 337 | #endif /* CONFIG_DEBUG_PAGEALLOC */ |
3c726f8d | 338 | |
bf72aeba | 339 | #ifdef CONFIG_PPC_64K_PAGES |
3c726f8d BH |
340 | /* |
341 | * Pick a size for the ordinary pages. Default is 4K, we support | |
bf72aeba PM |
342 | * 64K for user mappings and vmalloc if supported by the processor. |
343 | * We only use 64k for ioremap if the processor | |
344 | * (and firmware) support cache-inhibited large pages. | |
345 | * If not, we use 4k and set mmu_ci_restrictions so that | |
346 | * hash_page knows to switch processes that use cache-inhibited | |
347 | * mappings to 4k pages. | |
3c726f8d | 348 | */ |
bf72aeba | 349 | if (mmu_psize_defs[MMU_PAGE_64K].shift) { |
3c726f8d | 350 | mmu_virtual_psize = MMU_PAGE_64K; |
bf72aeba | 351 | mmu_vmalloc_psize = MMU_PAGE_64K; |
370a908d BH |
352 | if (mmu_linear_psize == MMU_PAGE_4K) |
353 | mmu_linear_psize = MMU_PAGE_64K; | |
bf72aeba PM |
354 | if (cpu_has_feature(CPU_FTR_CI_LARGE_PAGE)) |
355 | mmu_io_psize = MMU_PAGE_64K; | |
356 | else | |
357 | mmu_ci_restrictions = 1; | |
358 | } | |
370a908d | 359 | #endif /* CONFIG_PPC_64K_PAGES */ |
3c726f8d | 360 | |
bf72aeba PM |
361 | printk(KERN_DEBUG "Page orders: linear mapping = %d, " |
362 | "virtual = %d, io = %d\n", | |
3c726f8d | 363 | mmu_psize_defs[mmu_linear_psize].shift, |
bf72aeba PM |
364 | mmu_psize_defs[mmu_virtual_psize].shift, |
365 | mmu_psize_defs[mmu_io_psize].shift); | |
3c726f8d BH |
366 | |
367 | #ifdef CONFIG_HUGETLB_PAGE | |
368 | /* Init large page size. Currently, we pick 16M or 1M depending | |
369 | * on what is available | |
370 | */ | |
371 | if (mmu_psize_defs[MMU_PAGE_16M].shift) | |
4ec161cf | 372 | set_huge_psize(MMU_PAGE_16M); |
7d24f0b8 DG |
373 | /* With 4k/4level pagetables, we can't (for now) cope with a |
374 | * huge page size < PMD_SIZE */ | |
3c726f8d | 375 | else if (mmu_psize_defs[MMU_PAGE_1M].shift) |
4ec161cf | 376 | set_huge_psize(MMU_PAGE_1M); |
3c726f8d BH |
377 | #endif /* CONFIG_HUGETLB_PAGE */ |
378 | } | |
379 | ||
380 | static int __init htab_dt_scan_pftsize(unsigned long node, | |
381 | const char *uname, int depth, | |
382 | void *data) | |
383 | { | |
384 | char *type = of_get_flat_dt_prop(node, "device_type", NULL); | |
385 | u32 *prop; | |
386 | ||
387 | /* We are scanning "cpu" nodes only */ | |
388 | if (type == NULL || strcmp(type, "cpu") != 0) | |
389 | return 0; | |
390 | ||
391 | prop = (u32 *)of_get_flat_dt_prop(node, "ibm,pft-size", NULL); | |
392 | if (prop != NULL) { | |
393 | /* pft_size[0] is the NUMA CEC cookie */ | |
394 | ppc64_pft_size = prop[1]; | |
395 | return 1; | |
1da177e4 | 396 | } |
3c726f8d | 397 | return 0; |
1da177e4 LT |
398 | } |
399 | ||
3c726f8d | 400 | static unsigned long __init htab_get_table_size(void) |
3eac8c69 | 401 | { |
799d6046 | 402 | unsigned long mem_size, rnd_mem_size, pteg_count; |
3eac8c69 | 403 | |
3c726f8d | 404 | /* If hash size isn't already provided by the platform, we try to |
943ffb58 | 405 | * retrieve it from the device-tree. If it's not there neither, we |
3c726f8d | 406 | * calculate it now based on the total RAM size |
3eac8c69 | 407 | */ |
3c726f8d BH |
408 | if (ppc64_pft_size == 0) |
409 | of_scan_flat_dt(htab_dt_scan_pftsize, NULL); | |
3eac8c69 PM |
410 | if (ppc64_pft_size) |
411 | return 1UL << ppc64_pft_size; | |
412 | ||
413 | /* round mem_size up to next power of 2 */ | |
799d6046 PM |
414 | mem_size = lmb_phys_mem_size(); |
415 | rnd_mem_size = 1UL << __ilog2(mem_size); | |
416 | if (rnd_mem_size < mem_size) | |
3eac8c69 PM |
417 | rnd_mem_size <<= 1; |
418 | ||
419 | /* # pages / 2 */ | |
420 | pteg_count = max(rnd_mem_size >> (12 + 1), 1UL << 11); | |
421 | ||
422 | return pteg_count << 7; | |
423 | } | |
424 | ||
54b79248 MK |
425 | #ifdef CONFIG_MEMORY_HOTPLUG |
426 | void create_section_mapping(unsigned long start, unsigned long end) | |
427 | { | |
caf80e57 | 428 | BUG_ON(htab_bolt_mapping(start, end, __pa(start), |
54b79248 | 429 | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_COHERENT | PP_RWXX, |
1189be65 | 430 | mmu_linear_psize, mmu_kernel_ssize)); |
54b79248 MK |
431 | } |
432 | #endif /* CONFIG_MEMORY_HOTPLUG */ | |
433 | ||
7d0daae4 ME |
434 | static inline void make_bl(unsigned int *insn_addr, void *func) |
435 | { | |
436 | unsigned long funcp = *((unsigned long *)func); | |
437 | int offset = funcp - (unsigned long)insn_addr; | |
438 | ||
439 | *insn_addr = (unsigned int)(0x48000001 | (offset & 0x03fffffc)); | |
440 | flush_icache_range((unsigned long)insn_addr, 4+ | |
441 | (unsigned long)insn_addr); | |
442 | } | |
443 | ||
444 | static void __init htab_finish_init(void) | |
445 | { | |
446 | extern unsigned int *htab_call_hpte_insert1; | |
447 | extern unsigned int *htab_call_hpte_insert2; | |
448 | extern unsigned int *htab_call_hpte_remove; | |
449 | extern unsigned int *htab_call_hpte_updatepp; | |
450 | ||
16c2d476 | 451 | #ifdef CONFIG_PPC_HAS_HASH_64K |
7d0daae4 ME |
452 | extern unsigned int *ht64_call_hpte_insert1; |
453 | extern unsigned int *ht64_call_hpte_insert2; | |
454 | extern unsigned int *ht64_call_hpte_remove; | |
455 | extern unsigned int *ht64_call_hpte_updatepp; | |
456 | ||
457 | make_bl(ht64_call_hpte_insert1, ppc_md.hpte_insert); | |
458 | make_bl(ht64_call_hpte_insert2, ppc_md.hpte_insert); | |
459 | make_bl(ht64_call_hpte_remove, ppc_md.hpte_remove); | |
460 | make_bl(ht64_call_hpte_updatepp, ppc_md.hpte_updatepp); | |
5b825831 | 461 | #endif /* CONFIG_PPC_HAS_HASH_64K */ |
7d0daae4 ME |
462 | |
463 | make_bl(htab_call_hpte_insert1, ppc_md.hpte_insert); | |
464 | make_bl(htab_call_hpte_insert2, ppc_md.hpte_insert); | |
465 | make_bl(htab_call_hpte_remove, ppc_md.hpte_remove); | |
466 | make_bl(htab_call_hpte_updatepp, ppc_md.hpte_updatepp); | |
467 | } | |
468 | ||
1da177e4 LT |
469 | void __init htab_initialize(void) |
470 | { | |
337a7128 | 471 | unsigned long table; |
1da177e4 LT |
472 | unsigned long pteg_count; |
473 | unsigned long mode_rw; | |
41d824bf | 474 | unsigned long base = 0, size = 0, limit; |
3c726f8d BH |
475 | int i; |
476 | ||
1da177e4 LT |
477 | extern unsigned long tce_alloc_start, tce_alloc_end; |
478 | ||
479 | DBG(" -> htab_initialize()\n"); | |
480 | ||
1189be65 PM |
481 | /* Initialize segment sizes */ |
482 | htab_init_seg_sizes(); | |
483 | ||
3c726f8d BH |
484 | /* Initialize page sizes */ |
485 | htab_init_page_sizes(); | |
486 | ||
1189be65 PM |
487 | if (cpu_has_feature(CPU_FTR_1T_SEGMENT)) { |
488 | mmu_kernel_ssize = MMU_SEGSIZE_1T; | |
489 | mmu_highuser_ssize = MMU_SEGSIZE_1T; | |
490 | printk(KERN_INFO "Using 1TB segments\n"); | |
491 | } | |
492 | ||
1da177e4 LT |
493 | /* |
494 | * Calculate the required size of the htab. We want the number of | |
495 | * PTEGs to equal one half the number of real pages. | |
496 | */ | |
3c726f8d | 497 | htab_size_bytes = htab_get_table_size(); |
1da177e4 LT |
498 | pteg_count = htab_size_bytes >> 7; |
499 | ||
1da177e4 LT |
500 | htab_hash_mask = pteg_count - 1; |
501 | ||
57cfb814 | 502 | if (firmware_has_feature(FW_FEATURE_LPAR)) { |
1da177e4 LT |
503 | /* Using a hypervisor which owns the htab */ |
504 | htab_address = NULL; | |
505 | _SDR1 = 0; | |
506 | } else { | |
507 | /* Find storage for the HPT. Must be contiguous in | |
41d824bf ME |
508 | * the absolute address space. On cell we want it to be |
509 | * in the first 1 Gig. | |
1da177e4 | 510 | */ |
41d824bf ME |
511 | if (machine_is(cell)) |
512 | limit = 0x40000000; | |
513 | else | |
514 | limit = 0; | |
515 | ||
516 | table = lmb_alloc_base(htab_size_bytes, htab_size_bytes, limit); | |
1da177e4 LT |
517 | |
518 | DBG("Hash table allocated at %lx, size: %lx\n", table, | |
519 | htab_size_bytes); | |
520 | ||
1da177e4 LT |
521 | htab_address = abs_to_virt(table); |
522 | ||
523 | /* htab absolute addr + encoded htabsize */ | |
524 | _SDR1 = table + __ilog2(pteg_count) - 11; | |
525 | ||
526 | /* Initialize the HPT with no entries */ | |
527 | memset((void *)table, 0, htab_size_bytes); | |
799d6046 PM |
528 | |
529 | /* Set SDR1 */ | |
530 | mtspr(SPRN_SDR1, _SDR1); | |
1da177e4 LT |
531 | } |
532 | ||
515bae9c | 533 | mode_rw = _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_COHERENT | PP_RWXX; |
1da177e4 | 534 | |
370a908d BH |
535 | #ifdef CONFIG_DEBUG_PAGEALLOC |
536 | linear_map_hash_count = lmb_end_of_DRAM() >> PAGE_SHIFT; | |
537 | linear_map_hash_slots = __va(lmb_alloc_base(linear_map_hash_count, | |
538 | 1, lmb.rmo_size)); | |
539 | memset(linear_map_hash_slots, 0, linear_map_hash_count); | |
540 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
541 | ||
1da177e4 LT |
542 | /* On U3 based machines, we need to reserve the DART area and |
543 | * _NOT_ map it to avoid cache paradoxes as it's remapped non | |
544 | * cacheable later on | |
545 | */ | |
1da177e4 LT |
546 | |
547 | /* create bolted the linear mapping in the hash table */ | |
548 | for (i=0; i < lmb.memory.cnt; i++) { | |
b5666f70 | 549 | base = (unsigned long)__va(lmb.memory.region[i].base); |
1da177e4 LT |
550 | size = lmb.memory.region[i].size; |
551 | ||
552 | DBG("creating mapping for region: %lx : %lx\n", base, size); | |
553 | ||
554 | #ifdef CONFIG_U3_DART | |
555 | /* Do not map the DART space. Fortunately, it will be aligned | |
3c726f8d BH |
556 | * in such a way that it will not cross two lmb regions and |
557 | * will fit within a single 16Mb page. | |
558 | * The DART space is assumed to be a full 16Mb region even if | |
559 | * we only use 2Mb of that space. We will use more of it later | |
560 | * for AGP GART. We have to use a full 16Mb large page. | |
1da177e4 LT |
561 | */ |
562 | DBG("DART base: %lx\n", dart_tablebase); | |
563 | ||
564 | if (dart_tablebase != 0 && dart_tablebase >= base | |
565 | && dart_tablebase < (base + size)) { | |
caf80e57 | 566 | unsigned long dart_table_end = dart_tablebase + 16 * MB; |
1da177e4 | 567 | if (base != dart_tablebase) |
3c726f8d | 568 | BUG_ON(htab_bolt_mapping(base, dart_tablebase, |
caf80e57 | 569 | __pa(base), mode_rw, |
1189be65 PM |
570 | mmu_linear_psize, |
571 | mmu_kernel_ssize)); | |
caf80e57 | 572 | if ((base + size) > dart_table_end) |
3c726f8d | 573 | BUG_ON(htab_bolt_mapping(dart_tablebase+16*MB, |
caf80e57 ME |
574 | base + size, |
575 | __pa(dart_table_end), | |
3c726f8d | 576 | mode_rw, |
1189be65 PM |
577 | mmu_linear_psize, |
578 | mmu_kernel_ssize)); | |
1da177e4 LT |
579 | continue; |
580 | } | |
581 | #endif /* CONFIG_U3_DART */ | |
caf80e57 | 582 | BUG_ON(htab_bolt_mapping(base, base + size, __pa(base), |
1189be65 | 583 | mode_rw, mmu_linear_psize, mmu_kernel_ssize)); |
3c726f8d | 584 | } |
1da177e4 LT |
585 | |
586 | /* | |
587 | * If we have a memory_limit and we've allocated TCEs then we need to | |
588 | * explicitly map the TCE area at the top of RAM. We also cope with the | |
589 | * case that the TCEs start below memory_limit. | |
590 | * tce_alloc_start/end are 16MB aligned so the mapping should work | |
591 | * for either 4K or 16MB pages. | |
592 | */ | |
593 | if (tce_alloc_start) { | |
b5666f70 ME |
594 | tce_alloc_start = (unsigned long)__va(tce_alloc_start); |
595 | tce_alloc_end = (unsigned long)__va(tce_alloc_end); | |
1da177e4 LT |
596 | |
597 | if (base + size >= tce_alloc_start) | |
598 | tce_alloc_start = base + size + 1; | |
599 | ||
caf80e57 ME |
600 | BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end, |
601 | __pa(tce_alloc_start), mode_rw, | |
1189be65 | 602 | mmu_linear_psize, mmu_kernel_ssize)); |
1da177e4 LT |
603 | } |
604 | ||
7d0daae4 ME |
605 | htab_finish_init(); |
606 | ||
1da177e4 LT |
607 | DBG(" <- htab_initialize()\n"); |
608 | } | |
609 | #undef KB | |
610 | #undef MB | |
1da177e4 | 611 | |
e597cb32 | 612 | void htab_initialize_secondary(void) |
799d6046 | 613 | { |
57cfb814 | 614 | if (!firmware_has_feature(FW_FEATURE_LPAR)) |
799d6046 PM |
615 | mtspr(SPRN_SDR1, _SDR1); |
616 | } | |
617 | ||
1da177e4 LT |
618 | /* |
619 | * Called by asm hashtable.S for doing lazy icache flush | |
620 | */ | |
621 | unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap) | |
622 | { | |
623 | struct page *page; | |
624 | ||
76c8e25b BH |
625 | if (!pfn_valid(pte_pfn(pte))) |
626 | return pp; | |
627 | ||
1da177e4 LT |
628 | page = pte_page(pte); |
629 | ||
630 | /* page is dirty */ | |
631 | if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) { | |
632 | if (trap == 0x400) { | |
633 | __flush_dcache_icache(page_address(page)); | |
634 | set_bit(PG_arch_1, &page->flags); | |
635 | } else | |
3c726f8d | 636 | pp |= HPTE_R_N; |
1da177e4 LT |
637 | } |
638 | return pp; | |
639 | } | |
640 | ||
721151d0 PM |
641 | /* |
642 | * Demote a segment to using 4k pages. | |
643 | * For now this makes the whole process use 4k pages. | |
644 | */ | |
721151d0 | 645 | #ifdef CONFIG_PPC_64K_PAGES |
fa28237c | 646 | void demote_segment_4k(struct mm_struct *mm, unsigned long addr) |
16f1c746 | 647 | { |
721151d0 PM |
648 | if (mm->context.user_psize == MMU_PAGE_4K) |
649 | return; | |
d0f13e3c | 650 | slice_set_user_psize(mm, MMU_PAGE_4K); |
1e57ba8d | 651 | #ifdef CONFIG_SPU_BASE |
721151d0 PM |
652 | spu_flush_all_slbs(mm); |
653 | #endif | |
fa28237c PM |
654 | if (get_paca()->context.user_psize != MMU_PAGE_4K) { |
655 | get_paca()->context = mm->context; | |
656 | slb_flush_and_rebolt(); | |
657 | } | |
721151d0 | 658 | } |
16f1c746 | 659 | #endif /* CONFIG_PPC_64K_PAGES */ |
721151d0 | 660 | |
fa28237c PM |
661 | #ifdef CONFIG_PPC_SUBPAGE_PROT |
662 | /* | |
663 | * This looks up a 2-bit protection code for a 4k subpage of a 64k page. | |
664 | * Userspace sets the subpage permissions using the subpage_prot system call. | |
665 | * | |
666 | * Result is 0: full permissions, _PAGE_RW: read-only, | |
667 | * _PAGE_USER or _PAGE_USER|_PAGE_RW: no access. | |
668 | */ | |
669 | static int subpage_protection(pgd_t *pgdir, unsigned long ea) | |
670 | { | |
671 | struct subpage_prot_table *spt = pgd_subpage_prot(pgdir); | |
672 | u32 spp = 0; | |
673 | u32 **sbpm, *sbpp; | |
674 | ||
675 | if (ea >= spt->maxaddr) | |
676 | return 0; | |
677 | if (ea < 0x100000000) { | |
678 | /* addresses below 4GB use spt->low_prot */ | |
679 | sbpm = spt->low_prot; | |
680 | } else { | |
681 | sbpm = spt->protptrs[ea >> SBP_L3_SHIFT]; | |
682 | if (!sbpm) | |
683 | return 0; | |
684 | } | |
685 | sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)]; | |
686 | if (!sbpp) | |
687 | return 0; | |
688 | spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)]; | |
689 | ||
690 | /* extract 2-bit bitfield for this 4k subpage */ | |
691 | spp >>= 30 - 2 * ((ea >> 12) & 0xf); | |
692 | ||
693 | /* turn 0,1,2,3 into combination of _PAGE_USER and _PAGE_RW */ | |
694 | spp = ((spp & 2) ? _PAGE_USER : 0) | ((spp & 1) ? _PAGE_RW : 0); | |
695 | return spp; | |
696 | } | |
697 | ||
698 | #else /* CONFIG_PPC_SUBPAGE_PROT */ | |
699 | static inline int subpage_protection(pgd_t *pgdir, unsigned long ea) | |
700 | { | |
701 | return 0; | |
702 | } | |
703 | #endif | |
704 | ||
1da177e4 LT |
705 | /* Result code is: |
706 | * 0 - handled | |
707 | * 1 - normal page fault | |
708 | * -1 - critical hash insertion error | |
fa28237c | 709 | * -2 - access not permitted by subpage protection mechanism |
1da177e4 LT |
710 | */ |
711 | int hash_page(unsigned long ea, unsigned long access, unsigned long trap) | |
712 | { | |
713 | void *pgdir; | |
714 | unsigned long vsid; | |
715 | struct mm_struct *mm; | |
716 | pte_t *ptep; | |
1da177e4 | 717 | cpumask_t tmp; |
3c726f8d | 718 | int rc, user_region = 0, local = 0; |
1189be65 | 719 | int psize, ssize; |
1da177e4 | 720 | |
3c726f8d BH |
721 | DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n", |
722 | ea, access, trap); | |
1f8d419e | 723 | |
3c726f8d BH |
724 | if ((ea & ~REGION_MASK) >= PGTABLE_RANGE) { |
725 | DBG_LOW(" out of pgtable range !\n"); | |
726 | return 1; | |
727 | } | |
728 | ||
729 | /* Get region & vsid */ | |
1da177e4 LT |
730 | switch (REGION_ID(ea)) { |
731 | case USER_REGION_ID: | |
732 | user_region = 1; | |
733 | mm = current->mm; | |
3c726f8d BH |
734 | if (! mm) { |
735 | DBG_LOW(" user region with no mm !\n"); | |
1da177e4 | 736 | return 1; |
3c726f8d | 737 | } |
16c2d476 BH |
738 | #ifdef CONFIG_PPC_MM_SLICES |
739 | psize = get_slice_psize(mm, ea); | |
740 | #else | |
bf72aeba | 741 | psize = mm->context.user_psize; |
16c2d476 | 742 | #endif |
1189be65 PM |
743 | ssize = user_segment_size(ea); |
744 | vsid = get_vsid(mm->context.id, ea, ssize); | |
1da177e4 | 745 | break; |
1da177e4 | 746 | case VMALLOC_REGION_ID: |
1da177e4 | 747 | mm = &init_mm; |
1189be65 | 748 | vsid = get_kernel_vsid(ea, mmu_kernel_ssize); |
bf72aeba PM |
749 | if (ea < VMALLOC_END) |
750 | psize = mmu_vmalloc_psize; | |
751 | else | |
752 | psize = mmu_io_psize; | |
1189be65 | 753 | ssize = mmu_kernel_ssize; |
1da177e4 | 754 | break; |
1da177e4 LT |
755 | default: |
756 | /* Not a valid range | |
757 | * Send the problem up to do_page_fault | |
758 | */ | |
759 | return 1; | |
1da177e4 | 760 | } |
3c726f8d | 761 | DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid); |
1da177e4 | 762 | |
3c726f8d | 763 | /* Get pgdir */ |
1da177e4 | 764 | pgdir = mm->pgd; |
1da177e4 LT |
765 | if (pgdir == NULL) |
766 | return 1; | |
767 | ||
3c726f8d | 768 | /* Check CPU locality */ |
1da177e4 LT |
769 | tmp = cpumask_of_cpu(smp_processor_id()); |
770 | if (user_region && cpus_equal(mm->cpu_vm_mask, tmp)) | |
771 | local = 1; | |
772 | ||
d0f13e3c | 773 | #ifdef CONFIG_HUGETLB_PAGE |
3c726f8d | 774 | /* Handle hugepage regions */ |
16c2d476 | 775 | if (HPAGE_SHIFT && psize == mmu_huge_psize) { |
3c726f8d | 776 | DBG_LOW(" -> huge page !\n"); |
cbf52afd | 777 | return hash_huge_page(mm, access, ea, vsid, local, trap); |
3c726f8d | 778 | } |
d0f13e3c | 779 | #endif /* CONFIG_HUGETLB_PAGE */ |
3c726f8d | 780 | |
16c2d476 BH |
781 | #ifndef CONFIG_PPC_64K_PAGES |
782 | /* If we use 4K pages and our psize is not 4K, then we are hitting | |
783 | * a special driver mapping, we need to align the address before | |
784 | * we fetch the PTE | |
785 | */ | |
786 | if (psize != MMU_PAGE_4K) | |
787 | ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1); | |
788 | #endif /* CONFIG_PPC_64K_PAGES */ | |
789 | ||
3c726f8d BH |
790 | /* Get PTE and page size from page tables */ |
791 | ptep = find_linux_pte(pgdir, ea); | |
792 | if (ptep == NULL || !pte_present(*ptep)) { | |
793 | DBG_LOW(" no PTE !\n"); | |
794 | return 1; | |
795 | } | |
796 | ||
797 | #ifndef CONFIG_PPC_64K_PAGES | |
798 | DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep)); | |
799 | #else | |
800 | DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep), | |
801 | pte_val(*(ptep + PTRS_PER_PTE))); | |
802 | #endif | |
803 | /* Pre-check access permissions (will be re-checked atomically | |
804 | * in __hash_page_XX but this pre-check is a fast path | |
805 | */ | |
806 | if (access & ~pte_val(*ptep)) { | |
807 | DBG_LOW(" no access !\n"); | |
808 | return 1; | |
1da177e4 LT |
809 | } |
810 | ||
3c726f8d | 811 | /* Do actual hashing */ |
16c2d476 | 812 | #ifdef CONFIG_PPC_64K_PAGES |
721151d0 PM |
813 | /* If _PAGE_4K_PFN is set, make sure this is a 4k segment */ |
814 | if (pte_val(*ptep) & _PAGE_4K_PFN) { | |
815 | demote_segment_4k(mm, ea); | |
816 | psize = MMU_PAGE_4K; | |
817 | } | |
818 | ||
16f1c746 BH |
819 | /* If this PTE is non-cacheable and we have restrictions on |
820 | * using non cacheable large pages, then we switch to 4k | |
821 | */ | |
822 | if (mmu_ci_restrictions && psize == MMU_PAGE_64K && | |
823 | (pte_val(*ptep) & _PAGE_NO_CACHE)) { | |
824 | if (user_region) { | |
825 | demote_segment_4k(mm, ea); | |
826 | psize = MMU_PAGE_4K; | |
827 | } else if (ea < VMALLOC_END) { | |
828 | /* | |
829 | * some driver did a non-cacheable mapping | |
830 | * in vmalloc space, so switch vmalloc | |
831 | * to 4k pages | |
832 | */ | |
833 | printk(KERN_ALERT "Reducing vmalloc segment " | |
834 | "to 4kB pages because of " | |
835 | "non-cacheable mapping\n"); | |
836 | psize = mmu_vmalloc_psize = MMU_PAGE_4K; | |
1e57ba8d | 837 | #ifdef CONFIG_SPU_BASE |
94b2a439 BH |
838 | spu_flush_all_slbs(mm); |
839 | #endif | |
bf72aeba | 840 | } |
16f1c746 BH |
841 | } |
842 | if (user_region) { | |
843 | if (psize != get_paca()->context.user_psize) { | |
f6ab0b92 | 844 | get_paca()->context = mm->context; |
bf72aeba PM |
845 | slb_flush_and_rebolt(); |
846 | } | |
16f1c746 BH |
847 | } else if (get_paca()->vmalloc_sllp != |
848 | mmu_psize_defs[mmu_vmalloc_psize].sllp) { | |
849 | get_paca()->vmalloc_sllp = | |
850 | mmu_psize_defs[mmu_vmalloc_psize].sllp; | |
67439b76 | 851 | slb_vmalloc_update(); |
bf72aeba | 852 | } |
16c2d476 | 853 | #endif /* CONFIG_PPC_64K_PAGES */ |
16f1c746 | 854 | |
16c2d476 | 855 | #ifdef CONFIG_PPC_HAS_HASH_64K |
bf72aeba | 856 | if (psize == MMU_PAGE_64K) |
1189be65 | 857 | rc = __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize); |
3c726f8d | 858 | else |
16c2d476 | 859 | #endif /* CONFIG_PPC_HAS_HASH_64K */ |
fa28237c PM |
860 | { |
861 | int spp = subpage_protection(pgdir, ea); | |
862 | if (access & spp) | |
863 | rc = -2; | |
864 | else | |
865 | rc = __hash_page_4K(ea, access, vsid, ptep, trap, | |
866 | local, ssize, spp); | |
867 | } | |
3c726f8d BH |
868 | |
869 | #ifndef CONFIG_PPC_64K_PAGES | |
870 | DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep)); | |
871 | #else | |
872 | DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep), | |
873 | pte_val(*(ptep + PTRS_PER_PTE))); | |
874 | #endif | |
875 | DBG_LOW(" -> rc=%d\n", rc); | |
876 | return rc; | |
1da177e4 | 877 | } |
67207b96 | 878 | EXPORT_SYMBOL_GPL(hash_page); |
1da177e4 | 879 | |
3c726f8d BH |
880 | void hash_preload(struct mm_struct *mm, unsigned long ea, |
881 | unsigned long access, unsigned long trap) | |
1da177e4 | 882 | { |
3c726f8d BH |
883 | unsigned long vsid; |
884 | void *pgdir; | |
885 | pte_t *ptep; | |
886 | cpumask_t mask; | |
887 | unsigned long flags; | |
888 | int local = 0; | |
1189be65 | 889 | int ssize; |
3c726f8d | 890 | |
d0f13e3c BH |
891 | BUG_ON(REGION_ID(ea) != USER_REGION_ID); |
892 | ||
893 | #ifdef CONFIG_PPC_MM_SLICES | |
894 | /* We only prefault standard pages for now */ | |
2b02d139 | 895 | if (unlikely(get_slice_psize(mm, ea) != mm->context.user_psize)) |
3c726f8d | 896 | return; |
d0f13e3c | 897 | #endif |
3c726f8d BH |
898 | |
899 | DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx," | |
900 | " trap=%lx\n", mm, mm->pgd, ea, access, trap); | |
1da177e4 | 901 | |
16f1c746 | 902 | /* Get Linux PTE if available */ |
3c726f8d BH |
903 | pgdir = mm->pgd; |
904 | if (pgdir == NULL) | |
905 | return; | |
906 | ptep = find_linux_pte(pgdir, ea); | |
907 | if (!ptep) | |
908 | return; | |
16f1c746 BH |
909 | |
910 | #ifdef CONFIG_PPC_64K_PAGES | |
911 | /* If either _PAGE_4K_PFN or _PAGE_NO_CACHE is set (and we are on | |
912 | * a 64K kernel), then we don't preload, hash_page() will take | |
913 | * care of it once we actually try to access the page. | |
914 | * That way we don't have to duplicate all of the logic for segment | |
915 | * page size demotion here | |
916 | */ | |
917 | if (pte_val(*ptep) & (_PAGE_4K_PFN | _PAGE_NO_CACHE)) | |
918 | return; | |
919 | #endif /* CONFIG_PPC_64K_PAGES */ | |
920 | ||
921 | /* Get VSID */ | |
1189be65 PM |
922 | ssize = user_segment_size(ea); |
923 | vsid = get_vsid(mm->context.id, ea, ssize); | |
3c726f8d | 924 | |
16c2d476 | 925 | /* Hash doesn't like irqs */ |
3c726f8d | 926 | local_irq_save(flags); |
16c2d476 BH |
927 | |
928 | /* Is that local to this CPU ? */ | |
3c726f8d BH |
929 | mask = cpumask_of_cpu(smp_processor_id()); |
930 | if (cpus_equal(mm->cpu_vm_mask, mask)) | |
931 | local = 1; | |
16c2d476 BH |
932 | |
933 | /* Hash it in */ | |
934 | #ifdef CONFIG_PPC_HAS_HASH_64K | |
bf72aeba | 935 | if (mm->context.user_psize == MMU_PAGE_64K) |
1189be65 | 936 | __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize); |
1da177e4 | 937 | else |
5b825831 | 938 | #endif /* CONFIG_PPC_HAS_HASH_64K */ |
fa28237c PM |
939 | __hash_page_4K(ea, access, vsid, ptep, trap, local, ssize, |
940 | subpage_protection(pgdir, ea)); | |
16c2d476 | 941 | |
3c726f8d BH |
942 | local_irq_restore(flags); |
943 | } | |
944 | ||
f6ab0b92 BH |
945 | /* WARNING: This is called from hash_low_64.S, if you change this prototype, |
946 | * do not forget to update the assembly call site ! | |
947 | */ | |
1189be65 PM |
948 | void flush_hash_page(unsigned long va, real_pte_t pte, int psize, int ssize, |
949 | int local) | |
3c726f8d BH |
950 | { |
951 | unsigned long hash, index, shift, hidx, slot; | |
952 | ||
953 | DBG_LOW("flush_hash_page(va=%016x)\n", va); | |
954 | pte_iterate_hashed_subpages(pte, psize, va, index, shift) { | |
1189be65 | 955 | hash = hpt_hash(va, shift, ssize); |
3c726f8d BH |
956 | hidx = __rpte_to_hidx(pte, index); |
957 | if (hidx & _PTEIDX_SECONDARY) | |
958 | hash = ~hash; | |
959 | slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
960 | slot += hidx & _PTEIDX_GROUP_IX; | |
961 | DBG_LOW(" sub %d: hash=%x, hidx=%x\n", index, slot, hidx); | |
1189be65 | 962 | ppc_md.hpte_invalidate(slot, va, psize, ssize, local); |
3c726f8d | 963 | } pte_iterate_hashed_end(); |
1da177e4 LT |
964 | } |
965 | ||
61b1a942 | 966 | void flush_hash_range(unsigned long number, int local) |
1da177e4 | 967 | { |
3c726f8d | 968 | if (ppc_md.flush_hash_range) |
61b1a942 | 969 | ppc_md.flush_hash_range(number, local); |
3c726f8d | 970 | else { |
1da177e4 | 971 | int i; |
61b1a942 BH |
972 | struct ppc64_tlb_batch *batch = |
973 | &__get_cpu_var(ppc64_tlb_batch); | |
1da177e4 LT |
974 | |
975 | for (i = 0; i < number; i++) | |
3c726f8d | 976 | flush_hash_page(batch->vaddr[i], batch->pte[i], |
1189be65 | 977 | batch->psize, batch->ssize, local); |
1da177e4 LT |
978 | } |
979 | } | |
980 | ||
1da177e4 LT |
981 | /* |
982 | * low_hash_fault is called when we the low level hash code failed | |
983 | * to instert a PTE due to an hypervisor error | |
984 | */ | |
fa28237c | 985 | void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc) |
1da177e4 LT |
986 | { |
987 | if (user_mode(regs)) { | |
fa28237c PM |
988 | #ifdef CONFIG_PPC_SUBPAGE_PROT |
989 | if (rc == -2) | |
990 | _exception(SIGSEGV, regs, SEGV_ACCERR, address); | |
991 | else | |
992 | #endif | |
993 | _exception(SIGBUS, regs, BUS_ADRERR, address); | |
994 | } else | |
995 | bad_page_fault(regs, address, SIGBUS); | |
1da177e4 | 996 | } |
370a908d BH |
997 | |
998 | #ifdef CONFIG_DEBUG_PAGEALLOC | |
999 | static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi) | |
1000 | { | |
1189be65 PM |
1001 | unsigned long hash, hpteg; |
1002 | unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize); | |
1003 | unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize); | |
370a908d BH |
1004 | unsigned long mode = _PAGE_ACCESSED | _PAGE_DIRTY | |
1005 | _PAGE_COHERENT | PP_RWXX | HPTE_R_N; | |
1006 | int ret; | |
1007 | ||
1189be65 | 1008 | hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize); |
370a908d BH |
1009 | hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP); |
1010 | ||
1011 | ret = ppc_md.hpte_insert(hpteg, va, __pa(vaddr), | |
1189be65 PM |
1012 | mode, HPTE_V_BOLTED, |
1013 | mmu_linear_psize, mmu_kernel_ssize); | |
370a908d BH |
1014 | BUG_ON (ret < 0); |
1015 | spin_lock(&linear_map_hash_lock); | |
1016 | BUG_ON(linear_map_hash_slots[lmi] & 0x80); | |
1017 | linear_map_hash_slots[lmi] = ret | 0x80; | |
1018 | spin_unlock(&linear_map_hash_lock); | |
1019 | } | |
1020 | ||
1021 | static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi) | |
1022 | { | |
1189be65 PM |
1023 | unsigned long hash, hidx, slot; |
1024 | unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize); | |
1025 | unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize); | |
370a908d | 1026 | |
1189be65 | 1027 | hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize); |
370a908d BH |
1028 | spin_lock(&linear_map_hash_lock); |
1029 | BUG_ON(!(linear_map_hash_slots[lmi] & 0x80)); | |
1030 | hidx = linear_map_hash_slots[lmi] & 0x7f; | |
1031 | linear_map_hash_slots[lmi] = 0; | |
1032 | spin_unlock(&linear_map_hash_lock); | |
1033 | if (hidx & _PTEIDX_SECONDARY) | |
1034 | hash = ~hash; | |
1035 | slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
1036 | slot += hidx & _PTEIDX_GROUP_IX; | |
1189be65 | 1037 | ppc_md.hpte_invalidate(slot, va, mmu_linear_psize, mmu_kernel_ssize, 0); |
370a908d BH |
1038 | } |
1039 | ||
1040 | void kernel_map_pages(struct page *page, int numpages, int enable) | |
1041 | { | |
1042 | unsigned long flags, vaddr, lmi; | |
1043 | int i; | |
1044 | ||
1045 | local_irq_save(flags); | |
1046 | for (i = 0; i < numpages; i++, page++) { | |
1047 | vaddr = (unsigned long)page_address(page); | |
1048 | lmi = __pa(vaddr) >> PAGE_SHIFT; | |
1049 | if (lmi >= linear_map_hash_count) | |
1050 | continue; | |
1051 | if (enable) | |
1052 | kernel_map_linear_page(vaddr, lmi); | |
1053 | else | |
1054 | kernel_unmap_linear_page(vaddr, lmi); | |
1055 | } | |
1056 | local_irq_restore(flags); | |
1057 | } | |
1058 | #endif /* CONFIG_DEBUG_PAGEALLOC */ |