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e05b9b9e ME |
1 | /* |
2 | * Performance counter support for POWER8 processors. | |
3 | * | |
4 | * Copyright 2009 Paul Mackerras, IBM Corporation. | |
5 | * Copyright 2013 Michael Ellerman, IBM Corporation. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version | |
10 | * 2 of the License, or (at your option) any later version. | |
11 | */ | |
12 | ||
c2e37a26 ME |
13 | #define pr_fmt(fmt) "power8-pmu: " fmt |
14 | ||
e05b9b9e ME |
15 | #include <linux/kernel.h> |
16 | #include <linux/perf_event.h> | |
17 | #include <asm/firmware.h> | |
9de5cb0f | 18 | #include <asm/cputable.h> |
e05b9b9e ME |
19 | |
20 | ||
21 | /* | |
22 | * Some power8 event codes. | |
23 | */ | |
24 | #define PM_CYC 0x0001e | |
25 | #define PM_GCT_NOSLOT_CYC 0x100f8 | |
26 | #define PM_CMPLU_STALL 0x4000a | |
27 | #define PM_INST_CMPL 0x00002 | |
28 | #define PM_BRU_FIN 0x10068 | |
29 | #define PM_BR_MPRED_CMPL 0x400f6 | |
30 | ||
2fdd313f ME |
31 | /* All L1 D cache load references counted at finish, gated by reject */ |
32 | #define PM_LD_REF_L1 0x100ee | |
33 | /* Load Missed L1 */ | |
34 | #define PM_LD_MISS_L1 0x3e054 | |
35 | /* Store Missed L1 */ | |
36 | #define PM_ST_MISS_L1 0x300f0 | |
37 | /* L1 cache data prefetches */ | |
38 | #define PM_L1_PREF 0x0d8b8 | |
39 | /* Instruction fetches from L1 */ | |
40 | #define PM_INST_FROM_L1 0x04080 | |
41 | /* Demand iCache Miss */ | |
42 | #define PM_L1_ICACHE_MISS 0x200fd | |
43 | /* Instruction Demand sectors wriittent into IL1 */ | |
44 | #define PM_L1_DEMAND_WRITE 0x0408c | |
45 | /* Instruction prefetch written into IL1 */ | |
46 | #define PM_IC_PREF_WRITE 0x0408e | |
47 | /* The data cache was reloaded from local core's L3 due to a demand load */ | |
48 | #define PM_DATA_FROM_L3 0x4c042 | |
49 | /* Demand LD - L3 Miss (not L2 hit and not L3 hit) */ | |
50 | #define PM_DATA_FROM_L3MISS 0x300fe | |
51 | /* All successful D-side store dispatches for this thread */ | |
52 | #define PM_L2_ST 0x17080 | |
53 | /* All successful D-side store dispatches for this thread that were L2 Miss */ | |
54 | #define PM_L2_ST_MISS 0x17082 | |
55 | /* Total HW L3 prefetches(Load+store) */ | |
56 | #define PM_L3_PREF_ALL 0x4e052 | |
57 | /* Data PTEG reload */ | |
58 | #define PM_DTLB_MISS 0x300fc | |
59 | /* ITLB Reloaded */ | |
60 | #define PM_ITLB_MISS 0x400fc | |
61 | ||
e05b9b9e ME |
62 | |
63 | /* | |
64 | * Raw event encoding for POWER8: | |
65 | * | |
66 | * 60 56 52 48 44 40 36 32 | |
67 | * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | | |
ba969237 ME |
68 | * | | [ ] [ thresh_cmp ] [ thresh_ctl ] |
69 | * | | | | | |
70 | * | | *- IFM (Linux) thresh start/stop OR FAB match -* | |
71 | * | *- BHRB (Linux) | |
72 | * *- EBB (Linux) | |
e05b9b9e ME |
73 | * |
74 | * 28 24 20 16 12 8 4 0 | |
75 | * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | | |
76 | * [ ] [ sample ] [cache] [ pmc ] [unit ] c m [ pmcxsel ] | |
77 | * | | | | | | |
78 | * | | | | *- mark | |
79 | * | | *- L1/L2/L3 cache_sel | | |
80 | * | | | | |
81 | * | *- sampling mode for marked events *- combine | |
82 | * | | |
83 | * *- thresh_sel | |
84 | * | |
85 | * Below uses IBM bit numbering. | |
86 | * | |
87 | * MMCR1[x:y] = unit (PMCxUNIT) | |
88 | * MMCR1[x] = combine (PMCxCOMB) | |
89 | * | |
90 | * if pmc == 3 and unit == 0 and pmcxsel[0:6] == 0b0101011 | |
91 | * # PM_MRK_FAB_RSP_MATCH | |
92 | * MMCR1[20:27] = thresh_ctl (FAB_CRESP_MATCH / FAB_TYPE_MATCH) | |
93 | * else if pmc == 4 and unit == 0xf and pmcxsel[0:6] == 0b0101001 | |
94 | * # PM_MRK_FAB_RSP_MATCH_CYC | |
95 | * MMCR1[20:27] = thresh_ctl (FAB_CRESP_MATCH / FAB_TYPE_MATCH) | |
96 | * else | |
97 | * MMCRA[48:55] = thresh_ctl (THRESH START/END) | |
98 | * | |
99 | * if thresh_sel: | |
100 | * MMCRA[45:47] = thresh_sel | |
101 | * | |
102 | * if thresh_cmp: | |
103 | * MMCRA[22:24] = thresh_cmp[0:2] | |
104 | * MMCRA[25:31] = thresh_cmp[3:9] | |
105 | * | |
106 | * if unit == 6 or unit == 7 | |
107 | * MMCRC[53:55] = cache_sel[1:3] (L2EVENT_SEL) | |
108 | * else if unit == 8 or unit == 9: | |
109 | * if cache_sel[0] == 0: # L3 bank | |
110 | * MMCRC[47:49] = cache_sel[1:3] (L3EVENT_SEL0) | |
111 | * else if cache_sel[0] == 1: | |
112 | * MMCRC[50:51] = cache_sel[2:3] (L3EVENT_SEL1) | |
113 | * else if cache_sel[1]: # L1 event | |
114 | * MMCR1[16] = cache_sel[2] | |
115 | * MMCR1[17] = cache_sel[3] | |
116 | * | |
117 | * if mark: | |
118 | * MMCRA[63] = 1 (SAMPLE_ENABLE) | |
119 | * MMCRA[57:59] = sample[0:2] (RAND_SAMP_ELIG) | |
120 | * MMCRA[61:62] = sample[3:4] (RAND_SAMP_MODE) | |
ba969237 ME |
121 | * |
122 | * if EBB and BHRB: | |
123 | * MMCRA[32:33] = IFM | |
e05b9b9e ME |
124 | * |
125 | */ | |
126 | ||
4df48999 | 127 | #define EVENT_EBB_MASK 1ull |
fb568d76 | 128 | #define EVENT_EBB_SHIFT PERF_EVENT_CONFIG_EBB_SHIFT |
ba969237 ME |
129 | #define EVENT_BHRB_MASK 1ull |
130 | #define EVENT_BHRB_SHIFT 62 | |
131 | #define EVENT_WANTS_BHRB (EVENT_BHRB_MASK << EVENT_BHRB_SHIFT) | |
132 | #define EVENT_IFM_MASK 3ull | |
133 | #define EVENT_IFM_SHIFT 60 | |
e05b9b9e ME |
134 | #define EVENT_THR_CMP_SHIFT 40 /* Threshold CMP value */ |
135 | #define EVENT_THR_CMP_MASK 0x3ff | |
136 | #define EVENT_THR_CTL_SHIFT 32 /* Threshold control value (start/stop) */ | |
137 | #define EVENT_THR_CTL_MASK 0xffull | |
138 | #define EVENT_THR_SEL_SHIFT 29 /* Threshold select value */ | |
139 | #define EVENT_THR_SEL_MASK 0x7 | |
140 | #define EVENT_THRESH_SHIFT 29 /* All threshold bits */ | |
141 | #define EVENT_THRESH_MASK 0x1fffffull | |
142 | #define EVENT_SAMPLE_SHIFT 24 /* Sampling mode & eligibility */ | |
143 | #define EVENT_SAMPLE_MASK 0x1f | |
144 | #define EVENT_CACHE_SEL_SHIFT 20 /* L2/L3 cache select */ | |
145 | #define EVENT_CACHE_SEL_MASK 0xf | |
146 | #define EVENT_IS_L1 (4 << EVENT_CACHE_SEL_SHIFT) | |
147 | #define EVENT_PMC_SHIFT 16 /* PMC number (1-based) */ | |
148 | #define EVENT_PMC_MASK 0xf | |
149 | #define EVENT_UNIT_SHIFT 12 /* Unit */ | |
150 | #define EVENT_UNIT_MASK 0xf | |
151 | #define EVENT_COMBINE_SHIFT 11 /* Combine bit */ | |
152 | #define EVENT_COMBINE_MASK 0x1 | |
153 | #define EVENT_MARKED_SHIFT 8 /* Marked bit */ | |
154 | #define EVENT_MARKED_MASK 0x1 | |
155 | #define EVENT_IS_MARKED (EVENT_MARKED_MASK << EVENT_MARKED_SHIFT) | |
156 | #define EVENT_PSEL_MASK 0xff /* PMCxSEL value */ | |
157 | ||
ba969237 ME |
158 | /* Bits defined by Linux */ |
159 | #define EVENT_LINUX_MASK \ | |
160 | ((EVENT_EBB_MASK << EVENT_EBB_SHIFT) | \ | |
161 | (EVENT_BHRB_MASK << EVENT_BHRB_SHIFT) | \ | |
162 | (EVENT_IFM_MASK << EVENT_IFM_SHIFT)) | |
163 | ||
d8bec4c9 ME |
164 | #define EVENT_VALID_MASK \ |
165 | ((EVENT_THRESH_MASK << EVENT_THRESH_SHIFT) | \ | |
166 | (EVENT_SAMPLE_MASK << EVENT_SAMPLE_SHIFT) | \ | |
167 | (EVENT_CACHE_SEL_MASK << EVENT_CACHE_SEL_SHIFT) | \ | |
168 | (EVENT_PMC_MASK << EVENT_PMC_SHIFT) | \ | |
169 | (EVENT_UNIT_MASK << EVENT_UNIT_SHIFT) | \ | |
170 | (EVENT_COMBINE_MASK << EVENT_COMBINE_SHIFT) | \ | |
171 | (EVENT_MARKED_MASK << EVENT_MARKED_SHIFT) | \ | |
ba969237 | 172 | EVENT_LINUX_MASK | \ |
d8bec4c9 ME |
173 | EVENT_PSEL_MASK) |
174 | ||
b1113557 AK |
175 | /* MMCRA IFM bits - POWER8 */ |
176 | #define POWER8_MMCRA_IFM1 0x0000000040000000UL | |
177 | #define POWER8_MMCRA_IFM2 0x0000000080000000UL | |
178 | #define POWER8_MMCRA_IFM3 0x00000000C0000000UL | |
179 | ||
180 | #define ONLY_PLM \ | |
181 | (PERF_SAMPLE_BRANCH_USER |\ | |
182 | PERF_SAMPLE_BRANCH_KERNEL |\ | |
183 | PERF_SAMPLE_BRANCH_HV) | |
184 | ||
e05b9b9e ME |
185 | /* |
186 | * Layout of constraint bits: | |
187 | * | |
188 | * 60 56 52 48 44 40 36 32 | |
189 | * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | | |
190 | * [ fab_match ] [ thresh_cmp ] [ thresh_ctl ] [ ] | |
191 | * | | |
192 | * thresh_sel -* | |
193 | * | |
194 | * 28 24 20 16 12 8 4 0 | |
195 | * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | | |
ba969237 ME |
196 | * [ ] | [ ] [ sample ] [ ] [6] [5] [4] [3] [2] [1] |
197 | * | | | | | |
198 | * BHRB IFM -* | | | Count of events for each PMC. | |
199 | * EBB -* | | p1, p2, p3, p4, p5, p6. | |
200 | * L1 I/D qualifier -* | | |
e05b9b9e ME |
201 | * nc - number of counters -* |
202 | * | |
203 | * The PMC fields P1..P6, and NC, are adder fields. As we accumulate constraints | |
204 | * we want the low bit of each field to be added to any existing value. | |
205 | * | |
206 | * Everything else is a value field. | |
207 | */ | |
208 | ||
209 | #define CNST_FAB_MATCH_VAL(v) (((v) & EVENT_THR_CTL_MASK) << 56) | |
210 | #define CNST_FAB_MATCH_MASK CNST_FAB_MATCH_VAL(EVENT_THR_CTL_MASK) | |
211 | ||
212 | /* We just throw all the threshold bits into the constraint */ | |
213 | #define CNST_THRESH_VAL(v) (((v) & EVENT_THRESH_MASK) << 32) | |
214 | #define CNST_THRESH_MASK CNST_THRESH_VAL(EVENT_THRESH_MASK) | |
215 | ||
4df48999 ME |
216 | #define CNST_EBB_VAL(v) (((v) & EVENT_EBB_MASK) << 24) |
217 | #define CNST_EBB_MASK CNST_EBB_VAL(EVENT_EBB_MASK) | |
218 | ||
ba969237 ME |
219 | #define CNST_IFM_VAL(v) (((v) & EVENT_IFM_MASK) << 25) |
220 | #define CNST_IFM_MASK CNST_IFM_VAL(EVENT_IFM_MASK) | |
221 | ||
e05b9b9e ME |
222 | #define CNST_L1_QUAL_VAL(v) (((v) & 3) << 22) |
223 | #define CNST_L1_QUAL_MASK CNST_L1_QUAL_VAL(3) | |
224 | ||
225 | #define CNST_SAMPLE_VAL(v) (((v) & EVENT_SAMPLE_MASK) << 16) | |
226 | #define CNST_SAMPLE_MASK CNST_SAMPLE_VAL(EVENT_SAMPLE_MASK) | |
227 | ||
228 | /* | |
229 | * For NC we are counting up to 4 events. This requires three bits, and we need | |
230 | * the fifth event to overflow and set the 4th bit. To achieve that we bias the | |
231 | * fields by 3 in test_adder. | |
232 | */ | |
233 | #define CNST_NC_SHIFT 12 | |
234 | #define CNST_NC_VAL (1 << CNST_NC_SHIFT) | |
235 | #define CNST_NC_MASK (8 << CNST_NC_SHIFT) | |
236 | #define POWER8_TEST_ADDER (3 << CNST_NC_SHIFT) | |
237 | ||
238 | /* | |
239 | * For the per-PMC fields we have two bits. The low bit is added, so if two | |
240 | * events ask for the same PMC the sum will overflow, setting the high bit, | |
241 | * indicating an error. So our mask sets the high bit. | |
242 | */ | |
243 | #define CNST_PMC_SHIFT(pmc) ((pmc - 1) * 2) | |
244 | #define CNST_PMC_VAL(pmc) (1 << CNST_PMC_SHIFT(pmc)) | |
245 | #define CNST_PMC_MASK(pmc) (2 << CNST_PMC_SHIFT(pmc)) | |
246 | ||
247 | /* Our add_fields is defined as: */ | |
248 | #define POWER8_ADD_FIELDS \ | |
249 | CNST_PMC_VAL(1) | CNST_PMC_VAL(2) | CNST_PMC_VAL(3) | \ | |
250 | CNST_PMC_VAL(4) | CNST_PMC_VAL(5) | CNST_PMC_VAL(6) | CNST_NC_VAL | |
251 | ||
252 | ||
253 | /* Bits in MMCR1 for POWER8 */ | |
254 | #define MMCR1_UNIT_SHIFT(pmc) (60 - (4 * ((pmc) - 1))) | |
255 | #define MMCR1_COMBINE_SHIFT(pmc) (35 - ((pmc) - 1)) | |
256 | #define MMCR1_PMCSEL_SHIFT(pmc) (24 - (((pmc) - 1)) * 8) | |
a53b27b3 | 257 | #define MMCR1_FAB_SHIFT 36 |
e05b9b9e ME |
258 | #define MMCR1_DC_QUAL_SHIFT 47 |
259 | #define MMCR1_IC_QUAL_SHIFT 46 | |
260 | ||
261 | /* Bits in MMCRA for POWER8 */ | |
262 | #define MMCRA_SAMP_MODE_SHIFT 1 | |
263 | #define MMCRA_SAMP_ELIG_SHIFT 4 | |
264 | #define MMCRA_THR_CTL_SHIFT 8 | |
265 | #define MMCRA_THR_SEL_SHIFT 16 | |
266 | #define MMCRA_THR_CMP_SHIFT 32 | |
267 | #define MMCRA_SDAR_MODE_TLB (1ull << 42) | |
ba969237 | 268 | #define MMCRA_IFM_SHIFT 30 |
e05b9b9e | 269 | |
9de5cb0f ME |
270 | /* Bits in MMCR2 for POWER8 */ |
271 | #define MMCR2_FCS(pmc) (1ull << (63 - (((pmc) - 1) * 9))) | |
272 | #define MMCR2_FCP(pmc) (1ull << (62 - (((pmc) - 1) * 9))) | |
273 | #define MMCR2_FCH(pmc) (1ull << (57 - (((pmc) - 1) * 9))) | |
274 | ||
e05b9b9e ME |
275 | |
276 | static inline bool event_is_fab_match(u64 event) | |
277 | { | |
278 | /* Only check pmc, unit and pmcxsel, ignore the edge bit (0) */ | |
279 | event &= 0xff0fe; | |
280 | ||
281 | /* PM_MRK_FAB_RSP_MATCH & PM_MRK_FAB_RSP_MATCH_CYC */ | |
282 | return (event == 0x30056 || event == 0x4f052); | |
283 | } | |
284 | ||
285 | static int power8_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp) | |
286 | { | |
4df48999 | 287 | unsigned int unit, pmc, cache, ebb; |
e05b9b9e ME |
288 | unsigned long mask, value; |
289 | ||
290 | mask = value = 0; | |
291 | ||
d8bec4c9 ME |
292 | if (event & ~EVENT_VALID_MASK) |
293 | return -1; | |
294 | ||
4df48999 ME |
295 | pmc = (event >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK; |
296 | unit = (event >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK; | |
297 | cache = (event >> EVENT_CACHE_SEL_SHIFT) & EVENT_CACHE_SEL_MASK; | |
fb568d76 | 298 | ebb = (event >> EVENT_EBB_SHIFT) & EVENT_EBB_MASK; |
4df48999 | 299 | |
e05b9b9e | 300 | if (pmc) { |
7cbba630 ME |
301 | u64 base_event; |
302 | ||
e05b9b9e ME |
303 | if (pmc > 6) |
304 | return -1; | |
305 | ||
7cbba630 | 306 | /* Ignore Linux defined bits when checking event below */ |
ba969237 | 307 | base_event = event & ~EVENT_LINUX_MASK; |
e05b9b9e | 308 | |
7cbba630 | 309 | if (pmc >= 5 && base_event != 0x500fa && base_event != 0x600f4) |
e05b9b9e | 310 | return -1; |
7cbba630 ME |
311 | |
312 | mask |= CNST_PMC_MASK(pmc); | |
313 | value |= CNST_PMC_VAL(pmc); | |
e05b9b9e ME |
314 | } |
315 | ||
316 | if (pmc <= 4) { | |
317 | /* | |
318 | * Add to number of counters in use. Note this includes events with | |
319 | * a PMC of 0 - they still need a PMC, it's just assigned later. | |
320 | * Don't count events on PMC 5 & 6, there is only one valid event | |
321 | * on each of those counters, and they are handled above. | |
322 | */ | |
323 | mask |= CNST_NC_MASK; | |
324 | value |= CNST_NC_VAL; | |
325 | } | |
326 | ||
327 | if (unit >= 6 && unit <= 9) { | |
328 | /* | |
329 | * L2/L3 events contain a cache selector field, which is | |
330 | * supposed to be programmed into MMCRC. However MMCRC is only | |
331 | * HV writable, and there is no API for guest kernels to modify | |
332 | * it. The solution is for the hypervisor to initialise the | |
333 | * field to zeroes, and for us to only ever allow events that | |
e9aaac1a ME |
334 | * have a cache selector of zero. The bank selector (bit 3) is |
335 | * irrelevant, as long as the rest of the value is 0. | |
e05b9b9e | 336 | */ |
e9aaac1a | 337 | if (cache & 0x7) |
e05b9b9e ME |
338 | return -1; |
339 | ||
340 | } else if (event & EVENT_IS_L1) { | |
341 | mask |= CNST_L1_QUAL_MASK; | |
342 | value |= CNST_L1_QUAL_VAL(cache); | |
343 | } | |
344 | ||
345 | if (event & EVENT_IS_MARKED) { | |
346 | mask |= CNST_SAMPLE_MASK; | |
347 | value |= CNST_SAMPLE_VAL(event >> EVENT_SAMPLE_SHIFT); | |
348 | } | |
349 | ||
350 | /* | |
351 | * Special case for PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC, | |
352 | * the threshold control bits are used for the match value. | |
353 | */ | |
354 | if (event_is_fab_match(event)) { | |
355 | mask |= CNST_FAB_MATCH_MASK; | |
356 | value |= CNST_FAB_MATCH_VAL(event >> EVENT_THR_CTL_SHIFT); | |
357 | } else { | |
358 | /* | |
359 | * Check the mantissa upper two bits are not zero, unless the | |
360 | * exponent is also zero. See the THRESH_CMP_MANTISSA doc. | |
361 | */ | |
362 | unsigned int cmp, exp; | |
363 | ||
364 | cmp = (event >> EVENT_THR_CMP_SHIFT) & EVENT_THR_CMP_MASK; | |
365 | exp = cmp >> 7; | |
366 | ||
367 | if (exp && (cmp & 0x60) == 0) | |
368 | return -1; | |
369 | ||
370 | mask |= CNST_THRESH_MASK; | |
371 | value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT); | |
372 | } | |
373 | ||
4df48999 ME |
374 | if (!pmc && ebb) |
375 | /* EBB events must specify the PMC */ | |
376 | return -1; | |
377 | ||
ba969237 ME |
378 | if (event & EVENT_WANTS_BHRB) { |
379 | if (!ebb) | |
380 | /* Only EBB events can request BHRB */ | |
381 | return -1; | |
382 | ||
383 | mask |= CNST_IFM_MASK; | |
384 | value |= CNST_IFM_VAL(event >> EVENT_IFM_SHIFT); | |
385 | } | |
386 | ||
4df48999 ME |
387 | /* |
388 | * All events must agree on EBB, either all request it or none. | |
389 | * EBB events are pinned & exclusive, so this should never actually | |
390 | * hit, but we leave it as a fallback in case. | |
391 | */ | |
392 | mask |= CNST_EBB_VAL(ebb); | |
393 | value |= CNST_EBB_MASK; | |
394 | ||
e05b9b9e ME |
395 | *maskp = mask; |
396 | *valp = value; | |
397 | ||
398 | return 0; | |
399 | } | |
400 | ||
401 | static int power8_compute_mmcr(u64 event[], int n_ev, | |
8abd818f ME |
402 | unsigned int hwc[], unsigned long mmcr[], |
403 | struct perf_event *pevents[]) | |
e05b9b9e | 404 | { |
9de5cb0f | 405 | unsigned long mmcra, mmcr1, mmcr2, unit, combine, psel, cache, val; |
e05b9b9e ME |
406 | unsigned int pmc, pmc_inuse; |
407 | int i; | |
408 | ||
409 | pmc_inuse = 0; | |
410 | ||
411 | /* First pass to count resource use */ | |
412 | for (i = 0; i < n_ev; ++i) { | |
413 | pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK; | |
414 | if (pmc) | |
415 | pmc_inuse |= 1 << pmc; | |
416 | } | |
417 | ||
418 | /* In continous sampling mode, update SDAR on TLB miss */ | |
419 | mmcra = MMCRA_SDAR_MODE_TLB; | |
9de5cb0f | 420 | mmcr1 = mmcr2 = 0; |
e05b9b9e ME |
421 | |
422 | /* Second pass: assign PMCs, set all MMCR1 fields */ | |
423 | for (i = 0; i < n_ev; ++i) { | |
424 | pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK; | |
425 | unit = (event[i] >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK; | |
426 | combine = (event[i] >> EVENT_COMBINE_SHIFT) & EVENT_COMBINE_MASK; | |
427 | psel = event[i] & EVENT_PSEL_MASK; | |
428 | ||
429 | if (!pmc) { | |
430 | for (pmc = 1; pmc <= 4; ++pmc) { | |
431 | if (!(pmc_inuse & (1 << pmc))) | |
432 | break; | |
433 | } | |
434 | ||
435 | pmc_inuse |= 1 << pmc; | |
436 | } | |
437 | ||
438 | if (pmc <= 4) { | |
439 | mmcr1 |= unit << MMCR1_UNIT_SHIFT(pmc); | |
440 | mmcr1 |= combine << MMCR1_COMBINE_SHIFT(pmc); | |
441 | mmcr1 |= psel << MMCR1_PMCSEL_SHIFT(pmc); | |
442 | } | |
443 | ||
444 | if (event[i] & EVENT_IS_L1) { | |
445 | cache = event[i] >> EVENT_CACHE_SEL_SHIFT; | |
446 | mmcr1 |= (cache & 1) << MMCR1_IC_QUAL_SHIFT; | |
447 | cache >>= 1; | |
448 | mmcr1 |= (cache & 1) << MMCR1_DC_QUAL_SHIFT; | |
449 | } | |
450 | ||
451 | if (event[i] & EVENT_IS_MARKED) { | |
452 | mmcra |= MMCRA_SAMPLE_ENABLE; | |
453 | ||
454 | val = (event[i] >> EVENT_SAMPLE_SHIFT) & EVENT_SAMPLE_MASK; | |
455 | if (val) { | |
456 | mmcra |= (val & 3) << MMCRA_SAMP_MODE_SHIFT; | |
457 | mmcra |= (val >> 2) << MMCRA_SAMP_ELIG_SHIFT; | |
458 | } | |
459 | } | |
460 | ||
461 | /* | |
462 | * PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC, | |
463 | * the threshold bits are used for the match value. | |
464 | */ | |
465 | if (event_is_fab_match(event[i])) { | |
a53b27b3 ME |
466 | mmcr1 |= ((event[i] >> EVENT_THR_CTL_SHIFT) & |
467 | EVENT_THR_CTL_MASK) << MMCR1_FAB_SHIFT; | |
e05b9b9e ME |
468 | } else { |
469 | val = (event[i] >> EVENT_THR_CTL_SHIFT) & EVENT_THR_CTL_MASK; | |
470 | mmcra |= val << MMCRA_THR_CTL_SHIFT; | |
471 | val = (event[i] >> EVENT_THR_SEL_SHIFT) & EVENT_THR_SEL_MASK; | |
472 | mmcra |= val << MMCRA_THR_SEL_SHIFT; | |
473 | val = (event[i] >> EVENT_THR_CMP_SHIFT) & EVENT_THR_CMP_MASK; | |
474 | mmcra |= val << MMCRA_THR_CMP_SHIFT; | |
475 | } | |
476 | ||
ba969237 ME |
477 | if (event[i] & EVENT_WANTS_BHRB) { |
478 | val = (event[i] >> EVENT_IFM_SHIFT) & EVENT_IFM_MASK; | |
479 | mmcra |= val << MMCRA_IFM_SHIFT; | |
480 | } | |
481 | ||
9de5cb0f ME |
482 | if (pevents[i]->attr.exclude_user) |
483 | mmcr2 |= MMCR2_FCP(pmc); | |
484 | ||
485 | if (pevents[i]->attr.exclude_hv) | |
486 | mmcr2 |= MMCR2_FCH(pmc); | |
487 | ||
488 | if (pevents[i]->attr.exclude_kernel) { | |
489 | if (cpu_has_feature(CPU_FTR_HVMODE)) | |
490 | mmcr2 |= MMCR2_FCH(pmc); | |
491 | else | |
492 | mmcr2 |= MMCR2_FCS(pmc); | |
493 | } | |
494 | ||
e05b9b9e ME |
495 | hwc[i] = pmc - 1; |
496 | } | |
497 | ||
498 | /* Return MMCRx values */ | |
499 | mmcr[0] = 0; | |
500 | ||
501 | /* pmc_inuse is 1-based */ | |
502 | if (pmc_inuse & 2) | |
503 | mmcr[0] = MMCR0_PMC1CE; | |
504 | ||
505 | if (pmc_inuse & 0x7c) | |
506 | mmcr[0] |= MMCR0_PMCjCE; | |
507 | ||
7a7a41f9 ME |
508 | /* If we're not using PMC 5 or 6, freeze them */ |
509 | if (!(pmc_inuse & 0x60)) | |
510 | mmcr[0] |= MMCR0_FC56; | |
511 | ||
e05b9b9e ME |
512 | mmcr[1] = mmcr1; |
513 | mmcr[2] = mmcra; | |
9de5cb0f | 514 | mmcr[3] = mmcr2; |
e05b9b9e ME |
515 | |
516 | return 0; | |
517 | } | |
518 | ||
519 | #define MAX_ALT 2 | |
520 | ||
521 | /* Table of alternatives, sorted by column 0 */ | |
522 | static const unsigned int event_alternatives[][MAX_ALT] = { | |
523 | { 0x10134, 0x301e2 }, /* PM_MRK_ST_CMPL */ | |
524 | { 0x10138, 0x40138 }, /* PM_BR_MRK_2PATH */ | |
525 | { 0x18082, 0x3e05e }, /* PM_L3_CO_MEPF */ | |
526 | { 0x1d14e, 0x401e8 }, /* PM_MRK_DATA_FROM_L2MISS */ | |
527 | { 0x1e054, 0x4000a }, /* PM_CMPLU_STALL */ | |
528 | { 0x20036, 0x40036 }, /* PM_BR_2PATH */ | |
529 | { 0x200f2, 0x300f2 }, /* PM_INST_DISP */ | |
530 | { 0x200f4, 0x600f4 }, /* PM_RUN_CYC */ | |
531 | { 0x2013c, 0x3012e }, /* PM_MRK_FILT_MATCH */ | |
532 | { 0x3e054, 0x400f0 }, /* PM_LD_MISS_L1 */ | |
533 | { 0x400fa, 0x500fa }, /* PM_RUN_INST_CMPL */ | |
534 | }; | |
535 | ||
536 | /* | |
537 | * Scan the alternatives table for a match and return the | |
538 | * index into the alternatives table if found, else -1. | |
539 | */ | |
540 | static int find_alternative(u64 event) | |
541 | { | |
542 | int i, j; | |
543 | ||
544 | for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) { | |
545 | if (event < event_alternatives[i][0]) | |
546 | break; | |
547 | ||
548 | for (j = 0; j < MAX_ALT && event_alternatives[i][j]; ++j) | |
549 | if (event == event_alternatives[i][j]) | |
550 | return i; | |
551 | } | |
552 | ||
553 | return -1; | |
554 | } | |
555 | ||
556 | static int power8_get_alternatives(u64 event, unsigned int flags, u64 alt[]) | |
557 | { | |
558 | int i, j, num_alt = 0; | |
559 | u64 alt_event; | |
560 | ||
561 | alt[num_alt++] = event; | |
562 | ||
563 | i = find_alternative(event); | |
564 | if (i >= 0) { | |
565 | /* Filter out the original event, it's already in alt[0] */ | |
566 | for (j = 0; j < MAX_ALT; ++j) { | |
567 | alt_event = event_alternatives[i][j]; | |
568 | if (alt_event && alt_event != event) | |
569 | alt[num_alt++] = alt_event; | |
570 | } | |
571 | } | |
572 | ||
573 | if (flags & PPMU_ONLY_COUNT_RUN) { | |
574 | /* | |
575 | * We're only counting in RUN state, so PM_CYC is equivalent to | |
576 | * PM_RUN_CYC and PM_INST_CMPL === PM_RUN_INST_CMPL. | |
577 | */ | |
578 | j = num_alt; | |
579 | for (i = 0; i < num_alt; ++i) { | |
580 | switch (alt[i]) { | |
581 | case 0x1e: /* PM_CYC */ | |
582 | alt[j++] = 0x600f4; /* PM_RUN_CYC */ | |
583 | break; | |
584 | case 0x600f4: /* PM_RUN_CYC */ | |
585 | alt[j++] = 0x1e; | |
586 | break; | |
587 | case 0x2: /* PM_PPC_CMPL */ | |
588 | alt[j++] = 0x500fa; /* PM_RUN_INST_CMPL */ | |
589 | break; | |
590 | case 0x500fa: /* PM_RUN_INST_CMPL */ | |
591 | alt[j++] = 0x2; /* PM_PPC_CMPL */ | |
592 | break; | |
593 | } | |
594 | } | |
595 | num_alt = j; | |
596 | } | |
597 | ||
598 | return num_alt; | |
599 | } | |
600 | ||
601 | static void power8_disable_pmc(unsigned int pmc, unsigned long mmcr[]) | |
602 | { | |
603 | if (pmc <= 3) | |
604 | mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SHIFT(pmc + 1)); | |
605 | } | |
606 | ||
607 | PMU_FORMAT_ATTR(event, "config:0-49"); | |
608 | PMU_FORMAT_ATTR(pmcxsel, "config:0-7"); | |
609 | PMU_FORMAT_ATTR(mark, "config:8"); | |
610 | PMU_FORMAT_ATTR(combine, "config:11"); | |
611 | PMU_FORMAT_ATTR(unit, "config:12-15"); | |
612 | PMU_FORMAT_ATTR(pmc, "config:16-19"); | |
613 | PMU_FORMAT_ATTR(cache_sel, "config:20-23"); | |
614 | PMU_FORMAT_ATTR(sample_mode, "config:24-28"); | |
615 | PMU_FORMAT_ATTR(thresh_sel, "config:29-31"); | |
616 | PMU_FORMAT_ATTR(thresh_stop, "config:32-35"); | |
617 | PMU_FORMAT_ATTR(thresh_start, "config:36-39"); | |
618 | PMU_FORMAT_ATTR(thresh_cmp, "config:40-49"); | |
619 | ||
620 | static struct attribute *power8_pmu_format_attr[] = { | |
621 | &format_attr_event.attr, | |
622 | &format_attr_pmcxsel.attr, | |
623 | &format_attr_mark.attr, | |
624 | &format_attr_combine.attr, | |
625 | &format_attr_unit.attr, | |
626 | &format_attr_pmc.attr, | |
627 | &format_attr_cache_sel.attr, | |
628 | &format_attr_sample_mode.attr, | |
629 | &format_attr_thresh_sel.attr, | |
630 | &format_attr_thresh_stop.attr, | |
631 | &format_attr_thresh_start.attr, | |
632 | &format_attr_thresh_cmp.attr, | |
633 | NULL, | |
634 | }; | |
635 | ||
636 | struct attribute_group power8_pmu_format_group = { | |
637 | .name = "format", | |
638 | .attrs = power8_pmu_format_attr, | |
639 | }; | |
640 | ||
641 | static const struct attribute_group *power8_pmu_attr_groups[] = { | |
642 | &power8_pmu_format_group, | |
643 | NULL, | |
644 | }; | |
645 | ||
646 | static int power8_generic_events[] = { | |
647 | [PERF_COUNT_HW_CPU_CYCLES] = PM_CYC, | |
648 | [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PM_GCT_NOSLOT_CYC, | |
649 | [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = PM_CMPLU_STALL, | |
650 | [PERF_COUNT_HW_INSTRUCTIONS] = PM_INST_CMPL, | |
651 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PM_BRU_FIN, | |
652 | [PERF_COUNT_HW_BRANCH_MISSES] = PM_BR_MPRED_CMPL, | |
2fdd313f ME |
653 | [PERF_COUNT_HW_CACHE_REFERENCES] = PM_LD_REF_L1, |
654 | [PERF_COUNT_HW_CACHE_MISSES] = PM_LD_MISS_L1, | |
e05b9b9e ME |
655 | }; |
656 | ||
b1113557 AK |
657 | static u64 power8_bhrb_filter_map(u64 branch_sample_type) |
658 | { | |
659 | u64 pmu_bhrb_filter = 0; | |
b1113557 | 660 | |
7689bdca | 661 | /* BHRB and regular PMU events share the same privilege state |
b1113557 | 662 | * filter configuration. BHRB is always recorded along with a |
7689bdca AK |
663 | * regular PMU event. As the privilege state filter is handled |
664 | * in the basic PMC configuration of the accompanying regular | |
665 | * PMU event, we ignore any separate BHRB specific request. | |
b1113557 | 666 | */ |
b1113557 AK |
667 | |
668 | /* No branch filter requested */ | |
669 | if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY) | |
670 | return pmu_bhrb_filter; | |
671 | ||
672 | /* Invalid branch filter options - HW does not support */ | |
673 | if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_RETURN) | |
674 | return -1; | |
675 | ||
676 | if (branch_sample_type & PERF_SAMPLE_BRANCH_IND_CALL) | |
677 | return -1; | |
678 | ||
679 | if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_CALL) { | |
680 | pmu_bhrb_filter |= POWER8_MMCRA_IFM1; | |
681 | return pmu_bhrb_filter; | |
682 | } | |
683 | ||
684 | /* Every thing else is unsupported */ | |
685 | return -1; | |
686 | } | |
687 | ||
688 | static void power8_config_bhrb(u64 pmu_bhrb_filter) | |
689 | { | |
690 | /* Enable BHRB filter in PMU */ | |
691 | mtspr(SPRN_MMCRA, (mfspr(SPRN_MMCRA) | pmu_bhrb_filter)); | |
692 | } | |
693 | ||
2fdd313f ME |
694 | #define C(x) PERF_COUNT_HW_CACHE_##x |
695 | ||
696 | /* | |
697 | * Table of generalized cache-related events. | |
698 | * 0 means not supported, -1 means nonsensical, other values | |
699 | * are event codes. | |
700 | */ | |
701 | static int power8_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { | |
702 | [ C(L1D) ] = { | |
703 | [ C(OP_READ) ] = { | |
704 | [ C(RESULT_ACCESS) ] = PM_LD_REF_L1, | |
705 | [ C(RESULT_MISS) ] = PM_LD_MISS_L1, | |
706 | }, | |
707 | [ C(OP_WRITE) ] = { | |
708 | [ C(RESULT_ACCESS) ] = 0, | |
709 | [ C(RESULT_MISS) ] = PM_ST_MISS_L1, | |
710 | }, | |
711 | [ C(OP_PREFETCH) ] = { | |
712 | [ C(RESULT_ACCESS) ] = PM_L1_PREF, | |
713 | [ C(RESULT_MISS) ] = 0, | |
714 | }, | |
715 | }, | |
716 | [ C(L1I) ] = { | |
717 | [ C(OP_READ) ] = { | |
718 | [ C(RESULT_ACCESS) ] = PM_INST_FROM_L1, | |
719 | [ C(RESULT_MISS) ] = PM_L1_ICACHE_MISS, | |
720 | }, | |
721 | [ C(OP_WRITE) ] = { | |
722 | [ C(RESULT_ACCESS) ] = PM_L1_DEMAND_WRITE, | |
723 | [ C(RESULT_MISS) ] = -1, | |
724 | }, | |
725 | [ C(OP_PREFETCH) ] = { | |
726 | [ C(RESULT_ACCESS) ] = PM_IC_PREF_WRITE, | |
727 | [ C(RESULT_MISS) ] = 0, | |
728 | }, | |
729 | }, | |
730 | [ C(LL) ] = { | |
731 | [ C(OP_READ) ] = { | |
732 | [ C(RESULT_ACCESS) ] = PM_DATA_FROM_L3, | |
733 | [ C(RESULT_MISS) ] = PM_DATA_FROM_L3MISS, | |
734 | }, | |
735 | [ C(OP_WRITE) ] = { | |
736 | [ C(RESULT_ACCESS) ] = PM_L2_ST, | |
737 | [ C(RESULT_MISS) ] = PM_L2_ST_MISS, | |
738 | }, | |
739 | [ C(OP_PREFETCH) ] = { | |
740 | [ C(RESULT_ACCESS) ] = PM_L3_PREF_ALL, | |
741 | [ C(RESULT_MISS) ] = 0, | |
742 | }, | |
743 | }, | |
744 | [ C(DTLB) ] = { | |
745 | [ C(OP_READ) ] = { | |
746 | [ C(RESULT_ACCESS) ] = 0, | |
747 | [ C(RESULT_MISS) ] = PM_DTLB_MISS, | |
748 | }, | |
749 | [ C(OP_WRITE) ] = { | |
750 | [ C(RESULT_ACCESS) ] = -1, | |
751 | [ C(RESULT_MISS) ] = -1, | |
752 | }, | |
753 | [ C(OP_PREFETCH) ] = { | |
754 | [ C(RESULT_ACCESS) ] = -1, | |
755 | [ C(RESULT_MISS) ] = -1, | |
756 | }, | |
757 | }, | |
758 | [ C(ITLB) ] = { | |
759 | [ C(OP_READ) ] = { | |
760 | [ C(RESULT_ACCESS) ] = 0, | |
761 | [ C(RESULT_MISS) ] = PM_ITLB_MISS, | |
762 | }, | |
763 | [ C(OP_WRITE) ] = { | |
764 | [ C(RESULT_ACCESS) ] = -1, | |
765 | [ C(RESULT_MISS) ] = -1, | |
766 | }, | |
767 | [ C(OP_PREFETCH) ] = { | |
768 | [ C(RESULT_ACCESS) ] = -1, | |
769 | [ C(RESULT_MISS) ] = -1, | |
770 | }, | |
771 | }, | |
772 | [ C(BPU) ] = { | |
773 | [ C(OP_READ) ] = { | |
774 | [ C(RESULT_ACCESS) ] = PM_BRU_FIN, | |
775 | [ C(RESULT_MISS) ] = PM_BR_MPRED_CMPL, | |
776 | }, | |
777 | [ C(OP_WRITE) ] = { | |
778 | [ C(RESULT_ACCESS) ] = -1, | |
779 | [ C(RESULT_MISS) ] = -1, | |
780 | }, | |
781 | [ C(OP_PREFETCH) ] = { | |
782 | [ C(RESULT_ACCESS) ] = -1, | |
783 | [ C(RESULT_MISS) ] = -1, | |
784 | }, | |
785 | }, | |
786 | [ C(NODE) ] = { | |
787 | [ C(OP_READ) ] = { | |
788 | [ C(RESULT_ACCESS) ] = -1, | |
789 | [ C(RESULT_MISS) ] = -1, | |
790 | }, | |
791 | [ C(OP_WRITE) ] = { | |
792 | [ C(RESULT_ACCESS) ] = -1, | |
793 | [ C(RESULT_MISS) ] = -1, | |
794 | }, | |
795 | [ C(OP_PREFETCH) ] = { | |
796 | [ C(RESULT_ACCESS) ] = -1, | |
797 | [ C(RESULT_MISS) ] = -1, | |
798 | }, | |
799 | }, | |
800 | }; | |
801 | ||
802 | #undef C | |
803 | ||
e05b9b9e ME |
804 | static struct power_pmu power8_pmu = { |
805 | .name = "POWER8", | |
806 | .n_counter = 6, | |
807 | .max_alternatives = MAX_ALT + 1, | |
808 | .add_fields = POWER8_ADD_FIELDS, | |
809 | .test_adder = POWER8_TEST_ADDER, | |
810 | .compute_mmcr = power8_compute_mmcr, | |
b1113557 AK |
811 | .config_bhrb = power8_config_bhrb, |
812 | .bhrb_filter_map = power8_bhrb_filter_map, | |
e05b9b9e ME |
813 | .get_constraint = power8_get_constraint, |
814 | .get_alternatives = power8_get_alternatives, | |
815 | .disable_pmc = power8_disable_pmc, | |
4d9690dd | 816 | .flags = PPMU_HAS_SSLOT | PPMU_HAS_SIER | PPMU_ARCH_207S, |
e05b9b9e ME |
817 | .n_generic = ARRAY_SIZE(power8_generic_events), |
818 | .generic_events = power8_generic_events, | |
2fdd313f | 819 | .cache_events = &power8_cache_events, |
e05b9b9e | 820 | .attr_groups = power8_pmu_attr_groups, |
b1113557 | 821 | .bhrb_nr = 32, |
e05b9b9e ME |
822 | }; |
823 | ||
824 | static int __init init_power8_pmu(void) | |
825 | { | |
5d7ead00 ME |
826 | int rc; |
827 | ||
e05b9b9e ME |
828 | if (!cur_cpu_spec->oprofile_cpu_type || |
829 | strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power8")) | |
830 | return -ENODEV; | |
831 | ||
5d7ead00 ME |
832 | rc = register_power_pmu(&power8_pmu); |
833 | if (rc) | |
834 | return rc; | |
835 | ||
836 | /* Tell userspace that EBB is supported */ | |
837 | cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_EBB; | |
838 | ||
c2e37a26 ME |
839 | if (cpu_has_feature(CPU_FTR_PMAO_BUG)) |
840 | pr_info("PMAO restore workaround active.\n"); | |
841 | ||
5d7ead00 | 842 | return 0; |
e05b9b9e ME |
843 | } |
844 | early_initcall(init_power8_pmu); |