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powerpc/perf: Avoid mutating event in power8_get_constraint()
[deliverable/linux.git] / arch / powerpc / perf / power8-pmu.c
CommitLineData
e05b9b9e
ME		 1/*
2 * Performance counter support for POWER8 processors.
3 *
4 * Copyright 2009 Paul Mackerras, IBM Corporation.
5 * Copyright 2013 Michael Ellerman, IBM Corporation.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
c2e37a26
ME		 13#define pr_fmt(fmt) "power8-pmu: " fmt
14
e05b9b9e
ME		 15#include <linux/kernel.h>
16#include <linux/perf_event.h>
17#include <asm/firmware.h>
18
19
20/*
21 * Some power8 event codes.
22 */
23#define PM_CYC 0x0001e
24#define PM_GCT_NOSLOT_CYC 0x100f8
25#define PM_CMPLU_STALL 0x4000a
26#define PM_INST_CMPL 0x00002
27#define PM_BRU_FIN 0x10068
28#define PM_BR_MPRED_CMPL 0x400f6
29
2fdd313f
ME		 30/* All L1 D cache load references counted at finish, gated by reject */
31#define PM_LD_REF_L1 0x100ee
32/* Load Missed L1 */
33#define PM_LD_MISS_L1 0x3e054
34/* Store Missed L1 */
35#define PM_ST_MISS_L1 0x300f0
36/* L1 cache data prefetches */
37#define PM_L1_PREF 0x0d8b8
38/* Instruction fetches from L1 */
39#define PM_INST_FROM_L1 0x04080
40/* Demand iCache Miss */
41#define PM_L1_ICACHE_MISS 0x200fd
42/* Instruction Demand sectors wriittent into IL1 */
43#define PM_L1_DEMAND_WRITE 0x0408c
44/* Instruction prefetch written into IL1 */
45#define PM_IC_PREF_WRITE 0x0408e
46/* The data cache was reloaded from local core's L3 due to a demand load */
47#define PM_DATA_FROM_L3 0x4c042
48/* Demand LD - L3 Miss (not L2 hit and not L3 hit) */
49#define PM_DATA_FROM_L3MISS 0x300fe
50/* All successful D-side store dispatches for this thread */
51#define PM_L2_ST 0x17080
52/* All successful D-side store dispatches for this thread that were L2 Miss */
53#define PM_L2_ST_MISS 0x17082
54/* Total HW L3 prefetches(Load+store) */
55#define PM_L3_PREF_ALL 0x4e052
56/* Data PTEG reload */
57#define PM_DTLB_MISS 0x300fc
58/* ITLB Reloaded */
59#define PM_ITLB_MISS 0x400fc
60
e05b9b9e
ME		 61
62/*
63 * Raw event encoding for POWER8:
64 *
65 * 60 56 52 48 44 40 36 32
66 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
4df48999
ME		 67 * | [ thresh_cmp ] [ thresh_ctl ]
68 * | |
69 * *- EBB (Linux) thresh start/stop OR FAB match -*
e05b9b9e
ME		 70 *
71 * 28 24 20 16 12 8 4 0
72 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
73 * [ ] [ sample ] [cache] [ pmc ] [unit ] c m [ pmcxsel ]
74 * | | | | |
75 * | | | | *- mark
76 * | | *- L1/L2/L3 cache_sel |
77 * | | |
78 * | *- sampling mode for marked events *- combine
79 * |
80 * *- thresh_sel
81 *
82 * Below uses IBM bit numbering.
83 *
84 * MMCR1[x:y] = unit (PMCxUNIT)
85 * MMCR1[x] = combine (PMCxCOMB)
86 *
87 * if pmc == 3 and unit == 0 and pmcxsel[0:6] == 0b0101011
88 * # PM_MRK_FAB_RSP_MATCH
89 * MMCR1[20:27] = thresh_ctl (FAB_CRESP_MATCH / FAB_TYPE_MATCH)
90 * else if pmc == 4 and unit == 0xf and pmcxsel[0:6] == 0b0101001
91 * # PM_MRK_FAB_RSP_MATCH_CYC
92 * MMCR1[20:27] = thresh_ctl (FAB_CRESP_MATCH / FAB_TYPE_MATCH)
93 * else
94 * MMCRA[48:55] = thresh_ctl (THRESH START/END)
95 *
96 * if thresh_sel:
97 * MMCRA[45:47] = thresh_sel
98 *
99 * if thresh_cmp:
100 * MMCRA[22:24] = thresh_cmp[0:2]
101 * MMCRA[25:31] = thresh_cmp[3:9]
102 *
103 * if unit == 6 or unit == 7
104 * MMCRC[53:55] = cache_sel[1:3] (L2EVENT_SEL)
105 * else if unit == 8 or unit == 9:
106 * if cache_sel[0] == 0: # L3 bank
107 * MMCRC[47:49] = cache_sel[1:3] (L3EVENT_SEL0)
108 * else if cache_sel[0] == 1:
109 * MMCRC[50:51] = cache_sel[2:3] (L3EVENT_SEL1)
110 * else if cache_sel[1]: # L1 event
111 * MMCR1[16] = cache_sel[2]
112 * MMCR1[17] = cache_sel[3]
113 *
114 * if mark:
115 * MMCRA[63] = 1 (SAMPLE_ENABLE)
116 * MMCRA[57:59] = sample[0:2] (RAND_SAMP_ELIG)
117 * MMCRA[61:62] = sample[3:4] (RAND_SAMP_MODE)
118 *
119 */
120
4df48999 121#define EVENT_EBB_MASK 1ull
fb568d76 122#define EVENT_EBB_SHIFT PERF_EVENT_CONFIG_EBB_SHIFT
e05b9b9e
ME		 123#define EVENT_THR_CMP_SHIFT 40 /* Threshold CMP value */
124#define EVENT_THR_CMP_MASK 0x3ff
125#define EVENT_THR_CTL_SHIFT 32 /* Threshold control value (start/stop) */
126#define EVENT_THR_CTL_MASK 0xffull
127#define EVENT_THR_SEL_SHIFT 29 /* Threshold select value */
128#define EVENT_THR_SEL_MASK 0x7
129#define EVENT_THRESH_SHIFT 29 /* All threshold bits */
130#define EVENT_THRESH_MASK 0x1fffffull
131#define EVENT_SAMPLE_SHIFT 24 /* Sampling mode & eligibility */
132#define EVENT_SAMPLE_MASK 0x1f
133#define EVENT_CACHE_SEL_SHIFT 20 /* L2/L3 cache select */
134#define EVENT_CACHE_SEL_MASK 0xf
135#define EVENT_IS_L1 (4 << EVENT_CACHE_SEL_SHIFT)
136#define EVENT_PMC_SHIFT 16 /* PMC number (1-based) */
137#define EVENT_PMC_MASK 0xf
138#define EVENT_UNIT_SHIFT 12 /* Unit */
139#define EVENT_UNIT_MASK 0xf
140#define EVENT_COMBINE_SHIFT 11 /* Combine bit */
141#define EVENT_COMBINE_MASK 0x1
142#define EVENT_MARKED_SHIFT 8 /* Marked bit */
143#define EVENT_MARKED_MASK 0x1
144#define EVENT_IS_MARKED (EVENT_MARKED_MASK << EVENT_MARKED_SHIFT)
145#define EVENT_PSEL_MASK 0xff /* PMCxSEL value */
146
d8bec4c9
ME		 147#define EVENT_VALID_MASK \
148 ((EVENT_THRESH_MASK << EVENT_THRESH_SHIFT) | \
149 (EVENT_SAMPLE_MASK << EVENT_SAMPLE_SHIFT) | \
150 (EVENT_CACHE_SEL_MASK << EVENT_CACHE_SEL_SHIFT) | \
151 (EVENT_PMC_MASK << EVENT_PMC_SHIFT) | \
152 (EVENT_UNIT_MASK << EVENT_UNIT_SHIFT) | \
153 (EVENT_COMBINE_MASK << EVENT_COMBINE_SHIFT) | \
154 (EVENT_MARKED_MASK << EVENT_MARKED_SHIFT) | \
fb568d76 155 (EVENT_EBB_MASK << EVENT_EBB_SHIFT) | \
d8bec4c9
ME		 156 EVENT_PSEL_MASK)
157
b1113557
AK		 158/* MMCRA IFM bits - POWER8 */
159#define POWER8_MMCRA_IFM1 0x0000000040000000UL
160#define POWER8_MMCRA_IFM2 0x0000000080000000UL
161#define POWER8_MMCRA_IFM3 0x00000000C0000000UL
162
163#define ONLY_PLM \
164 (PERF_SAMPLE_BRANCH_USER |\
165 PERF_SAMPLE_BRANCH_KERNEL |\
166 PERF_SAMPLE_BRANCH_HV)
167
e05b9b9e
ME		 168/*
169 * Layout of constraint bits:
170 *
171 * 60 56 52 48 44 40 36 32
172 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
173 * [ fab_match ] [ thresh_cmp ] [ thresh_ctl ] [ ]
174 * |
175 * thresh_sel -*
176 *
177 * 28 24 20 16 12 8 4 0
178 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
4df48999
ME		 179 * | [ ] [ sample ] [ ] [6] [5] [4] [3] [2] [1]
180 * EBB -* | |
181 * | | Count of events for each PMC.
182 * L1 I/D qualifier -* | p1, p2, p3, p4, p5, p6.
e05b9b9e
ME		 183 * nc - number of counters -*
184 *
185 * The PMC fields P1..P6, and NC, are adder fields. As we accumulate constraints
186 * we want the low bit of each field to be added to any existing value.
187 *
188 * Everything else is a value field.
189 */
190
191#define CNST_FAB_MATCH_VAL(v) (((v) & EVENT_THR_CTL_MASK) << 56)
192#define CNST_FAB_MATCH_MASK CNST_FAB_MATCH_VAL(EVENT_THR_CTL_MASK)
193
194/* We just throw all the threshold bits into the constraint */
195#define CNST_THRESH_VAL(v) (((v) & EVENT_THRESH_MASK) << 32)
196#define CNST_THRESH_MASK CNST_THRESH_VAL(EVENT_THRESH_MASK)
197
4df48999
ME		 198#define CNST_EBB_VAL(v) (((v) & EVENT_EBB_MASK) << 24)
199#define CNST_EBB_MASK CNST_EBB_VAL(EVENT_EBB_MASK)
200
e05b9b9e
ME		 201#define CNST_L1_QUAL_VAL(v) (((v) & 3) << 22)
202#define CNST_L1_QUAL_MASK CNST_L1_QUAL_VAL(3)
203
204#define CNST_SAMPLE_VAL(v) (((v) & EVENT_SAMPLE_MASK) << 16)
205#define CNST_SAMPLE_MASK CNST_SAMPLE_VAL(EVENT_SAMPLE_MASK)
206
207/*
208 * For NC we are counting up to 4 events. This requires three bits, and we need
209 * the fifth event to overflow and set the 4th bit. To achieve that we bias the
210 * fields by 3 in test_adder.
211 */
212#define CNST_NC_SHIFT 12
213#define CNST_NC_VAL (1 << CNST_NC_SHIFT)
214#define CNST_NC_MASK (8 << CNST_NC_SHIFT)
215#define POWER8_TEST_ADDER (3 << CNST_NC_SHIFT)
216
217/*
218 * For the per-PMC fields we have two bits. The low bit is added, so if two
219 * events ask for the same PMC the sum will overflow, setting the high bit,
220 * indicating an error. So our mask sets the high bit.
221 */
222#define CNST_PMC_SHIFT(pmc) ((pmc - 1) * 2)
223#define CNST_PMC_VAL(pmc) (1 << CNST_PMC_SHIFT(pmc))
224#define CNST_PMC_MASK(pmc) (2 << CNST_PMC_SHIFT(pmc))
225
226/* Our add_fields is defined as: */
227#define POWER8_ADD_FIELDS \
228 CNST_PMC_VAL(1) | CNST_PMC_VAL(2) | CNST_PMC_VAL(3) | \
229 CNST_PMC_VAL(4) | CNST_PMC_VAL(5) | CNST_PMC_VAL(6) | CNST_NC_VAL
230
231
232/* Bits in MMCR1 for POWER8 */
233#define MMCR1_UNIT_SHIFT(pmc) (60 - (4 * ((pmc) - 1)))
234#define MMCR1_COMBINE_SHIFT(pmc) (35 - ((pmc) - 1))
235#define MMCR1_PMCSEL_SHIFT(pmc) (24 - (((pmc) - 1)) * 8)
a53b27b3 236#define MMCR1_FAB_SHIFT 36
e05b9b9e
ME		 237#define MMCR1_DC_QUAL_SHIFT 47
238#define MMCR1_IC_QUAL_SHIFT 46
239
240/* Bits in MMCRA for POWER8 */
241#define MMCRA_SAMP_MODE_SHIFT 1
242#define MMCRA_SAMP_ELIG_SHIFT 4
243#define MMCRA_THR_CTL_SHIFT 8
244#define MMCRA_THR_SEL_SHIFT 16
245#define MMCRA_THR_CMP_SHIFT 32
246#define MMCRA_SDAR_MODE_TLB (1ull << 42)
247
248
249static inline bool event_is_fab_match(u64 event)
250{
251 /* Only check pmc, unit and pmcxsel, ignore the edge bit (0) */
252 event &= 0xff0fe;
253
254 /* PM_MRK_FAB_RSP_MATCH & PM_MRK_FAB_RSP_MATCH_CYC */
255 return (event == 0x30056 || event == 0x4f052);
256}
257
258static int power8_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp)
259{
4df48999 260 unsigned int unit, pmc, cache, ebb;
e05b9b9e
ME		 261 unsigned long mask, value;
262
263 mask = value = 0;
264
d8bec4c9
ME		 265 if (event & ~EVENT_VALID_MASK)
266 return -1;
267
4df48999
ME		 268 pmc = (event >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK;
269 unit = (event >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK;
270 cache = (event >> EVENT_CACHE_SEL_SHIFT) & EVENT_CACHE_SEL_MASK;
fb568d76 271 ebb = (event >> EVENT_EBB_SHIFT) & EVENT_EBB_MASK;
4df48999 272
e05b9b9e 273 if (pmc) {
7cbba630
ME		 274 u64 base_event;
275
e05b9b9e
ME		 276 if (pmc > 6)
277 return -1;
278
7cbba630
ME		 279 /* Ignore Linux defined bits when checking event below */
280 base_event = event & ~(EVENT_EBB_MASK << EVENT_EBB_SHIFT);
e05b9b9e 281
7cbba630 282 if (pmc >= 5 && base_event != 0x500fa && base_event != 0x600f4)
e05b9b9e 283 return -1;
7cbba630
ME		 284
285 mask |= CNST_PMC_MASK(pmc);
286 value |= CNST_PMC_VAL(pmc);
e05b9b9e
ME		 287 }
288
289 if (pmc <= 4) {
290 /*
291 * Add to number of counters in use. Note this includes events with
292 * a PMC of 0 - they still need a PMC, it's just assigned later.
293 * Don't count events on PMC 5 & 6, there is only one valid event
294 * on each of those counters, and they are handled above.
295 */
296 mask |= CNST_NC_MASK;
297 value |= CNST_NC_VAL;
298 }
299
300 if (unit >= 6 && unit <= 9) {
301 /*
302 * L2/L3 events contain a cache selector field, which is
303 * supposed to be programmed into MMCRC. However MMCRC is only
304 * HV writable, and there is no API for guest kernels to modify
305 * it. The solution is for the hypervisor to initialise the
306 * field to zeroes, and for us to only ever allow events that
307 * have a cache selector of zero.
308 */
309 if (cache)
310 return -1;
311
312 } else if (event & EVENT_IS_L1) {
313 mask |= CNST_L1_QUAL_MASK;
314 value |= CNST_L1_QUAL_VAL(cache);
315 }
316
317 if (event & EVENT_IS_MARKED) {
318 mask |= CNST_SAMPLE_MASK;
319 value |= CNST_SAMPLE_VAL(event >> EVENT_SAMPLE_SHIFT);
320 }
321
322 /*
323 * Special case for PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC,
324 * the threshold control bits are used for the match value.
325 */
326 if (event_is_fab_match(event)) {
327 mask |= CNST_FAB_MATCH_MASK;
328 value |= CNST_FAB_MATCH_VAL(event >> EVENT_THR_CTL_SHIFT);
329 } else {
330 /*
331 * Check the mantissa upper two bits are not zero, unless the
332 * exponent is also zero. See the THRESH_CMP_MANTISSA doc.
333 */
334 unsigned int cmp, exp;
335
336 cmp = (event >> EVENT_THR_CMP_SHIFT) & EVENT_THR_CMP_MASK;
337 exp = cmp >> 7;
338
339 if (exp && (cmp & 0x60) == 0)
340 return -1;
341
342 mask |= CNST_THRESH_MASK;
343 value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT);
344 }
345
4df48999
ME		 346 if (!pmc && ebb)
347 /* EBB events must specify the PMC */
348 return -1;
349
350 /*
351 * All events must agree on EBB, either all request it or none.
352 * EBB events are pinned & exclusive, so this should never actually
353 * hit, but we leave it as a fallback in case.
354 */
355 mask |= CNST_EBB_VAL(ebb);
356 value |= CNST_EBB_MASK;
357
e05b9b9e
ME		 358 *maskp = mask;
359 *valp = value;
360
361 return 0;
362}
363
364static int power8_compute_mmcr(u64 event[], int n_ev,
365 unsigned int hwc[], unsigned long mmcr[])
366{
367 unsigned long mmcra, mmcr1, unit, combine, psel, cache, val;
368 unsigned int pmc, pmc_inuse;
369 int i;
370
371 pmc_inuse = 0;
372
373 /* First pass to count resource use */
374 for (i = 0; i < n_ev; ++i) {
375 pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK;
376 if (pmc)
377 pmc_inuse |= 1 << pmc;
378 }
379
380 /* In continous sampling mode, update SDAR on TLB miss */
381 mmcra = MMCRA_SDAR_MODE_TLB;
382 mmcr1 = 0;
383
384 /* Second pass: assign PMCs, set all MMCR1 fields */
385 for (i = 0; i < n_ev; ++i) {
386 pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK;
387 unit = (event[i] >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK;
388 combine = (event[i] >> EVENT_COMBINE_SHIFT) & EVENT_COMBINE_MASK;
389 psel = event[i] & EVENT_PSEL_MASK;
390
391 if (!pmc) {
392 for (pmc = 1; pmc <= 4; ++pmc) {
393 if (!(pmc_inuse & (1 << pmc)))
394 break;
395 }
396
397 pmc_inuse |= 1 << pmc;
398 }
399
400 if (pmc <= 4) {
401 mmcr1 |= unit << MMCR1_UNIT_SHIFT(pmc);
402 mmcr1 |= combine << MMCR1_COMBINE_SHIFT(pmc);
403 mmcr1 |= psel << MMCR1_PMCSEL_SHIFT(pmc);
404 }
405
406 if (event[i] & EVENT_IS_L1) {
407 cache = event[i] >> EVENT_CACHE_SEL_SHIFT;
408 mmcr1 |= (cache & 1) << MMCR1_IC_QUAL_SHIFT;
409 cache >>= 1;
410 mmcr1 |= (cache & 1) << MMCR1_DC_QUAL_SHIFT;
411 }
412
413 if (event[i] & EVENT_IS_MARKED) {
414 mmcra |= MMCRA_SAMPLE_ENABLE;
415
416 val = (event[i] >> EVENT_SAMPLE_SHIFT) & EVENT_SAMPLE_MASK;
417 if (val) {
418 mmcra |= (val & 3) << MMCRA_SAMP_MODE_SHIFT;
419 mmcra |= (val >> 2) << MMCRA_SAMP_ELIG_SHIFT;
420 }
421 }
422
423 /*
424 * PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC,
425 * the threshold bits are used for the match value.
426 */
427 if (event_is_fab_match(event[i])) {
a53b27b3
ME		 428 mmcr1 |= ((event[i] >> EVENT_THR_CTL_SHIFT) &
429 EVENT_THR_CTL_MASK) << MMCR1_FAB_SHIFT;
e05b9b9e
ME		 430 } else {
431 val = (event[i] >> EVENT_THR_CTL_SHIFT) & EVENT_THR_CTL_MASK;
432 mmcra |= val << MMCRA_THR_CTL_SHIFT;
433 val = (event[i] >> EVENT_THR_SEL_SHIFT) & EVENT_THR_SEL_MASK;
434 mmcra |= val << MMCRA_THR_SEL_SHIFT;
435 val = (event[i] >> EVENT_THR_CMP_SHIFT) & EVENT_THR_CMP_MASK;
436 mmcra |= val << MMCRA_THR_CMP_SHIFT;
437 }
438
439 hwc[i] = pmc - 1;
440 }
441
442 /* Return MMCRx values */
443 mmcr[0] = 0;
444
445 /* pmc_inuse is 1-based */
446 if (pmc_inuse & 2)
447 mmcr[0] = MMCR0_PMC1CE;
448
449 if (pmc_inuse & 0x7c)
450 mmcr[0] |= MMCR0_PMCjCE;
451
7a7a41f9
ME		 452 /* If we're not using PMC 5 or 6, freeze them */
453 if (!(pmc_inuse & 0x60))
454 mmcr[0] |= MMCR0_FC56;
455
e05b9b9e
ME		 456 mmcr[1] = mmcr1;
457 mmcr[2] = mmcra;
458
459 return 0;
460}
461
462#define MAX_ALT 2
463
464/* Table of alternatives, sorted by column 0 */
465static const unsigned int event_alternatives[][MAX_ALT] = {
466 { 0x10134, 0x301e2 }, /* PM_MRK_ST_CMPL */
467 { 0x10138, 0x40138 }, /* PM_BR_MRK_2PATH */
468 { 0x18082, 0x3e05e }, /* PM_L3_CO_MEPF */
469 { 0x1d14e, 0x401e8 }, /* PM_MRK_DATA_FROM_L2MISS */
470 { 0x1e054, 0x4000a }, /* PM_CMPLU_STALL */
471 { 0x20036, 0x40036 }, /* PM_BR_2PATH */
472 { 0x200f2, 0x300f2 }, /* PM_INST_DISP */
473 { 0x200f4, 0x600f4 }, /* PM_RUN_CYC */
474 { 0x2013c, 0x3012e }, /* PM_MRK_FILT_MATCH */
475 { 0x3e054, 0x400f0 }, /* PM_LD_MISS_L1 */
476 { 0x400fa, 0x500fa }, /* PM_RUN_INST_CMPL */
477};
478
479/*
480 * Scan the alternatives table for a match and return the
481 * index into the alternatives table if found, else -1.
482 */
483static int find_alternative(u64 event)
484{
485 int i, j;
486
487 for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) {
488 if (event < event_alternatives[i][0])
489 break;
490
491 for (j = 0; j < MAX_ALT && event_alternatives[i][j]; ++j)
492 if (event == event_alternatives[i][j])
493 return i;
494 }
495
496 return -1;
497}
498
499static int power8_get_alternatives(u64 event, unsigned int flags, u64 alt[])
500{
501 int i, j, num_alt = 0;
502 u64 alt_event;
503
504 alt[num_alt++] = event;
505
506 i = find_alternative(event);
507 if (i >= 0) {
508 /* Filter out the original event, it's already in alt[0] */
509 for (j = 0; j < MAX_ALT; ++j) {
510 alt_event = event_alternatives[i][j];
511 if (alt_event && alt_event != event)
512 alt[num_alt++] = alt_event;
513 }
514 }
515
516 if (flags & PPMU_ONLY_COUNT_RUN) {
517 /*
518 * We're only counting in RUN state, so PM_CYC is equivalent to
519 * PM_RUN_CYC and PM_INST_CMPL === PM_RUN_INST_CMPL.
520 */
521 j = num_alt;
522 for (i = 0; i < num_alt; ++i) {
523 switch (alt[i]) {
524 case 0x1e: /* PM_CYC */
525 alt[j++] = 0x600f4; /* PM_RUN_CYC */
526 break;
527 case 0x600f4: /* PM_RUN_CYC */
528 alt[j++] = 0x1e;
529 break;
530 case 0x2: /* PM_PPC_CMPL */
531 alt[j++] = 0x500fa; /* PM_RUN_INST_CMPL */
532 break;
533 case 0x500fa: /* PM_RUN_INST_CMPL */
534 alt[j++] = 0x2; /* PM_PPC_CMPL */
535 break;
536 }
537 }
538 num_alt = j;
539 }
540
541 return num_alt;
542}
543
544static void power8_disable_pmc(unsigned int pmc, unsigned long mmcr[])
545{
546 if (pmc <= 3)
547 mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SHIFT(pmc + 1));
548}
549
550PMU_FORMAT_ATTR(event, "config:0-49");
551PMU_FORMAT_ATTR(pmcxsel, "config:0-7");
552PMU_FORMAT_ATTR(mark, "config:8");
553PMU_FORMAT_ATTR(combine, "config:11");
554PMU_FORMAT_ATTR(unit, "config:12-15");
555PMU_FORMAT_ATTR(pmc, "config:16-19");
556PMU_FORMAT_ATTR(cache_sel, "config:20-23");
557PMU_FORMAT_ATTR(sample_mode, "config:24-28");
558PMU_FORMAT_ATTR(thresh_sel, "config:29-31");
559PMU_FORMAT_ATTR(thresh_stop, "config:32-35");
560PMU_FORMAT_ATTR(thresh_start, "config:36-39");
561PMU_FORMAT_ATTR(thresh_cmp, "config:40-49");
562
563static struct attribute *power8_pmu_format_attr[] = {
564 &format_attr_event.attr,
565 &format_attr_pmcxsel.attr,
566 &format_attr_mark.attr,
567 &format_attr_combine.attr,
568 &format_attr_unit.attr,
569 &format_attr_pmc.attr,
570 &format_attr_cache_sel.attr,
571 &format_attr_sample_mode.attr,
572 &format_attr_thresh_sel.attr,
573 &format_attr_thresh_stop.attr,
574 &format_attr_thresh_start.attr,
575 &format_attr_thresh_cmp.attr,
576 NULL,
577};
578
579struct attribute_group power8_pmu_format_group = {
580 .name = "format",
581 .attrs = power8_pmu_format_attr,
582};
583
584static const struct attribute_group *power8_pmu_attr_groups[] = {
585 &power8_pmu_format_group,
586 NULL,
587};
588
589static int power8_generic_events[] = {
590 [PERF_COUNT_HW_CPU_CYCLES] = PM_CYC,
591 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PM_GCT_NOSLOT_CYC,
592 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = PM_CMPLU_STALL,
593 [PERF_COUNT_HW_INSTRUCTIONS] = PM_INST_CMPL,
594 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PM_BRU_FIN,
595 [PERF_COUNT_HW_BRANCH_MISSES] = PM_BR_MPRED_CMPL,
2fdd313f
ME		 596 [PERF_COUNT_HW_CACHE_REFERENCES] = PM_LD_REF_L1,
597 [PERF_COUNT_HW_CACHE_MISSES] = PM_LD_MISS_L1,
e05b9b9e
ME		 598};
599
b1113557
AK		 600static u64 power8_bhrb_filter_map(u64 branch_sample_type)
601{
602 u64 pmu_bhrb_filter = 0;
b1113557 603
7689bdca 604 /* BHRB and regular PMU events share the same privilege state
b1113557 605 * filter configuration. BHRB is always recorded along with a
7689bdca
AK		 606 * regular PMU event. As the privilege state filter is handled
607 * in the basic PMC configuration of the accompanying regular
608 * PMU event, we ignore any separate BHRB specific request.
b1113557 609 */
b1113557
AK		 610
611 /* No branch filter requested */
612 if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY)
613 return pmu_bhrb_filter;
614
615 /* Invalid branch filter options - HW does not support */
616 if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_RETURN)
617 return -1;
618
619 if (branch_sample_type & PERF_SAMPLE_BRANCH_IND_CALL)
620 return -1;
621
622 if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_CALL) {
623 pmu_bhrb_filter |= POWER8_MMCRA_IFM1;
624 return pmu_bhrb_filter;
625 }
626
627 /* Every thing else is unsupported */
628 return -1;
629}
630
631static void power8_config_bhrb(u64 pmu_bhrb_filter)
632{
633 /* Enable BHRB filter in PMU */
634 mtspr(SPRN_MMCRA, (mfspr(SPRN_MMCRA) | pmu_bhrb_filter));
635}
636
2fdd313f
ME		 637#define C(x) PERF_COUNT_HW_CACHE_##x
638
639/*
640 * Table of generalized cache-related events.
641 * 0 means not supported, -1 means nonsensical, other values
642 * are event codes.
643 */
644static int power8_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
645 [ C(L1D) ] = {
646 [ C(OP_READ) ] = {
647 [ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
648 [ C(RESULT_MISS) ] = PM_LD_MISS_L1,
649 },
650 [ C(OP_WRITE) ] = {
651 [ C(RESULT_ACCESS) ] = 0,
652 [ C(RESULT_MISS) ] = PM_ST_MISS_L1,
653 },
654 [ C(OP_PREFETCH) ] = {
655 [ C(RESULT_ACCESS) ] = PM_L1_PREF,
656 [ C(RESULT_MISS) ] = 0,
657 },
658 },
659 [ C(L1I) ] = {
660 [ C(OP_READ) ] = {
661 [ C(RESULT_ACCESS) ] = PM_INST_FROM_L1,
662 [ C(RESULT_MISS) ] = PM_L1_ICACHE_MISS,
663 },
664 [ C(OP_WRITE) ] = {
665 [ C(RESULT_ACCESS) ] = PM_L1_DEMAND_WRITE,
666 [ C(RESULT_MISS) ] = -1,
667 },
668 [ C(OP_PREFETCH) ] = {
669 [ C(RESULT_ACCESS) ] = PM_IC_PREF_WRITE,
670 [ C(RESULT_MISS) ] = 0,
671 },
672 },
673 [ C(LL) ] = {
674 [ C(OP_READ) ] = {
675 [ C(RESULT_ACCESS) ] = PM_DATA_FROM_L3,
676 [ C(RESULT_MISS) ] = PM_DATA_FROM_L3MISS,
677 },
678 [ C(OP_WRITE) ] = {
679 [ C(RESULT_ACCESS) ] = PM_L2_ST,
680 [ C(RESULT_MISS) ] = PM_L2_ST_MISS,
681 },
682 [ C(OP_PREFETCH) ] = {
683 [ C(RESULT_ACCESS) ] = PM_L3_PREF_ALL,
684 [ C(RESULT_MISS) ] = 0,
685 },
686 },
687 [ C(DTLB) ] = {
688 [ C(OP_READ) ] = {
689 [ C(RESULT_ACCESS) ] = 0,
690 [ C(RESULT_MISS) ] = PM_DTLB_MISS,
691 },
692 [ C(OP_WRITE) ] = {
693 [ C(RESULT_ACCESS) ] = -1,
694 [ C(RESULT_MISS) ] = -1,
695 },
696 [ C(OP_PREFETCH) ] = {
697 [ C(RESULT_ACCESS) ] = -1,
698 [ C(RESULT_MISS) ] = -1,
699 },
700 },
701 [ C(ITLB) ] = {
702 [ C(OP_READ) ] = {
703 [ C(RESULT_ACCESS) ] = 0,
704 [ C(RESULT_MISS) ] = PM_ITLB_MISS,
705 },
706 [ C(OP_WRITE) ] = {
707 [ C(RESULT_ACCESS) ] = -1,
708 [ C(RESULT_MISS) ] = -1,
709 },
710 [ C(OP_PREFETCH) ] = {
711 [ C(RESULT_ACCESS) ] = -1,
712 [ C(RESULT_MISS) ] = -1,
713 },
714 },
715 [ C(BPU) ] = {
716 [ C(OP_READ) ] = {
717 [ C(RESULT_ACCESS) ] = PM_BRU_FIN,
718 [ C(RESULT_MISS) ] = PM_BR_MPRED_CMPL,
719 },
720 [ C(OP_WRITE) ] = {
721 [ C(RESULT_ACCESS) ] = -1,
722 [ C(RESULT_MISS) ] = -1,
723 },
724 [ C(OP_PREFETCH) ] = {
725 [ C(RESULT_ACCESS) ] = -1,
726 [ C(RESULT_MISS) ] = -1,
727 },
728 },
729 [ C(NODE) ] = {
730 [ C(OP_READ) ] = {
731 [ C(RESULT_ACCESS) ] = -1,
732 [ C(RESULT_MISS) ] = -1,
733 },
734 [ C(OP_WRITE) ] = {
735 [ C(RESULT_ACCESS) ] = -1,
736 [ C(RESULT_MISS) ] = -1,
737 },
738 [ C(OP_PREFETCH) ] = {
739 [ C(RESULT_ACCESS) ] = -1,
740 [ C(RESULT_MISS) ] = -1,
741 },
742 },
743};
744
745#undef C
746
e05b9b9e
ME		 747static struct power_pmu power8_pmu = {
748 .name = "POWER8",
749 .n_counter = 6,
750 .max_alternatives = MAX_ALT + 1,
751 .add_fields = POWER8_ADD_FIELDS,
752 .test_adder = POWER8_TEST_ADDER,
753 .compute_mmcr = power8_compute_mmcr,
b1113557
AK		 754 .config_bhrb = power8_config_bhrb,
755 .bhrb_filter_map = power8_bhrb_filter_map,
e05b9b9e
ME		 756 .get_constraint = power8_get_constraint,
757 .get_alternatives = power8_get_alternatives,
758 .disable_pmc = power8_disable_pmc,
4df48999 759 .flags = PPMU_HAS_SSLOT | PPMU_HAS_SIER | PPMU_BHRB | PPMU_EBB,
e05b9b9e
ME		 760 .n_generic = ARRAY_SIZE(power8_generic_events),
761 .generic_events = power8_generic_events,
2fdd313f 762 .cache_events = &power8_cache_events,
e05b9b9e 763 .attr_groups = power8_pmu_attr_groups,
b1113557 764 .bhrb_nr = 32,
e05b9b9e
ME		 765};
766
767static int __init init_power8_pmu(void)
768{
5d7ead00
ME		 769 int rc;
770
e05b9b9e
ME		 771 if (!cur_cpu_spec->oprofile_cpu_type ||
772 strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power8"))
773 return -ENODEV;
774
5d7ead00
ME		 775 rc = register_power_pmu(&power8_pmu);
776 if (rc)
777 return rc;
778
779 /* Tell userspace that EBB is supported */
780 cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_EBB;
781
c2e37a26
ME		 782 if (cpu_has_feature(CPU_FTR_PMAO_BUG))
783 pr_info("PMAO restore workaround active.\n");
784
5d7ead00 785 return 0;
e05b9b9e
ME		 786}
787early_initcall(init_power8_pmu);
Linux kernel - Deliverables
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