[deliverable/linux.git] / arch / powerpc / platforms / 85xx / mpc85xx_mds.c

/*
 * Copyright (C) 2006-2010, 2012 Freescale Semicondutor, Inc.
 * All rights reserved.
 *
 * Author: Andy Fleming <afleming@freescale.com>
 *
 * Based on 83xx/mpc8360e_pb.c by:
 *	   Li Yang <LeoLi@freescale.com>
 *	   Yin Olivia <Hong-hua.Yin@freescale.com>
 *
 * Description:
 * MPC85xx MDS board specific routines.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/reboot.h>
#include <linux/pci.h>
#include <linux/kdev_t.h>
#include <linux/major.h>
#include <linux/console.h>
#include <linux/delay.h>
#include <linux/seq_file.h>
#include <linux/initrd.h>
#include <linux/fsl_devices.h>
#include <linux/of_platform.h>
#include <linux/of_device.h>
#include <linux/phy.h>
#include <linux/memblock.h>

#include <linux/atomic.h>
#include <asm/time.h>
#include <asm/io.h>
#include <asm/machdep.h>
#include <asm/pci-bridge.h>
#include <asm/irq.h>
#include <mm/mmu_decl.h>
#include <asm/prom.h>
#include <asm/udbg.h>
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
#include <sysdev/simple_gpio.h>
#include <asm/qe.h>
#include <asm/qe_ic.h>
#include <asm/mpic.h>
#include <asm/swiotlb.h>
#include <asm/fsl_guts.h>
#include "smp.h"

#include "mpc85xx.h"

#undef DEBUG
#ifdef DEBUG
#define DBG(fmt...) udbg_printf(fmt)
#else
#define DBG(fmt...)
#endif

#define MV88E1111_SCR	0x10
#define MV88E1111_SCR_125CLK	0x0010
static int mpc8568_fixup_125_clock(struct phy_device *phydev)
{
	int scr;
	int err;

	/* Workaround for the 125 CLK Toggle */
	scr = phy_read(phydev, MV88E1111_SCR);

	if (scr < 0)
		return scr;

	err = phy_write(phydev, MV88E1111_SCR, scr & ~(MV88E1111_SCR_125CLK));

	if (err)
		return err;

	err = phy_write(phydev, MII_BMCR, BMCR_RESET);

	if (err)
		return err;

	scr = phy_read(phydev, MV88E1111_SCR);

	if (scr < 0)
		return scr;

	err = phy_write(phydev, MV88E1111_SCR, scr | 0x0008);

	return err;
}

static int mpc8568_mds_phy_fixups(struct phy_device *phydev)
{
	int temp;
	int err;

	/* Errata */
	err = phy_write(phydev,29, 0x0006);

	if (err)
		return err;

	temp = phy_read(phydev, 30);

	if (temp < 0)
		return temp;

	temp = (temp & (~0x8000)) | 0x4000;
	err = phy_write(phydev,30, temp);

	if (err)
		return err;

	err = phy_write(phydev,29, 0x000a);

	if (err)
		return err;

	temp = phy_read(phydev, 30);

	if (temp < 0)
		return temp;

	temp = phy_read(phydev, 30);

	if (temp < 0)
		return temp;

	temp &= ~0x0020;

	err = phy_write(phydev,30,temp);

	if (err)
		return err;

	/* Disable automatic MDI/MDIX selection */
	temp = phy_read(phydev, 16);

	if (temp < 0)
		return temp;

	temp &= ~0x0060;
	err = phy_write(phydev,16,temp);

	return err;
}

/* ************************************************************************
 *
 * Setup the architecture
 *
 */
#ifdef CONFIG_QUICC_ENGINE
static void __init mpc85xx_mds_reset_ucc_phys(void)
{
	struct device_node *np;
	static u8 __iomem *bcsr_regs;

	/* Map BCSR area */
	np = of_find_node_by_name(NULL, "bcsr");
	if (!np)
		return;

	bcsr_regs = of_iomap(np, 0);
	of_node_put(np);
	if (!bcsr_regs)
		return;

	if (machine_is(mpc8568_mds)) {
#define BCSR_UCC1_GETH_EN	(0x1 << 7)
#define BCSR_UCC2_GETH_EN	(0x1 << 7)
#define BCSR_UCC1_MODE_MSK	(0x3 << 4)
#define BCSR_UCC2_MODE_MSK	(0x3 << 0)

		/* Turn off UCC1 & UCC2 */
		clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
		clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);

		/* Mode is RGMII, all bits clear */
		clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK |
					 BCSR_UCC2_MODE_MSK);

		/* Turn UCC1 & UCC2 on */
		setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
		setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
	} else if (machine_is(mpc8569_mds)) {
#define BCSR7_UCC12_GETHnRST	(0x1 << 2)
#define BCSR8_UEM_MARVELL_RST	(0x1 << 1)
#define BCSR_UCC_RGMII		(0x1 << 6)
#define BCSR_UCC_RTBI		(0x1 << 5)
		/*
		 * U-Boot mangles interrupt polarity for Marvell PHYs,
		 * so reset built-in and UEM Marvell PHYs, this puts
		 * the PHYs into their normal state.
		 */
		clrbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
		setbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);

		setbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
		clrbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);

		for (np = NULL; (np = of_find_compatible_node(np,
						"network",
						"ucc_geth")) != NULL;) {
			const unsigned int *prop;
			int ucc_num;

			prop = of_get_property(np, "cell-index", NULL);
			if (prop == NULL)
				continue;

			ucc_num = *prop - 1;

			prop = of_get_property(np, "phy-connection-type", NULL);
			if (prop == NULL)
				continue;

			if (strcmp("rtbi", (const char *)prop) == 0)
				clrsetbits_8(&bcsr_regs[7 + ucc_num],
					BCSR_UCC_RGMII, BCSR_UCC_RTBI);
		}
	} else if (machine_is(p1021_mds)) {
#define BCSR11_ENET_MICRST     (0x1 << 5)
		/* Reset Micrel PHY */
		clrbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
		setbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
	}

	iounmap(bcsr_regs);
}

static void __init mpc85xx_mds_qe_init(void)
{
	struct device_node *np;

	np = of_find_compatible_node(NULL, NULL, "fsl,qe");
	if (!np) {
		np = of_find_node_by_name(NULL, "qe");
		if (!np)
			return;
	}

	if (!of_device_is_available(np)) {
		of_node_put(np);
		return;
	}

	qe_reset();
	of_node_put(np);

	np = of_find_node_by_name(NULL, "par_io");
	if (np) {
		struct device_node *ucc;

		par_io_init(np);
		of_node_put(np);

		for_each_node_by_name(ucc, "ucc")
			par_io_of_config(ucc);
	}

	mpc85xx_mds_reset_ucc_phys();

	if (machine_is(p1021_mds)) {

		struct ccsr_guts __iomem *guts;

		np = of_find_node_by_name(NULL, "global-utilities");
		if (np) {
			guts = of_iomap(np, 0);
			if (!guts)
				pr_err("mpc85xx-rdb: could not map global utilities register\n");
			else{
			/* P1021 has pins muxed for QE and other functions. To
			 * enable QE UEC mode, we need to set bit QE0 for UCC1
			 * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
			 * and QE12 for QE MII management signals in PMUXCR
			 * register.
			 */
				setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
						  MPC85xx_PMUXCR_QE(3) |
						  MPC85xx_PMUXCR_QE(9) |
						  MPC85xx_PMUXCR_QE(12));
				iounmap(guts);
			}
			of_node_put(np);
		}

	}
}

static void __init mpc85xx_mds_qeic_init(void)
{
	struct device_node *np;

	np = of_find_compatible_node(NULL, NULL, "fsl,qe");
	if (!of_device_is_available(np)) {
		of_node_put(np);
		return;
	}

	np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
	if (!np) {
		np = of_find_node_by_type(NULL, "qeic");
		if (!np)
			return;
	}

	if (machine_is(p1021_mds))
		qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
				qe_ic_cascade_high_mpic);
	else
		qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
	of_node_put(np);
}
#else
static void __init mpc85xx_mds_qe_init(void) { }
static void __init mpc85xx_mds_qeic_init(void) { }
#endif	/* CONFIG_QUICC_ENGINE */

static void __init mpc85xx_mds_setup_arch(void)
{
	if (ppc_md.progress)
		ppc_md.progress("mpc85xx_mds_setup_arch()", 0);

	mpc85xx_smp_init();

	mpc85xx_mds_qe_init();

	fsl_pci_assign_primary();

	swiotlb_detect_4g();
}


static int __init board_fixups(void)
{
	char phy_id[20];
	char *compstrs[2] = {"fsl,gianfar-mdio", "fsl,ucc-mdio"};
	struct device_node *mdio;
	struct resource res;
	int i;

	for (i = 0; i < ARRAY_SIZE(compstrs); i++) {
		mdio = of_find_compatible_node(NULL, NULL, compstrs[i]);

		of_address_to_resource(mdio, 0, &res);
		snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
			(unsigned long long)res.start, 1);

		phy_register_fixup_for_id(phy_id, mpc8568_fixup_125_clock);
		phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);

		/* Register a workaround for errata */
		snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
			(unsigned long long)res.start, 7);
		phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);

		of_node_put(mdio);
	}

	return 0;
}
machine_arch_initcall(mpc8568_mds, board_fixups);
machine_arch_initcall(mpc8569_mds, board_fixups);

static int __init mpc85xx_publish_devices(void)
{
	if (machine_is(mpc8568_mds))
		simple_gpiochip_init("fsl,mpc8568mds-bcsr-gpio");
	if (machine_is(mpc8569_mds))
		simple_gpiochip_init("fsl,mpc8569mds-bcsr-gpio");

	return mpc85xx_common_publish_devices();
}

machine_arch_initcall(mpc8568_mds, mpc85xx_publish_devices);
machine_arch_initcall(mpc8569_mds, mpc85xx_publish_devices);
machine_arch_initcall(p1021_mds, mpc85xx_common_publish_devices);

machine_arch_initcall(mpc8568_mds, swiotlb_setup_bus_notifier);
machine_arch_initcall(mpc8569_mds, swiotlb_setup_bus_notifier);
machine_arch_initcall(p1021_mds, swiotlb_setup_bus_notifier);

static void __init mpc85xx_mds_pic_init(void)
{
	struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
			MPIC_SINGLE_DEST_CPU,
			0, 256, " OpenPIC  ");
	BUG_ON(mpic == NULL);

	mpic_init(mpic);
	mpc85xx_mds_qeic_init();
}

static int __init mpc85xx_mds_probe(void)
{
        unsigned long root = of_get_flat_dt_root();

        return of_flat_dt_is_compatible(root, "MPC85xxMDS");
}

define_machine(mpc8568_mds) {
	.name		= "MPC8568 MDS",
	.probe		= mpc85xx_mds_probe,
	.setup_arch	= mpc85xx_mds_setup_arch,
	.init_IRQ	= mpc85xx_mds_pic_init,
	.get_irq	= mpic_get_irq,
	.restart	= fsl_rstcr_restart,
	.calibrate_decr	= generic_calibrate_decr,
	.progress	= udbg_progress,
#ifdef CONFIG_PCI
	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
#endif
};

static int __init mpc8569_mds_probe(void)
{
	unsigned long root = of_get_flat_dt_root();

	return of_flat_dt_is_compatible(root, "fsl,MPC8569EMDS");
}

define_machine(mpc8569_mds) {
	.name		= "MPC8569 MDS",
	.probe		= mpc8569_mds_probe,
	.setup_arch	= mpc85xx_mds_setup_arch,
	.init_IRQ	= mpc85xx_mds_pic_init,
	.get_irq	= mpic_get_irq,
	.restart	= fsl_rstcr_restart,
	.calibrate_decr	= generic_calibrate_decr,
	.progress	= udbg_progress,
#ifdef CONFIG_PCI
	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
#endif
};

static int __init p1021_mds_probe(void)
{
	unsigned long root = of_get_flat_dt_root();

	return of_flat_dt_is_compatible(root, "fsl,P1021MDS");

}

define_machine(p1021_mds) {
	.name		= "P1021 MDS",
	.probe		= p1021_mds_probe,
	.setup_arch	= mpc85xx_mds_setup_arch,
	.init_IRQ	= mpc85xx_mds_pic_init,
	.get_irq	= mpic_get_irq,
	.restart	= fsl_rstcr_restart,
	.calibrate_decr	= generic_calibrate_decr,
	.progress	= udbg_progress,
#ifdef CONFIG_PCI
	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
#endif
};
Commit	Line	Data
c2882bb1	1	/*
c141b38f ZF	2	* Copyright (C) 2006-2010, 2012 Freescale Semicondutor, Inc.
c141b38f ZF	3	* All rights reserved.
c2882bb1 AF	4	*
	5	* Author: Andy Fleming <afleming@freescale.com>
	6	*
	7	* Based on 83xx/mpc8360e_pb.c by:
	8	* Li Yang <LeoLi@freescale.com>
	9	* Yin Olivia <Hong-hua.Yin@freescale.com>
	10	*
	11	* Description:
23f510bc	12	* MPC85xx MDS board specific routines.
c2882bb1 AF	13	*
	14	* This program is free software; you can redistribute it and/or modify it
	15	* under the terms of the GNU General Public License as published by the
	16	* Free Software Foundation; either version 2 of the License, or (at your
	17	* option) any later version.
	18	*/
	19
	20	#include <linux/stddef.h>
	21	#include <linux/kernel.h>
	22	#include <linux/init.h>
	23	#include <linux/errno.h>
	24	#include <linux/reboot.h>
	25	#include <linux/pci.h>
	26	#include <linux/kdev_t.h>
	27	#include <linux/major.h>
	28	#include <linux/console.h>
	29	#include <linux/delay.h>
	30	#include <linux/seq_file.h>
c2882bb1	31	#include <linux/initrd.h>
c2882bb1	32	#include <linux/fsl_devices.h>
882407b9 JL	33	#include <linux/of_platform.h>
882407b9 JL	34	#include <linux/of_device.h>
94833a42	35	#include <linux/phy.h>
95f72d1e	36	#include <linux/memblock.h>
c2882bb1	37
60063497	38	#include <linux/atomic.h>
c2882bb1 AF	39	#include <asm/time.h>
	40	#include <asm/io.h>
	41	#include <asm/machdep.h>
c2882bb1	42	#include <asm/pci-bridge.h>
c2882bb1 AF	43	#include <asm/irq.h>
	44	#include <mm/mmu_decl.h>
	45	#include <asm/prom.h>
	46	#include <asm/udbg.h>
	47	#include <sysdev/fsl_soc.h>
3f6c5dae	48	#include <sysdev/fsl_pci.h>
9b9d401b	49	#include <sysdev/simple_gpio.h>
c2882bb1 AF	50	#include <asm/qe.h>
	51	#include <asm/qe_ic.h>
	52	#include <asm/mpic.h>
152d0182	53	#include <asm/swiotlb.h>
c141b38f	54	#include <asm/fsl_guts.h>
582d3e09	55	#include "smp.h"
c2882bb1	56
543a07b1 DES	57	#include "mpc85xx.h"
543a07b1 DES	58
c2882bb1 AF	59	#undef DEBUG
	60	#ifdef DEBUG
	61	#define DBG(fmt...) udbg_printf(fmt)
	62	#else
	63	#define DBG(fmt...)
	64	#endif
	65
94833a42 AF	66	#define MV88E1111_SCR 0x10
	67	#define MV88E1111_SCR_125CLK 0x0010
	68	static int mpc8568_fixup_125_clock(struct phy_device *phydev)
	69	{
	70	int scr;
	71	int err;
	72
	73	/* Workaround for the 125 CLK Toggle */
	74	scr = phy_read(phydev, MV88E1111_SCR);
	75
	76	if (scr < 0)
	77	return scr;
	78
	79	err = phy_write(phydev, MV88E1111_SCR, scr & ~(MV88E1111_SCR_125CLK));
	80
	81	if (err)
	82	return err;
	83
	84	err = phy_write(phydev, MII_BMCR, BMCR_RESET);
	85
	86	if (err)
	87	return err;
	88
	89	scr = phy_read(phydev, MV88E1111_SCR);
	90
	91	if (scr < 0)
29827b02	92	return scr;
94833a42 AF	93
	94	err = phy_write(phydev, MV88E1111_SCR, scr \| 0x0008);
	95
	96	return err;
	97	}
	98
	99	static int mpc8568_mds_phy_fixups(struct phy_device *phydev)
	100	{
	101	int temp;
	102	int err;
	103
	104	/* Errata */
	105	err = phy_write(phydev,29, 0x0006);
	106
	107	if (err)
	108	return err;
	109
	110	temp = phy_read(phydev, 30);
	111
	112	if (temp < 0)
	113	return temp;
	114
	115	temp = (temp & (~0x8000)) \| 0x4000;
	116	err = phy_write(phydev,30, temp);
	117
	118	if (err)
	119	return err;
	120
	121	err = phy_write(phydev,29, 0x000a);
	122
	123	if (err)
	124	return err;
	125
	126	temp = phy_read(phydev, 30);
	127
	128	if (temp < 0)
	129	return temp;
	130
	131	temp = phy_read(phydev, 30);
	132
	133	if (temp < 0)
	134	return temp;
	135
	136	temp &= ~0x0020;
	137
	138	err = phy_write(phydev,30,temp);
	139
	140	if (err)
	141	return err;
	142
	143	/* Disable automatic MDI/MDIX selection */
	144	temp = phy_read(phydev, 16);
	145
	146	if (temp < 0)
	147	return temp;
	148
	149	temp &= ~0x0060;
	150	err = phy_write(phydev,16,temp);
	151
	152	return err;
	153	}
	154
c2882bb1 AF	155	/* ************************************************************************
	156	*
	157	* Setup the architecture
	158	*
	159	*/
dee9ad71	160	#ifdef CONFIG_QUICC_ENGINE
99d8238f	161	static void __init mpc85xx_mds_reset_ucc_phys(void)
c2882bb1 AF	162	{
c2882bb1 AF	163	struct device_node *np;
99d8238f	164	static u8 __iomem *bcsr_regs;
c2882bb1	165
c2882bb1 AF	166	/* Map BCSR area */
c2882bb1 AF	167	np = of_find_node_by_name(NULL, "bcsr");
99d8238f AV	168	if (!np)
99d8238f AV	169	return;
c2882bb1	170
99d8238f AV	171	bcsr_regs = of_iomap(np, 0);
	172	of_node_put(np);
	173	if (!bcsr_regs)
	174	return;
c2882bb1	175
99d8238f AV	176	if (machine_is(mpc8568_mds)) {
	177	#define BCSR_UCC1_GETH_EN (0x1 << 7)
	178	#define BCSR_UCC2_GETH_EN (0x1 << 7)
	179	#define BCSR_UCC1_MODE_MSK (0x3 << 4)
	180	#define BCSR_UCC2_MODE_MSK (0x3 << 0)
152d0182	181
99d8238f AV	182	/* Turn off UCC1 & UCC2 */
	183	clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
	184	clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
	185
	186	/* Mode is RGMII, all bits clear */
	187	clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK \|
	188	BCSR_UCC2_MODE_MSK);
	189
	190	/* Turn UCC1 & UCC2 on */
	191	setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
	192	setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
	193	} else if (machine_is(mpc8569_mds)) {
	194	#define BCSR7_UCC12_GETHnRST (0x1 << 2)
	195	#define BCSR8_UEM_MARVELL_RST (0x1 << 1)
	196	#define BCSR_UCC_RGMII (0x1 << 6)
	197	#define BCSR_UCC_RTBI (0x1 << 5)
	198	/*
	199	* U-Boot mangles interrupt polarity for Marvell PHYs,
	200	* so reset built-in and UEM Marvell PHYs, this puts
	201	* the PHYs into their normal state.
	202	*/
	203	clrbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
	204	setbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
	205
	206	setbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
	207	clrbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
	208
	209	for (np = NULL; (np = of_find_compatible_node(np,
	210	"network",
	211	"ucc_geth")) != NULL;) {
	212	const unsigned int *prop;
	213	int ucc_num;
	214
	215	prop = of_get_property(np, "cell-index", NULL);
	216	if (prop == NULL)
	217	continue;
	218
	219	ucc_num = *prop - 1;
	220
	221	prop = of_get_property(np, "phy-connection-type", NULL);
	222	if (prop == NULL)
	223	continue;
	224
	225	if (strcmp("rtbi", (const char *)prop) == 0)
	226	clrsetbits_8(&bcsr_regs[7 + ucc_num],
	227	BCSR_UCC_RGMII, BCSR_UCC_RTBI);
c9438aff	228	}
99d8238f AV	229	} else if (machine_is(p1021_mds)) {
	230	#define BCSR11_ENET_MICRST (0x1 << 5)
	231	/* Reset Micrel PHY */
	232	clrbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
	233	setbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
c9438aff	234	}
c2882bb1	235
99d8238f AV	236	iounmap(bcsr_regs);
99d8238f AV	237	}
48936a08	238
99d8238f AV	239	static void __init mpc85xx_mds_qe_init(void)
	240	{
	241	struct device_node *np;
48936a08	242
a2dd70a1 AV	243	np = of_find_compatible_node(NULL, NULL, "fsl,qe");
	244	if (!np) {
	245	np = of_find_node_by_name(NULL, "qe");
	246	if (!np)
	247	return;
c2882bb1 AF	248	}
c2882bb1 AF	249
dee9ad71 AV	250	if (!of_device_is_available(np)) {
	251	of_node_put(np);
	252	return;
	253	}
	254
a2dd70a1 AV	255	qe_reset();
	256	of_node_put(np);
	257
	258	np = of_find_node_by_name(NULL, "par_io");
	259	if (np) {
	260	struct device_node *ucc;
c2882bb1 AF	261
	262	par_io_init(np);
	263	of_node_put(np);
	264
a2dd70a1	265	for_each_node_by_name(ucc, "ucc")
c2882bb1	266	par_io_of_config(ucc);
c2882bb1 AF	267	}
c2882bb1 AF	268
99d8238f	269	mpc85xx_mds_reset_ucc_phys();
48936a08 HW	270
48936a08 HW	271	if (machine_is(p1021_mds)) {
48936a08	272
9cb6abcb	273	struct ccsr_guts __iomem *guts;
48936a08	274
c141b38f	275	np = of_find_node_by_name(NULL, "global-utilities");
48936a08	276	if (np) {
c141b38f ZF	277	guts = of_iomap(np, 0);
	278	if (!guts)
	279	pr_err("mpc85xx-rdb: could not map global utilities register\n");
	280	else{
48936a08 HW	281	/* P1021 has pins muxed for QE and other functions. To
	282	* enable QE UEC mode, we need to set bit QE0 for UCC1
	283	* in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
8dd11f80	284	* and QE12 for QE MII management signals in PMUXCR
48936a08 HW	285	* register.
48936a08 HW	286	*/
c141b38f ZF	287	setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) \|
	288	MPC85xx_PMUXCR_QE(3) \|
	289	MPC85xx_PMUXCR_QE(9) \|
	290	MPC85xx_PMUXCR_QE(12));
	291	iounmap(guts);
	292	}
48936a08 HW	293	of_node_put(np);
	294	}
	295
	296	}
99d8238f AV	297	}
	298
	299	static void __init mpc85xx_mds_qeic_init(void)
	300	{
	301	struct device_node *np;
	302
	303	np = of_find_compatible_node(NULL, NULL, "fsl,qe");
	304	if (!of_device_is_available(np)) {
	305	of_node_put(np);
	306	return;
	307	}
	308
	309	np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
	310	if (!np) {
	311	np = of_find_node_by_type(NULL, "qeic");
	312	if (!np)
	313	return;
	314	}
	315
	316	if (machine_is(p1021_mds))
	317	qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
	318	qe_ic_cascade_high_mpic);
	319	else
	320	qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
	321	of_node_put(np);
	322	}
	323	#else
99d8238f AV	324	static void __init mpc85xx_mds_qe_init(void) { }
99d8238f AV	325	static void __init mpc85xx_mds_qeic_init(void) { }
c2882bb1	326	#endif /* CONFIG_QUICC_ENGINE */
152d0182	327
99d8238f AV	328	static void __init mpc85xx_mds_setup_arch(void)
99d8238f AV	329	{
99d8238f AV	330	if (ppc_md.progress)
	331	ppc_md.progress("mpc85xx_mds_setup_arch()", 0);
	332
99d8238f	333	mpc85xx_smp_init();
99d8238f AV	334
	335	mpc85xx_mds_qe_init();
	336
905e75c4 JH	337	fsl_pci_assign_primary();
	338
	339	swiotlb_detect_4g();
c2882bb1 AF	340	}
c2882bb1 AF	341
94833a42 AF	342
	343	static int __init board_fixups(void)
	344	{
aab0d375	345	char phy_id[20];
94833a42 AF	346	char *compstrs[2] = {"fsl,gianfar-mdio", "fsl,ucc-mdio"};
	347	struct device_node *mdio;
	348	struct resource res;
	349	int i;
	350
	351	for (i = 0; i < ARRAY_SIZE(compstrs); i++) {
	352	mdio = of_find_compatible_node(NULL, NULL, compstrs[i]);
	353
	354	of_address_to_resource(mdio, 0, &res);
aab0d375	355	snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
24a99596	356	(unsigned long long)res.start, 1);
94833a42 AF	357
	358	phy_register_fixup_for_id(phy_id, mpc8568_fixup_125_clock);
	359	phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
	360
	361	/* Register a workaround for errata */
aab0d375	362	snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
24a99596	363	(unsigned long long)res.start, 7);
94833a42 AF	364	phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
	365
	366	of_node_put(mdio);
	367	}
	368
	369	return 0;
	370	}
ea5130dc	371	machine_arch_initcall(mpc8568_mds, board_fixups);
4b3b42b3	372	machine_arch_initcall(mpc8569_mds, board_fixups);
94833a42	373
23f510bc	374	static int __init mpc85xx_publish_devices(void)
c2882bb1	375	{
e98efaf3 AV	376	if (machine_is(mpc8568_mds))
e98efaf3 AV	377	simple_gpiochip_init("fsl,mpc8568mds-bcsr-gpio");
9b9d401b AV	378	if (machine_is(mpc8569_mds))
	379	simple_gpiochip_init("fsl,mpc8569mds-bcsr-gpio");
	380
8a95bc8d	381	return mpc85xx_common_publish_devices();
48936a08 HW	382	}
48936a08 HW	383
905e75c4 JH	384	machine_arch_initcall(mpc8568_mds, mpc85xx_publish_devices);
	385	machine_arch_initcall(mpc8569_mds, mpc85xx_publish_devices);
	386	machine_arch_initcall(p1021_mds, mpc85xx_common_publish_devices);
c2882bb1	387
152d0182 KG	388	machine_arch_initcall(mpc8568_mds, swiotlb_setup_bus_notifier);
152d0182 KG	389	machine_arch_initcall(mpc8569_mds, swiotlb_setup_bus_notifier);
48936a08	390	machine_arch_initcall(p1021_mds, swiotlb_setup_bus_notifier);
152d0182	391
23f510bc	392	static void __init mpc85xx_mds_pic_init(void)
c2882bb1	393	{
e55d7f73	394	struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN \|
5019609f	395	MPIC_SINGLE_DEST_CPU,
b533f8ae	396	0, 256, " OpenPIC ");
c2882bb1	397	BUG_ON(mpic == NULL);
c2882bb1	398
c2882bb1	399	mpic_init(mpic);
99d8238f	400	mpc85xx_mds_qeic_init();
c2882bb1 AF	401	}
c2882bb1 AF	402
23f510bc	403	static int __init mpc85xx_mds_probe(void)
c2882bb1	404	{
6936c625	405	unsigned long root = of_get_flat_dt_root();
c2882bb1	406
6936c625	407	return of_flat_dt_is_compatible(root, "MPC85xxMDS");
c2882bb1 AF	408	}
c2882bb1 AF	409
ea5130dc HW	410	define_machine(mpc8568_mds) {
ea5130dc HW	411	.name = "MPC8568 MDS",
23f510bc KG	412	.probe = mpc85xx_mds_probe,
	413	.setup_arch = mpc85xx_mds_setup_arch,
	414	.init_IRQ = mpc85xx_mds_pic_init,
c2882bb1	415	.get_irq = mpic_get_irq,
e1c1575f	416	.restart = fsl_rstcr_restart,
c2882bb1 AF	417	.calibrate_decr = generic_calibrate_decr,
c2882bb1 AF	418	.progress = udbg_progress,
2af8569d	419	#ifdef CONFIG_PCI
aa3c1121	420	.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
2af8569d	421	#endif
c2882bb1	422	};
4b3b42b3 HW	423
	424	static int __init mpc8569_mds_probe(void)
	425	{
	426	unsigned long root = of_get_flat_dt_root();
	427
	428	return of_flat_dt_is_compatible(root, "fsl,MPC8569EMDS");
	429	}
	430
	431	define_machine(mpc8569_mds) {
	432	.name = "MPC8569 MDS",
	433	.probe = mpc8569_mds_probe,
	434	.setup_arch = mpc85xx_mds_setup_arch,
	435	.init_IRQ = mpc85xx_mds_pic_init,
	436	.get_irq = mpic_get_irq,
	437	.restart = fsl_rstcr_restart,
	438	.calibrate_decr = generic_calibrate_decr,
	439	.progress = udbg_progress,
	440	#ifdef CONFIG_PCI
	441	.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
	442	#endif
	443	};
48936a08 HW	444
	445	static int __init p1021_mds_probe(void)
	446	{
	447	unsigned long root = of_get_flat_dt_root();
	448
	449	return of_flat_dt_is_compatible(root, "fsl,P1021MDS");
	450
	451	}
	452
	453	define_machine(p1021_mds) {
	454	.name = "P1021 MDS",
	455	.probe = p1021_mds_probe,
	456	.setup_arch = mpc85xx_mds_setup_arch,
	457	.init_IRQ = mpc85xx_mds_pic_init,
	458	.get_irq = mpic_get_irq,
	459	.restart = fsl_rstcr_restart,
	460	.calibrate_decr = generic_calibrate_decr,
	461	.progress = udbg_progress,
	462	#ifdef CONFIG_PCI
	463	.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
	464	#endif
	465	};
	466