[deliverable/linux.git] / arch / powerpc / platforms / 85xx / smp.c

/*
 * Author: Andy Fleming <afleming@freescale.com>
 * 	   Kumar Gala <galak@kernel.crashing.org>
 *
 * Copyright 2006-2008, 2011-2012 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/kexec.h>
#include <linux/highmem.h>
#include <linux/cpu.h>

#include <asm/machdep.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/mpic.h>
#include <asm/cacheflush.h>
#include <asm/dbell.h>
#include <asm/fsl_guts.h>

#include <sysdev/fsl_soc.h>
#include <sysdev/mpic.h>
#include "smp.h"

struct epapr_spin_table {
	u32	addr_h;
	u32	addr_l;
	u32	r3_h;
	u32	r3_l;
	u32	reserved;
	u32	pir;
};

static struct ccsr_guts __iomem *guts;
static u64 timebase;
static int tb_req;
static int tb_valid;

static void mpc85xx_timebase_freeze(int freeze)
{
	uint32_t mask;

	mask = CCSR_GUTS_DEVDISR_TB0 | CCSR_GUTS_DEVDISR_TB1;
	if (freeze)
		setbits32(&guts->devdisr, mask);
	else
		clrbits32(&guts->devdisr, mask);

	in_be32(&guts->devdisr);
}

static void mpc85xx_give_timebase(void)
{
	unsigned long flags;

	local_irq_save(flags);

	while (!tb_req)
		barrier();
	tb_req = 0;

	mpc85xx_timebase_freeze(1);
#ifdef CONFIG_PPC64
	/*
	 * e5500/e6500 have a workaround for erratum A-006958 in place
	 * that will reread the timebase until TBL is non-zero.
	 * That would be a bad thing when the timebase is frozen.
	 *
	 * Thus, we read it manually, and instead of checking that
	 * TBL is non-zero, we ensure that TB does not change.  We don't
	 * do that for the main mftb implementation, because it requires
	 * a scratch register
	 */
	{
		u64 prev;

		asm volatile("mfspr %0, %1" : "=r" (timebase) :
			     "i" (SPRN_TBRL));

		do {
			prev = timebase;
			asm volatile("mfspr %0, %1" : "=r" (timebase) :
				     "i" (SPRN_TBRL));
		} while (prev != timebase);
	}
#else
	timebase = get_tb();
#endif
	mb();
	tb_valid = 1;

	while (tb_valid)
		barrier();

	mpc85xx_timebase_freeze(0);

	local_irq_restore(flags);
}

static void mpc85xx_take_timebase(void)
{
	unsigned long flags;

	local_irq_save(flags);

	tb_req = 1;
	while (!tb_valid)
		barrier();

	set_tb(timebase >> 32, timebase & 0xffffffff);
	isync();
	tb_valid = 0;

	local_irq_restore(flags);
}

#ifdef CONFIG_HOTPLUG_CPU
static void smp_85xx_mach_cpu_die(void)
{
	unsigned int cpu = smp_processor_id();
	u32 tmp;

	local_irq_disable();
	idle_task_exit();
	generic_set_cpu_dead(cpu);
	mb();

	mtspr(SPRN_TCR, 0);

	__flush_disable_L1();
	tmp = (mfspr(SPRN_HID0) & ~(HID0_DOZE|HID0_SLEEP)) | HID0_NAP;
	mtspr(SPRN_HID0, tmp);
	isync();

	/* Enter NAP mode. */
	tmp = mfmsr();
	tmp |= MSR_WE;
	mb();
	mtmsr(tmp);
	isync();

	while (1)
		;
}
#endif

static inline void flush_spin_table(void *spin_table)
{
	flush_dcache_range((ulong)spin_table,
		(ulong)spin_table + sizeof(struct epapr_spin_table));
}

static inline u32 read_spin_table_addr_l(void *spin_table)
{
	flush_dcache_range((ulong)spin_table,
		(ulong)spin_table + sizeof(struct epapr_spin_table));
	return in_be32(&((struct epapr_spin_table *)spin_table)->addr_l);
}

static int smp_85xx_kick_cpu(int nr)
{
	unsigned long flags;
	const u64 *cpu_rel_addr;
	__iomem struct epapr_spin_table *spin_table;
	struct device_node *np;
	int hw_cpu = get_hard_smp_processor_id(nr);
	int ioremappable;
	int ret = 0;

	WARN_ON(nr < 0 || nr >= NR_CPUS);
	WARN_ON(hw_cpu < 0 || hw_cpu >= NR_CPUS);

	pr_debug("smp_85xx_kick_cpu: kick CPU #%d\n", nr);

	np = of_get_cpu_node(nr, NULL);
	cpu_rel_addr = of_get_property(np, "cpu-release-addr", NULL);

	if (cpu_rel_addr == NULL) {
		printk(KERN_ERR "No cpu-release-addr for cpu %d\n", nr);
		return -ENOENT;
	}

	/*
	 * A secondary core could be in a spinloop in the bootpage
	 * (0xfffff000), somewhere in highmem, or somewhere in lowmem.
	 * The bootpage and highmem can be accessed via ioremap(), but
	 * we need to directly access the spinloop if its in lowmem.
	 */
	ioremappable = *cpu_rel_addr > virt_to_phys(high_memory);

	/* Map the spin table */
	if (ioremappable)
		spin_table = ioremap_prot(*cpu_rel_addr,
			sizeof(struct epapr_spin_table), _PAGE_COHERENT);
	else
		spin_table = phys_to_virt(*cpu_rel_addr);

	local_irq_save(flags);
#ifdef CONFIG_PPC32
#ifdef CONFIG_HOTPLUG_CPU
	/* Corresponding to generic_set_cpu_dead() */
	generic_set_cpu_up(nr);

	if (system_state == SYSTEM_RUNNING) {
		/*
		 * To keep it compatible with old boot program which uses
		 * cache-inhibit spin table, we need to flush the cache
		 * before accessing spin table to invalidate any staled data.
		 * We also need to flush the cache after writing to spin
		 * table to push data out.
		 */
		flush_spin_table(spin_table);
		out_be32(&spin_table->addr_l, 0);
		flush_spin_table(spin_table);

		/*
		 * We don't set the BPTR register here since it already points
		 * to the boot page properly.
		 */
		mpic_reset_core(nr);

		/*
		 * wait until core is ready...
		 * We need to invalidate the stale data, in case the boot
		 * loader uses a cache-inhibited spin table.
		 */
		if (!spin_event_timeout(
				read_spin_table_addr_l(spin_table) == 1,
				10000, 100)) {
			pr_err("%s: timeout waiting for core %d to reset\n",
							__func__, hw_cpu);
			ret = -ENOENT;
			goto out;
		}

		/*  clear the acknowledge status */
		__secondary_hold_acknowledge = -1;
	}
#endif
	flush_spin_table(spin_table);
	out_be32(&spin_table->pir, hw_cpu);
	out_be32(&spin_table->addr_l, __pa(__early_start));
	flush_spin_table(spin_table);

	/* Wait a bit for the CPU to ack. */
	if (!spin_event_timeout(__secondary_hold_acknowledge == hw_cpu,
					10000, 100)) {
		pr_err("%s: timeout waiting for core %d to ack\n",
						__func__, hw_cpu);
		ret = -ENOENT;
		goto out;
	}
out:
#else
	smp_generic_kick_cpu(nr);

	flush_spin_table(spin_table);
	out_be32(&spin_table->pir, hw_cpu);
	out_be64((u64 *)(&spin_table->addr_h),
	  __pa((u64)*((unsigned long long *)generic_secondary_smp_init)));
	flush_spin_table(spin_table);
#endif

	local_irq_restore(flags);

	if (ioremappable)
		iounmap(spin_table);

	return ret;
}

struct smp_ops_t smp_85xx_ops = {
	.kick_cpu = smp_85xx_kick_cpu,
	.cpu_bootable = smp_generic_cpu_bootable,
#ifdef CONFIG_HOTPLUG_CPU
	.cpu_disable	= generic_cpu_disable,
	.cpu_die	= generic_cpu_die,
#endif
#ifdef CONFIG_KEXEC
	.give_timebase	= smp_generic_give_timebase,
	.take_timebase	= smp_generic_take_timebase,
#endif
};

#ifdef CONFIG_KEXEC
atomic_t kexec_down_cpus = ATOMIC_INIT(0);

void mpc85xx_smp_kexec_cpu_down(int crash_shutdown, int secondary)
{
	local_irq_disable();

	if (secondary) {
		atomic_inc(&kexec_down_cpus);
		/* loop forever */
		while (1);
	}
}

static void mpc85xx_smp_kexec_down(void *arg)
{
	if (ppc_md.kexec_cpu_down)
		ppc_md.kexec_cpu_down(0,1);
}

static void map_and_flush(unsigned long paddr)
{
	struct page *page = pfn_to_page(paddr >> PAGE_SHIFT);
	unsigned long kaddr  = (unsigned long)kmap(page);

	flush_dcache_range(kaddr, kaddr + PAGE_SIZE);
	kunmap(page);
}

/**
 * Before we reset the other cores, we need to flush relevant cache
 * out to memory so we don't get anything corrupted, some of these flushes
 * are performed out of an overabundance of caution as interrupts are not
 * disabled yet and we can switch cores
 */
static void mpc85xx_smp_flush_dcache_kexec(struct kimage *image)
{
	kimage_entry_t *ptr, entry;
	unsigned long paddr;
	int i;

	if (image->type == KEXEC_TYPE_DEFAULT) {
		/* normal kexec images are stored in temporary pages */
		for (ptr = &image->head; (entry = *ptr) && !(entry & IND_DONE);
		     ptr = (entry & IND_INDIRECTION) ?
				phys_to_virt(entry & PAGE_MASK) : ptr + 1) {
			if (!(entry & IND_DESTINATION)) {
				map_and_flush(entry);
			}
		}
		/* flush out last IND_DONE page */
		map_and_flush(entry);
	} else {
		/* crash type kexec images are copied to the crash region */
		for (i = 0; i < image->nr_segments; i++) {
			struct kexec_segment *seg = &image->segment[i];
			for (paddr = seg->mem; paddr < seg->mem + seg->memsz;
			     paddr += PAGE_SIZE) {
				map_and_flush(paddr);
			}
		}
	}

	/* also flush the kimage struct to be passed in as well */
	flush_dcache_range((unsigned long)image,
			   (unsigned long)image + sizeof(*image));
}

static void mpc85xx_smp_machine_kexec(struct kimage *image)
{
	int timeout = INT_MAX;
	int i, num_cpus = num_present_cpus();

	mpc85xx_smp_flush_dcache_kexec(image);

	if (image->type == KEXEC_TYPE_DEFAULT)
		smp_call_function(mpc85xx_smp_kexec_down, NULL, 0);

	while ( (atomic_read(&kexec_down_cpus) != (num_cpus - 1)) &&
		( timeout > 0 ) )
	{
		timeout--;
	}

	if ( !timeout )
		printk(KERN_ERR "Unable to bring down secondary cpu(s)");

	for_each_online_cpu(i)
	{
		if ( i == smp_processor_id() ) continue;
		mpic_reset_core(i);
	}

	default_machine_kexec(image);
}
#endif /* CONFIG_KEXEC */

static void smp_85xx_setup_cpu(int cpu_nr)
{
	if (smp_85xx_ops.probe == smp_mpic_probe)
		mpic_setup_this_cpu();

	if (cpu_has_feature(CPU_FTR_DBELL))
		doorbell_setup_this_cpu();
}

static const struct of_device_id mpc85xx_smp_guts_ids[] = {
	{ .compatible = "fsl,mpc8572-guts", },
	{ .compatible = "fsl,p1020-guts", },
	{ .compatible = "fsl,p1021-guts", },
	{ .compatible = "fsl,p1022-guts", },
	{ .compatible = "fsl,p1023-guts", },
	{ .compatible = "fsl,p2020-guts", },
	{},
};

void __init mpc85xx_smp_init(void)
{
	struct device_node *np;

	smp_85xx_ops.setup_cpu = smp_85xx_setup_cpu;

	np = of_find_node_by_type(NULL, "open-pic");
	if (np) {
		smp_85xx_ops.probe = smp_mpic_probe;
		smp_85xx_ops.message_pass = smp_mpic_message_pass;
	}

	if (cpu_has_feature(CPU_FTR_DBELL)) {
		/*
		 * If left NULL, .message_pass defaults to
		 * smp_muxed_ipi_message_pass
		 */
		smp_85xx_ops.message_pass = NULL;
		smp_85xx_ops.cause_ipi = doorbell_cause_ipi;
	}

	np = of_find_matching_node(NULL, mpc85xx_smp_guts_ids);
	if (np) {
		guts = of_iomap(np, 0);
		of_node_put(np);
		if (!guts) {
			pr_err("%s: Could not map guts node address\n",
								__func__);
			return;
		}
		smp_85xx_ops.give_timebase = mpc85xx_give_timebase;
		smp_85xx_ops.take_timebase = mpc85xx_take_timebase;
#ifdef CONFIG_HOTPLUG_CPU
		ppc_md.cpu_die = smp_85xx_mach_cpu_die;
#endif
	}

	smp_ops = &smp_85xx_ops;

#ifdef CONFIG_KEXEC
	ppc_md.kexec_cpu_down = mpc85xx_smp_kexec_cpu_down;
	ppc_md.machine_kexec = mpc85xx_smp_machine_kexec;
#endif
}
Commit	Line	Data
d5b26db2 KG	1	/*
	2	* Author: Andy Fleming <afleming@freescale.com>
	3	* Kumar Gala <galak@kernel.crashing.org>
	4	*
15f34eb1	5	* Copyright 2006-2008, 2011-2012 Freescale Semiconductor Inc.
d5b26db2 KG	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License as published by the
	9	* Free Software Foundation; either version 2 of the License, or (at your
	10	* option) any later version.
	11	*/
	12
	13	#include <linux/stddef.h>
	14	#include <linux/kernel.h>
	15	#include <linux/init.h>
	16	#include <linux/delay.h>
	17	#include <linux/of.h>
c11eede6	18	#include <linux/of_address.h>
f933a41e	19	#include <linux/kexec.h>
677de425	20	#include <linux/highmem.h>
15f34eb1	21	#include <linux/cpu.h>
d5b26db2 KG	22
	23	#include <asm/machdep.h>
	24	#include <asm/pgtable.h>
	25	#include <asm/page.h>
	26	#include <asm/mpic.h>
	27	#include <asm/cacheflush.h>
563fdd4a	28	#include <asm/dbell.h>
bf345263	29	#include <asm/fsl_guts.h>
d5b26db2 KG	30
d5b26db2 KG	31	#include <sysdev/fsl_soc.h>
f933a41e	32	#include <sysdev/mpic.h>
582d3e09	33	#include "smp.h"
d5b26db2	34
15f34eb1 ZC	35	struct epapr_spin_table {
	36	u32 addr_h;
	37	u32 addr_l;
	38	u32 r3_h;
	39	u32 r3_l;
	40	u32 reserved;
	41	u32 pir;
	42	};
d5b26db2	43
bf345263 ZC	44	static struct ccsr_guts __iomem *guts;
	45	static u64 timebase;
	46	static int tb_req;
	47	static int tb_valid;
	48
	49	static void mpc85xx_timebase_freeze(int freeze)
	50	{
	51	uint32_t mask;
	52
	53	mask = CCSR_GUTS_DEVDISR_TB0 \| CCSR_GUTS_DEVDISR_TB1;
	54	if (freeze)
	55	setbits32(&guts->devdisr, mask);
	56	else
	57	clrbits32(&guts->devdisr, mask);
	58
	59	in_be32(&guts->devdisr);
	60	}
	61
	62	static void mpc85xx_give_timebase(void)
	63	{
	64	unsigned long flags;
	65
	66	local_irq_save(flags);
	67
	68	while (!tb_req)
	69	barrier();
	70	tb_req = 0;
	71
	72	mpc85xx_timebase_freeze(1);
d52459ca SW	73	#ifdef CONFIG_PPC64
	74	/*
	75	* e5500/e6500 have a workaround for erratum A-006958 in place
	76	* that will reread the timebase until TBL is non-zero.
	77	* That would be a bad thing when the timebase is frozen.
	78	*
	79	* Thus, we read it manually, and instead of checking that
	80	* TBL is non-zero, we ensure that TB does not change. We don't
	81	* do that for the main mftb implementation, because it requires
	82	* a scratch register
	83	*/
	84	{
	85	u64 prev;
	86
beb2dc0a SW	87	asm volatile("mfspr %0, %1" : "=r" (timebase) :
beb2dc0a SW	88	"i" (SPRN_TBRL));
d52459ca SW	89
	90	do {
	91	prev = timebase;
beb2dc0a SW	92	asm volatile("mfspr %0, %1" : "=r" (timebase) :
beb2dc0a SW	93	"i" (SPRN_TBRL));
d52459ca SW	94	} while (prev != timebase);
	95	}
	96	#else
bf345263	97	timebase = get_tb();
d52459ca	98	#endif
bf345263 ZC	99	mb();
	100	tb_valid = 1;
	101
	102	while (tb_valid)
	103	barrier();
	104
	105	mpc85xx_timebase_freeze(0);
	106
	107	local_irq_restore(flags);
	108	}
	109
	110	static void mpc85xx_take_timebase(void)
	111	{
	112	unsigned long flags;
	113
	114	local_irq_save(flags);
	115
	116	tb_req = 1;
	117	while (!tb_valid)
	118	barrier();
	119
	120	set_tb(timebase >> 32, timebase & 0xffffffff);
	121	isync();
	122	tb_valid = 0;
	123
	124	local_irq_restore(flags);
	125	}
	126
d0832a75	127	#ifdef CONFIG_HOTPLUG_CPU
061d19f2	128	static void smp_85xx_mach_cpu_die(void)
d0832a75 ZC	129	{
	130	unsigned int cpu = smp_processor_id();
	131	u32 tmp;
	132
	133	local_irq_disable();
	134	idle_task_exit();
	135	generic_set_cpu_dead(cpu);
	136	mb();
	137
	138	mtspr(SPRN_TCR, 0);
	139
	140	__flush_disable_L1();
	141	tmp = (mfspr(SPRN_HID0) & ~(HID0_DOZE\|HID0_SLEEP)) \| HID0_NAP;
	142	mtspr(SPRN_HID0, tmp);
	143	isync();
	144
	145	/* Enter NAP mode. */
	146	tmp = mfmsr();
	147	tmp \|= MSR_WE;
	148	mb();
	149	mtmsr(tmp);
	150	isync();
	151
	152	while (1)
	153	;
	154	}
	155	#endif
	156
bc15236f YS	157	static inline void flush_spin_table(void *spin_table)
	158	{
	159	flush_dcache_range((ulong)spin_table,
	160	(ulong)spin_table + sizeof(struct epapr_spin_table));
	161	}
	162
	163	static inline u32 read_spin_table_addr_l(void *spin_table)
	164	{
	165	flush_dcache_range((ulong)spin_table,
	166	(ulong)spin_table + sizeof(struct epapr_spin_table));
	167	return in_be32(&((struct epapr_spin_table *)spin_table)->addr_l);
	168	}
	169
061d19f2	170	static int smp_85xx_kick_cpu(int nr)
d5b26db2 KG	171	{
	172	unsigned long flags;
	173	const u64 *cpu_rel_addr;
15f34eb1	174	__iomem struct epapr_spin_table *spin_table;
d5b26db2	175	struct device_node *np;
d0832a75	176	int hw_cpu = get_hard_smp_processor_id(nr);
d1d47ec6	177	int ioremappable;
d0832a75	178	int ret = 0;
d5b26db2	179
45116806 KG	180	WARN_ON(nr < 0 \|\| nr >= NR_CPUS);
45116806 KG	181	WARN_ON(hw_cpu < 0 \|\| hw_cpu >= NR_CPUS);
d5b26db2 KG	182
	183	pr_debug("smp_85xx_kick_cpu: kick CPU #%d\n", nr);
	184
d5b26db2 KG	185	np = of_get_cpu_node(nr, NULL);
	186	cpu_rel_addr = of_get_property(np, "cpu-release-addr", NULL);
	187
	188	if (cpu_rel_addr == NULL) {
	189	printk(KERN_ERR "No cpu-release-addr for cpu %d\n", nr);
de300974	190	return -ENOENT;
d5b26db2 KG	191	}
d5b26db2 KG	192
d1d47ec6 PT	193	/*
	194	* A secondary core could be in a spinloop in the bootpage
	195	* (0xfffff000), somewhere in highmem, or somewhere in lowmem.
	196	* The bootpage and highmem can be accessed via ioremap(), but
	197	* we need to directly access the spinloop if its in lowmem.
	198	*/
	199	ioremappable = *cpu_rel_addr > virt_to_phys(high_memory);
	200
d5b26db2	201	/* Map the spin table */
d1d47ec6	202	if (ioremappable)
bc15236f YS	203	spin_table = ioremap_prot(*cpu_rel_addr,
bc15236f YS	204	sizeof(struct epapr_spin_table), _PAGE_COHERENT);
d1d47ec6	205	else
15f34eb1	206	spin_table = phys_to_virt(*cpu_rel_addr);
d5b26db2	207
cb1ffb62	208	local_irq_save(flags);
d0832a75 ZC	209	#ifdef CONFIG_PPC32
	210	#ifdef CONFIG_HOTPLUG_CPU
	211	/* Corresponding to generic_set_cpu_dead() */
	212	generic_set_cpu_up(nr);
	213
	214	if (system_state == SYSTEM_RUNNING) {
bc15236f YS	215	/*
	216	* To keep it compatible with old boot program which uses
	217	* cache-inhibit spin table, we need to flush the cache
	218	* before accessing spin table to invalidate any staled data.
	219	* We also need to flush the cache after writing to spin
	220	* table to push data out.
	221	*/
	222	flush_spin_table(spin_table);
d0832a75	223	out_be32(&spin_table->addr_l, 0);
bc15236f	224	flush_spin_table(spin_table);
cb1ffb62	225
d0832a75 ZC	226	/*
	227	* We don't set the BPTR register here since it already points
	228	* to the boot page properly.
	229	*/
ddb487dc	230	mpic_reset_core(nr);
d0832a75	231
bc15236f YS	232	/*
	233	* wait until core is ready...
	234	* We need to invalidate the stale data, in case the boot
	235	* loader uses a cache-inhibited spin table.
	236	*/
	237	if (!spin_event_timeout(
	238	read_spin_table_addr_l(spin_table) == 1,
	239	10000, 100)) {
d0832a75 ZC	240	pr_err("%s: timeout waiting for core %d to reset\n",
	241	__func__, hw_cpu);
	242	ret = -ENOENT;
	243	goto out;
	244	}
	245
	246	/* clear the acknowledge status */
	247	__secondary_hold_acknowledge = -1;
	248	}
	249	#endif
bc15236f	250	flush_spin_table(spin_table);
15f34eb1	251	out_be32(&spin_table->pir, hw_cpu);
15f34eb1	252	out_be32(&spin_table->addr_l, __pa(__early_start));
bc15236f	253	flush_spin_table(spin_table);
d1d47ec6	254
d5b26db2	255	/* Wait a bit for the CPU to ack. */
d0832a75 ZC	256	if (!spin_event_timeout(__secondary_hold_acknowledge == hw_cpu,
	257	10000, 100)) {
	258	pr_err("%s: timeout waiting for core %d to ack\n",
	259	__func__, hw_cpu);
	260	ret = -ENOENT;
	261	goto out;
	262	}
	263	out:
5b8544c3	264	#else
decbb280 KG	265	smp_generic_kick_cpu(nr);
decbb280 KG	266
bc15236f	267	flush_spin_table(spin_table);
d0832a75	268	out_be32(&spin_table->pir, hw_cpu);
15f34eb1 ZC	269	out_be64((u64 *)(&spin_table->addr_h),
15f34eb1 ZC	270	__pa((u64)((unsigned long long )generic_secondary_smp_init)));
bc15236f	271	flush_spin_table(spin_table);
5b8544c3	272	#endif
d5b26db2	273
d5b26db2 KG	274	local_irq_restore(flags);
d5b26db2 KG	275
d1d47ec6	276	if (ioremappable)
15f34eb1	277	iounmap(spin_table);
cb1ffb62	278
d0832a75	279	return ret;
d5b26db2 KG	280	}
d5b26db2 KG	281
d5b26db2	282	struct smp_ops_t smp_85xx_ops = {
d5b26db2	283	.kick_cpu = smp_85xx_kick_cpu,
39fd4027	284	.cpu_bootable = smp_generic_cpu_bootable,
d0832a75 ZC	285	#ifdef CONFIG_HOTPLUG_CPU
	286	.cpu_disable = generic_cpu_disable,
	287	.cpu_die = generic_cpu_die,
	288	#endif
f933a41e MM	289	#ifdef CONFIG_KEXEC
	290	.give_timebase = smp_generic_give_timebase,
	291	.take_timebase = smp_generic_take_timebase,
	292	#endif
d5b26db2 KG	293	};
d5b26db2 KG	294
f933a41e	295	#ifdef CONFIG_KEXEC
5d692961	296	atomic_t kexec_down_cpus = ATOMIC_INIT(0);
f933a41e MM	297
	298	void mpc85xx_smp_kexec_cpu_down(int crash_shutdown, int secondary)
	299	{
5d692961	300	local_irq_disable();
f933a41e	301
5d692961 MM	302	if (secondary) {
	303	atomic_inc(&kexec_down_cpus);
	304	/* loop forever */
f933a41e MM	305	while (1);
	306	}
	307	}
	308
	309	static void mpc85xx_smp_kexec_down(void *arg)
	310	{
	311	if (ppc_md.kexec_cpu_down)
	312	ppc_md.kexec_cpu_down(0,1);
	313	}
	314
677de425 MM	315	static void map_and_flush(unsigned long paddr)
	316	{
	317	struct page *page = pfn_to_page(paddr >> PAGE_SHIFT);
	318	unsigned long kaddr = (unsigned long)kmap(page);
	319
	320	flush_dcache_range(kaddr, kaddr + PAGE_SIZE);
	321	kunmap(page);
	322	}
	323
	324	/**
	325	* Before we reset the other cores, we need to flush relevant cache
	326	* out to memory so we don't get anything corrupted, some of these flushes
	327	* are performed out of an overabundance of caution as interrupts are not
	328	* disabled yet and we can switch cores
	329	*/
	330	static void mpc85xx_smp_flush_dcache_kexec(struct kimage *image)
	331	{
	332	kimage_entry_t *ptr, entry;
	333	unsigned long paddr;
	334	int i;
	335
	336	if (image->type == KEXEC_TYPE_DEFAULT) {
	337	/* normal kexec images are stored in temporary pages */
	338	for (ptr = &image->head; (entry = *ptr) && !(entry & IND_DONE);
	339	ptr = (entry & IND_INDIRECTION) ?
	340	phys_to_virt(entry & PAGE_MASK) : ptr + 1) {
	341	if (!(entry & IND_DESTINATION)) {
	342	map_and_flush(entry);
	343	}
	344	}
	345	/* flush out last IND_DONE page */
	346	map_and_flush(entry);
	347	} else {
	348	/* crash type kexec images are copied to the crash region */
	349	for (i = 0; i < image->nr_segments; i++) {
	350	struct kexec_segment *seg = &image->segment[i];
	351	for (paddr = seg->mem; paddr < seg->mem + seg->memsz;
	352	paddr += PAGE_SIZE) {
	353	map_and_flush(paddr);
	354	}
	355	}
	356	}
	357
	358	/* also flush the kimage struct to be passed in as well */
	359	flush_dcache_range((unsigned long)image,
	360	(unsigned long)image + sizeof(*image));
	361	}
	362
f933a41e MM	363	static void mpc85xx_smp_machine_kexec(struct kimage *image)
f933a41e MM	364	{
5d692961 MM	365	int timeout = INT_MAX;
5d692961 MM	366	int i, num_cpus = num_present_cpus();
f933a41e	367
677de425	368	mpc85xx_smp_flush_dcache_kexec(image);
f933a41e	369
5d692961 MM	370	if (image->type == KEXEC_TYPE_DEFAULT)
5d692961 MM	371	smp_call_function(mpc85xx_smp_kexec_down, NULL, 0);
f933a41e	372
5d692961	373	while ( (atomic_read(&kexec_down_cpus) != (num_cpus - 1)) &&
f933a41e MM	374	( timeout > 0 ) )
	375	{
	376	timeout--;
	377	}
	378
	379	if ( !timeout )
	380	printk(KERN_ERR "Unable to bring down secondary cpu(s)");
	381
43a327b7	382	for_each_online_cpu(i)
f933a41e MM	383	{
	384	if ( i == smp_processor_id() ) continue;
	385	mpic_reset_core(i);
	386	}
	387
	388	default_machine_kexec(image);
	389	}
	390	#endif /* CONFIG_KEXEC */
	391
061d19f2	392	static void smp_85xx_setup_cpu(int cpu_nr)
dc2c9c52 SW	393	{
	394	if (smp_85xx_ops.probe == smp_mpic_probe)
	395	mpic_setup_this_cpu();
	396
	397	if (cpu_has_feature(CPU_FTR_DBELL))
	398	doorbell_setup_this_cpu();
	399	}
	400
bf345263 ZC	401	static const struct of_device_id mpc85xx_smp_guts_ids[] = {
	402	{ .compatible = "fsl,mpc8572-guts", },
	403	{ .compatible = "fsl,p1020-guts", },
	404	{ .compatible = "fsl,p1021-guts", },
	405	{ .compatible = "fsl,p1022-guts", },
	406	{ .compatible = "fsl,p1023-guts", },
	407	{ .compatible = "fsl,p2020-guts", },
	408	{},
	409	};
	410
563fdd4a KG	411	void __init mpc85xx_smp_init(void)
	412	{
	413	struct device_node *np;
	414
dc2c9c52 SW	415	smp_85xx_ops.setup_cpu = smp_85xx_setup_cpu;
dc2c9c52 SW	416
563fdd4a KG	417	np = of_find_node_by_type(NULL, "open-pic");
	418	if (np) {
	419	smp_85xx_ops.probe = smp_mpic_probe;
563fdd4a	420	smp_85xx_ops.message_pass = smp_mpic_message_pass;
563fdd4a KG	421	}
563fdd4a KG	422
23d72bfd	423	if (cpu_has_feature(CPU_FTR_DBELL)) {
2647aa19 LT	424	/*
	425	* If left NULL, .message_pass defaults to
	426	* smp_muxed_ipi_message_pass
	427	*/
de423ff5	428	smp_85xx_ops.message_pass = NULL;
23d72bfd MM	429	smp_85xx_ops.cause_ipi = doorbell_cause_ipi;
23d72bfd MM	430	}
563fdd4a	431
bf345263 ZC	432	np = of_find_matching_node(NULL, mpc85xx_smp_guts_ids);
	433	if (np) {
	434	guts = of_iomap(np, 0);
	435	of_node_put(np);
	436	if (!guts) {
	437	pr_err("%s: Could not map guts node address\n",
	438	__func__);
	439	return;
	440	}
	441	smp_85xx_ops.give_timebase = mpc85xx_give_timebase;
	442	smp_85xx_ops.take_timebase = mpc85xx_take_timebase;
d0832a75 ZC	443	#ifdef CONFIG_HOTPLUG_CPU
	444	ppc_md.cpu_die = smp_85xx_mach_cpu_die;
	445	#endif
bf345263 ZC	446	}
bf345263 ZC	447
d5b26db2	448	smp_ops = &smp_85xx_ops;
f933a41e MM	449
	450	#ifdef CONFIG_KEXEC
	451	ppc_md.kexec_cpu_down = mpc85xx_smp_kexec_cpu_down;
	452	ppc_md.machine_kexec = mpc85xx_smp_machine_kexec;
	453	#endif
d5b26db2	454	}