Commit | Line | Data |
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b809b3e8 JL |
1 | /* |
2 | * MPC86XX pci setup code | |
3 | * | |
4 | * Recode: ZHANG WEI <wei.zhang@freescale.com> | |
5 | * Initial author: Xianghua Xiao <x.xiao@freescale.com> | |
6 | * | |
7 | * Copyright 2006 Freescale Semiconductor Inc. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License as published by the | |
11 | * Free Software Foundation; either version 2 of the License, or (at your | |
12 | * option) any later version. | |
13 | */ | |
14 | ||
b809b3e8 JL |
15 | #include <linux/types.h> |
16 | #include <linux/module.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/pci.h> | |
19 | #include <linux/serial.h> | |
20 | ||
21 | #include <asm/system.h> | |
22 | #include <asm/atomic.h> | |
23 | #include <asm/io.h> | |
24 | #include <asm/prom.h> | |
25 | #include <asm/immap_86xx.h> | |
26 | #include <asm/pci-bridge.h> | |
27 | #include <sysdev/fsl_soc.h> | |
28 | ||
29 | #include "mpc86xx.h" | |
30 | ||
31 | #undef DEBUG | |
32 | ||
33 | #ifdef DEBUG | |
34 | #define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args) | |
35 | #else | |
36 | #define DBG(fmt, args...) | |
37 | #endif | |
38 | ||
39 | struct pcie_outbound_window_regs { | |
40 | uint pexotar; /* 0x.0 - PCI Express outbound translation address register */ | |
41 | uint pexotear; /* 0x.4 - PCI Express outbound translation extended address register */ | |
42 | uint pexowbar; /* 0x.8 - PCI Express outbound window base address register */ | |
43 | char res1[4]; | |
44 | uint pexowar; /* 0x.10 - PCI Express outbound window attributes register */ | |
45 | char res2[12]; | |
46 | }; | |
47 | ||
48 | struct pcie_inbound_window_regs { | |
49 | uint pexitar; /* 0x.0 - PCI Express inbound translation address register */ | |
50 | char res1[4]; | |
51 | uint pexiwbar; /* 0x.8 - PCI Express inbound window base address register */ | |
52 | uint pexiwbear; /* 0x.c - PCI Express inbound window base extended address register */ | |
53 | uint pexiwar; /* 0x.10 - PCI Express inbound window attributes register */ | |
54 | char res2[12]; | |
55 | }; | |
56 | ||
57 | static void __init setup_pcie_atmu(struct pci_controller *hose, struct resource *rsrc) | |
58 | { | |
59 | volatile struct ccsr_pex *pcie; | |
60 | volatile struct pcie_outbound_window_regs *pcieow; | |
61 | volatile struct pcie_inbound_window_regs *pcieiw; | |
62 | int i = 0; | |
63 | ||
64 | DBG("PCIE memory map start 0x%x, size 0x%x\n", rsrc->start, | |
65 | rsrc->end - rsrc->start + 1); | |
66 | pcie = ioremap(rsrc->start, rsrc->end - rsrc->start + 1); | |
67 | ||
68 | /* Disable all windows (except pexowar0 since its ignored) */ | |
69 | pcie->pexowar1 = 0; | |
70 | pcie->pexowar2 = 0; | |
71 | pcie->pexowar3 = 0; | |
72 | pcie->pexowar4 = 0; | |
73 | pcie->pexiwar1 = 0; | |
74 | pcie->pexiwar2 = 0; | |
75 | pcie->pexiwar3 = 0; | |
76 | ||
77 | pcieow = (struct pcie_outbound_window_regs *)&pcie->pexotar1; | |
78 | pcieiw = (struct pcie_inbound_window_regs *)&pcie->pexitar1; | |
79 | ||
80 | /* Setup outbound MEM window */ | |
81 | for(i = 0; i < 3; i++) | |
82 | if (hose->mem_resources[i].flags & IORESOURCE_MEM){ | |
83 | DBG("PCIE MEM resource start 0x%08x, size 0x%08x.\n", | |
84 | hose->mem_resources[i].start, | |
85 | hose->mem_resources[i].end | |
86 | - hose->mem_resources[i].start + 1); | |
87 | pcieow->pexotar = (hose->mem_resources[i].start) >> 12 | |
88 | & 0x000fffff; | |
89 | pcieow->pexotear = 0; | |
90 | pcieow->pexowbar = (hose->mem_resources[i].start) >> 12 | |
91 | & 0x000fffff; | |
92 | /* Enable, Mem R/W */ | |
93 | pcieow->pexowar = 0x80044000 | | |
94 | (__ilog2(hose->mem_resources[i].end | |
95 | - hose->mem_resources[i].start + 1) | |
96 | - 1); | |
97 | pcieow++; | |
98 | } | |
99 | ||
100 | /* Setup outbound IO window */ | |
101 | if (hose->io_resource.flags & IORESOURCE_IO){ | |
102 | DBG("PCIE IO resource start 0x%08x, size 0x%08x, phy base 0x%08x.\n", | |
103 | hose->io_resource.start, | |
104 | hose->io_resource.end - hose->io_resource.start + 1, | |
105 | hose->io_base_phys); | |
106 | pcieow->pexotar = (hose->io_resource.start) >> 12 & 0x000fffff; | |
107 | pcieow->pexotear = 0; | |
108 | pcieow->pexowbar = (hose->io_base_phys) >> 12 & 0x000fffff; | |
109 | /* Enable, IO R/W */ | |
110 | pcieow->pexowar = 0x80088000 | (__ilog2(hose->io_resource.end | |
111 | - hose->io_resource.start + 1) - 1); | |
112 | } | |
113 | ||
114 | /* Setup 2G inbound Memory Window @ 0 */ | |
115 | pcieiw->pexitar = 0x00000000; | |
116 | pcieiw->pexiwbar = 0x00000000; | |
117 | /* Enable, Prefetch, Local Mem, Snoop R/W, 2G */ | |
118 | pcieiw->pexiwar = 0xa0f5501e; | |
119 | } | |
120 | ||
121 | static void __init | |
122 | mpc86xx_setup_pcie(struct pci_controller *hose, u32 pcie_offset, u32 pcie_size) | |
123 | { | |
b809b3e8 JL |
124 | u16 cmd; |
125 | unsigned int temps; | |
126 | ||
127 | DBG("PCIE host controller register offset 0x%08x, size 0x%08x.\n", | |
128 | pcie_offset, pcie_size); | |
129 | ||
b809b3e8 JL |
130 | early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd); |
131 | cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | |
132 | | PCI_COMMAND_IO; | |
133 | early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd); | |
134 | ||
135 | early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80); | |
136 | ||
137 | /* PCIE Bus, Fix the MPC8641D host bridge's location to bus 0xFF. */ | |
138 | early_read_config_dword(hose, 0, 0, PCI_PRIMARY_BUS, &temps); | |
139 | temps = (temps & 0xff000000) | (0xff) | (0x0 << 8) | (0xfe << 16); | |
140 | early_write_config_dword(hose, 0, 0, PCI_PRIMARY_BUS, temps); | |
141 | } | |
142 | ||
9ad494f6 KG |
143 | int mpc86xx_exclude_device(u_char bus, u_char devfn) |
144 | { | |
145 | if (bus == 0 && PCI_SLOT(devfn) == 0) | |
146 | return PCIBIOS_DEVICE_NOT_FOUND; | |
147 | ||
148 | return PCIBIOS_SUCCESSFUL; | |
149 | } | |
150 | ||
b809b3e8 JL |
151 | int __init add_bridge(struct device_node *dev) |
152 | { | |
153 | int len; | |
154 | struct pci_controller *hose; | |
155 | struct resource rsrc; | |
8efca493 | 156 | const int *bus_range; |
b809b3e8 JL |
157 | int has_address = 0; |
158 | int primary = 0; | |
159 | ||
160 | DBG("Adding PCIE host bridge %s\n", dev->full_name); | |
161 | ||
162 | /* Fetch host bridge registers address */ | |
163 | has_address = (of_address_to_resource(dev, 0, &rsrc) == 0); | |
164 | ||
165 | /* Get bus range if any */ | |
8efca493 | 166 | bus_range = get_property(dev, "bus-range", &len); |
b809b3e8 JL |
167 | if (bus_range == NULL || len < 2 * sizeof(int)) |
168 | printk(KERN_WARNING "Can't get bus-range for %s, assume" | |
169 | " bus 0\n", dev->full_name); | |
170 | ||
171 | hose = pcibios_alloc_controller(); | |
172 | if (!hose) | |
173 | return -ENOMEM; | |
174 | hose->arch_data = dev; | |
175 | hose->set_cfg_type = 1; | |
176 | ||
177 | /* last_busno = 0xfe cause by MPC8641 PCIE bug */ | |
178 | hose->first_busno = bus_range ? bus_range[0] : 0x0; | |
179 | hose->last_busno = bus_range ? bus_range[1] : 0xfe; | |
180 | ||
181 | setup_indirect_pcie(hose, rsrc.start, rsrc.start + 0x4); | |
182 | ||
183 | /* Setup the PCIE host controller. */ | |
184 | mpc86xx_setup_pcie(hose, rsrc.start, rsrc.end - rsrc.start + 1); | |
185 | ||
186 | if ((rsrc.start & 0xfffff) == 0x8000) | |
187 | primary = 1; | |
188 | ||
189 | printk(KERN_INFO "Found MPC86xx PCIE host bridge at 0x%08lx. " | |
190 | "Firmware bus number: %d->%d\n", | |
869d7f38 JL |
191 | (unsigned long) rsrc.start, |
192 | hose->first_busno, hose->last_busno); | |
b809b3e8 JL |
193 | |
194 | DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", | |
195 | hose, hose->cfg_addr, hose->cfg_data); | |
196 | ||
197 | /* Interpret the "ranges" property */ | |
198 | /* This also maps the I/O region and sets isa_io/mem_base */ | |
199 | pci_process_bridge_OF_ranges(hose, dev, primary); | |
200 | ||
201 | /* Setup PEX window registers */ | |
202 | setup_pcie_atmu(hose, &rsrc); | |
203 | ||
204 | return 0; | |
205 | } |