Commit | Line | Data |
---|---|---|
bbd0abda | 1 | /* |
bbd0abda PM |
2 | * Copyright (C) 2005 Sven Luther <sl@bplan-gmbh.de> |
3 | * Thanks to : | |
4 | * Dale Farnsworth <dale@farnsworth.org> | |
5 | * Mark A. Greer <mgreer@mvista.com> | |
6 | * Nicolas DET <nd@bplan-gmbh.de> | |
7 | * Benjamin Herrenschmidt <benh@kernel.crashing.org> | |
8 | * And anyone else who helped me on this. | |
9 | */ | |
10 | ||
11 | #include <linux/types.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/ioport.h> | |
14 | #include <linux/device.h> | |
300230dc | 15 | #include <linux/platform_device.h> |
bbd0abda PM |
16 | #include <linux/mv643xx.h> |
17 | #include <linux/pci.h> | |
18 | ||
dd03d25f ND |
19 | #define PEGASOS2_MARVELL_REGBASE (0xf1000000) |
20 | #define PEGASOS2_MARVELL_REGSIZE (0x00004000) | |
21 | #define PEGASOS2_SRAM_BASE (0xf2000000) | |
22 | #define PEGASOS2_SRAM_SIZE (256*1024) | |
23 | ||
10156cea GP |
24 | #define PEGASOS2_SRAM_BASE_ETH_PORT0 (PEGASOS2_SRAM_BASE) |
25 | #define PEGASOS2_SRAM_BASE_ETH_PORT1 (PEGASOS2_SRAM_BASE_ETH_PORT0 + (PEGASOS2_SRAM_SIZE / 2) ) | |
dd03d25f ND |
26 | |
27 | ||
28 | #define PEGASOS2_SRAM_RXRING_SIZE (PEGASOS2_SRAM_SIZE/4) | |
29 | #define PEGASOS2_SRAM_TXRING_SIZE (PEGASOS2_SRAM_SIZE/4) | |
30 | ||
31 | #undef BE_VERBOSE | |
32 | ||
bbd0abda PM |
33 | static struct resource mv643xx_eth_shared_resources[] = { |
34 | [0] = { | |
35 | .name = "ethernet shared base", | |
36 | .start = 0xf1000000 + MV643XX_ETH_SHARED_REGS, | |
37 | .end = 0xf1000000 + MV643XX_ETH_SHARED_REGS + | |
38 | MV643XX_ETH_SHARED_REGS_SIZE - 1, | |
39 | .flags = IORESOURCE_MEM, | |
40 | }, | |
41 | }; | |
42 | ||
43 | static struct platform_device mv643xx_eth_shared_device = { | |
44 | .name = MV643XX_ETH_SHARED_NAME, | |
45 | .id = 0, | |
46 | .num_resources = ARRAY_SIZE(mv643xx_eth_shared_resources), | |
47 | .resource = mv643xx_eth_shared_resources, | |
48 | }; | |
49 | ||
c3a07134 FF |
50 | /* |
51 | * The orion mdio driver only covers shared + 0x4 up to shared + 0x84 - 1 | |
52 | */ | |
53 | static struct resource mv643xx_eth_mvmdio_resources[] = { | |
54 | [0] = { | |
55 | .name = "ethernet mdio base", | |
56 | .start = 0xf1000000 + MV643XX_ETH_SHARED_REGS + 0x4, | |
57 | .end = 0xf1000000 + MV643XX_ETH_SHARED_REGS + 0x83, | |
58 | .flags = IORESOURCE_MEM, | |
59 | }, | |
60 | }; | |
61 | ||
62 | static struct platform_device mv643xx_eth_mvmdio_device = { | |
63 | .name = "orion-mdio", | |
64 | .id = -1, | |
65 | .num_resources = ARRAY_SIZE(mv643xx_eth_mvmdio_resources), | |
66 | .resource = mv643xx_eth_shared_resources, | |
67 | }; | |
68 | ||
10156cea | 69 | static struct resource mv643xx_eth_port1_resources[] = { |
bbd0abda | 70 | [0] = { |
10156cea | 71 | .name = "eth port1 irq", |
bbd0abda PM |
72 | .start = 9, |
73 | .end = 9, | |
74 | .flags = IORESOURCE_IRQ, | |
75 | }, | |
76 | }; | |
77 | ||
10156cea | 78 | static struct mv643xx_eth_platform_data eth_port1_pd = { |
fa3959f4 | 79 | .shared = &mv643xx_eth_shared_device, |
84dd619e | 80 | .port_number = 1, |
10156cea | 81 | .phy_addr = MV643XX_ETH_PHY_ADDR(7), |
fa3959f4 | 82 | |
10156cea | 83 | .tx_sram_addr = PEGASOS2_SRAM_BASE_ETH_PORT1, |
dd03d25f ND |
84 | .tx_sram_size = PEGASOS2_SRAM_TXRING_SIZE, |
85 | .tx_queue_size = PEGASOS2_SRAM_TXRING_SIZE/16, | |
86 | ||
10156cea | 87 | .rx_sram_addr = PEGASOS2_SRAM_BASE_ETH_PORT1 + PEGASOS2_SRAM_TXRING_SIZE, |
dd03d25f ND |
88 | .rx_sram_size = PEGASOS2_SRAM_RXRING_SIZE, |
89 | .rx_queue_size = PEGASOS2_SRAM_RXRING_SIZE/16, | |
90 | }; | |
bbd0abda | 91 | |
10156cea | 92 | static struct platform_device eth_port1_device = { |
bbd0abda PM |
93 | .name = MV643XX_ETH_NAME, |
94 | .id = 1, | |
10156cea GP |
95 | .num_resources = ARRAY_SIZE(mv643xx_eth_port1_resources), |
96 | .resource = mv643xx_eth_port1_resources, | |
bbd0abda | 97 | .dev = { |
10156cea | 98 | .platform_data = ð_port1_pd, |
bbd0abda PM |
99 | }, |
100 | }; | |
101 | ||
102 | static struct platform_device *mv643xx_eth_pd_devs[] __initdata = { | |
103 | &mv643xx_eth_shared_device, | |
c3a07134 | 104 | &mv643xx_eth_mvmdio_device, |
10156cea | 105 | ð_port1_device, |
bbd0abda PM |
106 | }; |
107 | ||
dd03d25f ND |
108 | /***********/ |
109 | /***********/ | |
110 | #define MV_READ(offset,val) { val = readl(mv643xx_reg_base + offset); } | |
111 | #define MV_WRITE(offset,data) writel(data, mv643xx_reg_base + offset) | |
112 | ||
113 | static void __iomem *mv643xx_reg_base; | |
114 | ||
115 | static int Enable_SRAM(void) | |
116 | { | |
117 | u32 ALong; | |
118 | ||
119 | if (mv643xx_reg_base == NULL) | |
120 | mv643xx_reg_base = ioremap(PEGASOS2_MARVELL_REGBASE, | |
121 | PEGASOS2_MARVELL_REGSIZE); | |
122 | ||
123 | if (mv643xx_reg_base == NULL) | |
124 | return -ENOMEM; | |
125 | ||
126 | #ifdef BE_VERBOSE | |
127 | printk("Pegasos II/Marvell MV64361: register remapped from %p to %p\n", | |
128 | (void *)PEGASOS2_MARVELL_REGBASE, (void *)mv643xx_reg_base); | |
129 | #endif | |
130 | ||
131 | MV_WRITE(MV64340_SRAM_CONFIG, 0); | |
bbd0abda | 132 | |
dd03d25f ND |
133 | MV_WRITE(MV64340_INTEGRATED_SRAM_BASE_ADDR, PEGASOS2_SRAM_BASE >> 16); |
134 | ||
135 | MV_READ(MV64340_BASE_ADDR_ENABLE, ALong); | |
136 | ALong &= ~(1 << 19); | |
137 | MV_WRITE(MV64340_BASE_ADDR_ENABLE, ALong); | |
138 | ||
139 | ALong = 0x02; | |
140 | ALong |= PEGASOS2_SRAM_BASE & 0xffff0000; | |
141 | MV_WRITE(MV643XX_ETH_BAR_4, ALong); | |
142 | ||
143 | MV_WRITE(MV643XX_ETH_SIZE_REG_4, (PEGASOS2_SRAM_SIZE-1) & 0xffff0000); | |
144 | ||
145 | MV_READ(MV643XX_ETH_BASE_ADDR_ENABLE_REG, ALong); | |
146 | ALong &= ~(1 << 4); | |
147 | MV_WRITE(MV643XX_ETH_BASE_ADDR_ENABLE_REG, ALong); | |
148 | ||
149 | #ifdef BE_VERBOSE | |
150 | printk("Pegasos II/Marvell MV64361: register unmapped\n"); | |
151 | printk("Pegasos II/Marvell MV64361: SRAM at %p, size=%x\n", (void*) PEGASOS2_SRAM_BASE, PEGASOS2_SRAM_SIZE); | |
152 | #endif | |
153 | ||
154 | iounmap(mv643xx_reg_base); | |
155 | mv643xx_reg_base = NULL; | |
156 | ||
157 | return 1; | |
158 | } | |
159 | ||
160 | ||
161 | /***********/ | |
162 | /***********/ | |
405861a0 | 163 | static int __init mv643xx_eth_add_pds(void) |
bbd0abda PM |
164 | { |
165 | int ret = 0; | |
166 | static struct pci_device_id pci_marvell_mv64360[] = { | |
167 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_MV64360) }, | |
168 | { } | |
169 | }; | |
170 | ||
dd03d25f ND |
171 | #ifdef BE_VERBOSE |
172 | printk("Pegasos II/Marvell MV64361: init\n"); | |
173 | #endif | |
174 | ||
bbd0abda | 175 | if (pci_dev_present(pci_marvell_mv64360)) { |
dd03d25f ND |
176 | ret = platform_add_devices(mv643xx_eth_pd_devs, |
177 | ARRAY_SIZE(mv643xx_eth_pd_devs)); | |
178 | ||
179 | if ( Enable_SRAM() < 0) | |
180 | { | |
10156cea GP |
181 | eth_port1_pd.tx_sram_addr = 0; |
182 | eth_port1_pd.tx_sram_size = 0; | |
183 | eth_port1_pd.rx_sram_addr = 0; | |
184 | eth_port1_pd.rx_sram_size = 0; | |
dd03d25f ND |
185 | |
186 | #ifdef BE_VERBOSE | |
187 | printk("Pegasos II/Marvell MV64361: Can't enable the " | |
188 | "SRAM\n"); | |
189 | #endif | |
190 | } | |
bbd0abda | 191 | } |
dd03d25f ND |
192 | |
193 | #ifdef BE_VERBOSE | |
194 | printk("Pegasos II/Marvell MV64361: init is over\n"); | |
195 | #endif | |
196 | ||
bbd0abda PM |
197 | return ret; |
198 | } | |
dd03d25f | 199 | |
bbd0abda | 200 | device_initcall(mv643xx_eth_add_pds); |