Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (C) 2001 Allan Trautman, IBM Corporation |
3 | * | |
4 | * iSeries specific routines for PCI. | |
d387899f | 5 | * |
1da177e4 LT |
6 | * Based on code from pci.c and iSeries_pci.c 32bit |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
d387899f | 12 | * |
1da177e4 LT |
13 | * This program is distributed in the hope that it will be useful, |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
d387899f | 17 | * |
1da177e4 LT |
18 | * You should have received a copy of the GNU General Public License |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
22 | #include <linux/kernel.h> | |
d387899f | 23 | #include <linux/list.h> |
1da177e4 LT |
24 | #include <linux/string.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/module.h> | |
27 | #include <linux/ide.h> | |
28 | #include <linux/pci.h> | |
29 | ||
30 | #include <asm/io.h> | |
31 | #include <asm/irq.h> | |
32 | #include <asm/prom.h> | |
33 | #include <asm/machdep.h> | |
34 | #include <asm/pci-bridge.h> | |
1da177e4 | 35 | #include <asm/iommu.h> |
426c1a11 | 36 | #include <asm/abs_addr.h> |
1da177e4 | 37 | |
8021b8a7 | 38 | #include <asm/iseries/hv_call_xm.h> |
bbc8b628 | 39 | #include <asm/iseries/mf.h> |
1da177e4 | 40 | |
d387899f | 41 | #include <asm/ppc-pci.h> |
1da177e4 | 42 | |
b08567cb | 43 | #include "irq.h" |
426c1a11 | 44 | #include "pci.h" |
c6d2ea92 | 45 | #include "call_pci.h" |
b08567cb | 46 | |
1da177e4 LT |
47 | extern unsigned long io_page_mask; |
48 | ||
49 | /* | |
d387899f | 50 | * Forward declares of prototypes. |
1da177e4 | 51 | */ |
252e75a5 | 52 | static struct device_node *find_Device_Node(int bus, int devfn); |
1da177e4 LT |
53 | static void scan_PHB_slots(struct pci_controller *Phb); |
54 | static void scan_EADS_bridge(HvBusNumber Bus, HvSubBusNumber SubBus, int IdSel); | |
55 | static int scan_bridge_slot(HvBusNumber Bus, struct HvCallPci_BridgeInfo *Info); | |
56 | ||
57 | LIST_HEAD(iSeries_Global_Device_List); | |
58 | ||
59 | static int DeviceCount; | |
60 | ||
61 | /* Counters and control flags. */ | |
62 | static long Pci_Io_Read_Count; | |
63 | static long Pci_Io_Write_Count; | |
64 | #if 0 | |
65 | static long Pci_Cfg_Read_Count; | |
66 | static long Pci_Cfg_Write_Count; | |
67 | #endif | |
68 | static long Pci_Error_Count; | |
69 | ||
d387899f | 70 | static int Pci_Retry_Max = 3; /* Only retry 3 times */ |
1da177e4 LT |
71 | static int Pci_Error_Flag = 1; /* Set Retry Error on. */ |
72 | ||
73 | static struct pci_ops iSeries_pci_ops; | |
74 | ||
75 | /* | |
76 | * Table defines | |
77 | * Each Entry size is 4 MB * 1024 Entries = 4GB I/O address space. | |
78 | */ | |
79 | #define IOMM_TABLE_MAX_ENTRIES 1024 | |
80 | #define IOMM_TABLE_ENTRY_SIZE 0x0000000000400000UL | |
81 | #define BASE_IO_MEMORY 0xE000000000000000UL | |
82 | ||
83 | static unsigned long max_io_memory = 0xE000000000000000UL; | |
84 | static long current_iomm_table_entry; | |
85 | ||
86 | /* | |
87 | * Lookup Tables. | |
88 | */ | |
252e75a5 | 89 | static struct device_node **iomm_table; |
1da177e4 LT |
90 | static u8 *iobar_table; |
91 | ||
92 | /* | |
93 | * Static and Global variables | |
94 | */ | |
95 | static char *pci_io_text = "iSeries PCI I/O"; | |
96 | static DEFINE_SPINLOCK(iomm_table_lock); | |
97 | ||
98 | /* | |
99 | * iomm_table_initialize | |
100 | * | |
101 | * Allocates and initalizes the Address Translation Table and Bar | |
102 | * Tables to get them ready for use. Must be called before any | |
103 | * I/O space is handed out to the device BARs. | |
104 | */ | |
105 | static void iomm_table_initialize(void) | |
106 | { | |
107 | spin_lock(&iomm_table_lock); | |
108 | iomm_table = kmalloc(sizeof(*iomm_table) * IOMM_TABLE_MAX_ENTRIES, | |
109 | GFP_KERNEL); | |
110 | iobar_table = kmalloc(sizeof(*iobar_table) * IOMM_TABLE_MAX_ENTRIES, | |
111 | GFP_KERNEL); | |
112 | spin_unlock(&iomm_table_lock); | |
113 | if ((iomm_table == NULL) || (iobar_table == NULL)) | |
114 | panic("PCI: I/O tables allocation failed.\n"); | |
115 | } | |
116 | ||
117 | /* | |
118 | * iomm_table_allocate_entry | |
119 | * | |
120 | * Adds pci_dev entry in address translation table | |
121 | * | |
122 | * - Allocates the number of entries required in table base on BAR | |
123 | * size. | |
124 | * - Allocates starting at BASE_IO_MEMORY and increases. | |
125 | * - The size is round up to be a multiple of entry size. | |
126 | * - CurrentIndex is incremented to keep track of the last entry. | |
127 | * - Builds the resource entry for allocated BARs. | |
128 | */ | |
129 | static void iomm_table_allocate_entry(struct pci_dev *dev, int bar_num) | |
130 | { | |
131 | struct resource *bar_res = &dev->resource[bar_num]; | |
132 | long bar_size = pci_resource_len(dev, bar_num); | |
133 | ||
134 | /* | |
135 | * No space to allocate, quick exit, skip Allocation. | |
136 | */ | |
137 | if (bar_size == 0) | |
138 | return; | |
139 | /* | |
140 | * Set Resource values. | |
141 | */ | |
142 | spin_lock(&iomm_table_lock); | |
143 | bar_res->name = pci_io_text; | |
144 | bar_res->start = | |
145 | IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry; | |
146 | bar_res->start += BASE_IO_MEMORY; | |
147 | bar_res->end = bar_res->start + bar_size - 1; | |
148 | /* | |
149 | * Allocate the number of table entries needed for BAR. | |
150 | */ | |
151 | while (bar_size > 0 ) { | |
152 | iomm_table[current_iomm_table_entry] = dev->sysdata; | |
153 | iobar_table[current_iomm_table_entry] = bar_num; | |
154 | bar_size -= IOMM_TABLE_ENTRY_SIZE; | |
155 | ++current_iomm_table_entry; | |
156 | } | |
157 | max_io_memory = BASE_IO_MEMORY + | |
158 | (IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry); | |
159 | spin_unlock(&iomm_table_lock); | |
160 | } | |
161 | ||
162 | /* | |
163 | * allocate_device_bars | |
164 | * | |
165 | * - Allocates ALL pci_dev BAR's and updates the resources with the | |
166 | * BAR value. BARS with zero length will have the resources | |
167 | * The HvCallPci_getBarParms is used to get the size of the BAR | |
168 | * space. It calls iomm_table_allocate_entry to allocate | |
169 | * each entry. | |
170 | * - Loops through The Bar resources(0 - 5) including the ROM | |
171 | * is resource(6). | |
172 | */ | |
173 | static void allocate_device_bars(struct pci_dev *dev) | |
174 | { | |
175 | struct resource *bar_res; | |
176 | int bar_num; | |
177 | ||
178 | for (bar_num = 0; bar_num <= PCI_ROM_RESOURCE; ++bar_num) { | |
179 | bar_res = &dev->resource[bar_num]; | |
180 | iomm_table_allocate_entry(dev, bar_num); | |
d387899f | 181 | } |
1da177e4 LT |
182 | } |
183 | ||
184 | /* | |
185 | * Log error information to system console. | |
186 | * Filter out the device not there errors. | |
187 | * PCI: EADs Connect Failed 0x18.58.10 Rc: 0x00xx | |
188 | * PCI: Read Vendor Failed 0x18.58.10 Rc: 0x00xx | |
189 | * PCI: Connect Bus Unit Failed 0x18.58.10 Rc: 0x00xx | |
190 | */ | |
191 | static void pci_Log_Error(char *Error_Text, int Bus, int SubBus, | |
192 | int AgentId, int HvRc) | |
193 | { | |
194 | if (HvRc == 0x0302) | |
195 | return; | |
196 | printk(KERN_ERR "PCI: %s Failed: 0x%02X.%02X.%02X Rc: 0x%04X", | |
197 | Error_Text, Bus, SubBus, AgentId, HvRc); | |
198 | } | |
199 | ||
200 | /* | |
201 | * build_device_node(u16 Bus, int SubBus, u8 DevFn) | |
202 | */ | |
252e75a5 | 203 | static struct device_node *build_device_node(HvBusNumber Bus, |
1da177e4 LT |
204 | HvSubBusNumber SubBus, int AgentId, int Function) |
205 | { | |
252e75a5 SR |
206 | struct device_node *node; |
207 | struct pci_dn *pdn; | |
1da177e4 | 208 | |
252e75a5 | 209 | node = kmalloc(sizeof(struct device_node), GFP_KERNEL); |
1da177e4 LT |
210 | if (node == NULL) |
211 | return NULL; | |
252e75a5 SR |
212 | memset(node, 0, sizeof(struct device_node)); |
213 | pdn = kzalloc(sizeof(*pdn), GFP_KERNEL); | |
214 | if (pdn == NULL) { | |
215 | kfree(node); | |
216 | return NULL; | |
217 | } | |
218 | node->data = pdn; | |
f255f0dd | 219 | pdn->node = node; |
76f9f87f | 220 | list_add_tail(&pdn->Device_List, &iSeries_Global_Device_List); |
20f48ccf SR |
221 | pdn->busno = Bus; |
222 | pdn->bussubno = SubBus; | |
252e75a5 | 223 | pdn->devfn = PCI_DEVFN(ISERIES_ENCODE_DEVICE(AgentId), Function); |
1da177e4 LT |
224 | return node; |
225 | } | |
226 | ||
227 | /* | |
228 | * unsigned long __init find_and_init_phbs(void) | |
229 | * | |
230 | * Description: | |
231 | * This function checks for all possible system PCI host bridges that connect | |
232 | * PCI buses. The system hypervisor is queried as to the guest partition | |
233 | * ownership status. A pci_controller is built for any bus which is partially | |
234 | * owned or fully owned by this guest partition. | |
235 | */ | |
236 | unsigned long __init find_and_init_phbs(void) | |
237 | { | |
238 | struct pci_controller *phb; | |
239 | HvBusNumber bus; | |
240 | ||
1da177e4 LT |
241 | /* Check all possible buses. */ |
242 | for (bus = 0; bus < 256; bus++) { | |
243 | int ret = HvCallXm_testBus(bus); | |
244 | if (ret == 0) { | |
245 | printk("bus %d appears to exist\n", bus); | |
246 | ||
247 | phb = (struct pci_controller *)kmalloc(sizeof(struct pci_controller), GFP_KERNEL); | |
248 | if (phb == NULL) | |
249 | return -ENOMEM; | |
3238e9c9 | 250 | pci_setup_pci_controller(phb); |
1da177e4 LT |
251 | |
252 | phb->pci_mem_offset = phb->local_number = bus; | |
253 | phb->first_busno = bus; | |
254 | phb->last_busno = bus; | |
255 | phb->ops = &iSeries_pci_ops; | |
256 | ||
1da177e4 LT |
257 | /* Find and connect the devices. */ |
258 | scan_PHB_slots(phb); | |
259 | } | |
260 | /* | |
261 | * Check for Unexpected Return code, a clue that something | |
262 | * has gone wrong. | |
263 | */ | |
264 | else if (ret != 0x0301) | |
265 | printk(KERN_ERR "Unexpected Return on Probe(0x%04X): 0x%04X", | |
266 | bus, ret); | |
267 | } | |
268 | return 0; | |
269 | } | |
270 | ||
271 | /* | |
272 | * iSeries_pcibios_init | |
d387899f | 273 | * |
1da177e4 LT |
274 | * Chance to initialize and structures or variable before PCI Bus walk. |
275 | */ | |
276 | void iSeries_pcibios_init(void) | |
277 | { | |
1da177e4 LT |
278 | iomm_table_initialize(); |
279 | find_and_init_phbs(); | |
280 | io_page_mask = -1; | |
1da177e4 LT |
281 | } |
282 | ||
283 | /* | |
d387899f | 284 | * iSeries_pci_final_fixup(void) |
1da177e4 LT |
285 | */ |
286 | void __init iSeries_pci_final_fixup(void) | |
287 | { | |
288 | struct pci_dev *pdev = NULL; | |
252e75a5 | 289 | struct device_node *node; |
d387899f | 290 | int DeviceCount = 0; |
1da177e4 | 291 | |
1da177e4 LT |
292 | /* Fix up at the device node and pci_dev relationship */ |
293 | mf_display_src(0xC9000100); | |
294 | ||
295 | printk("pcibios_final_fixup\n"); | |
296 | for_each_pci_dev(pdev) { | |
297 | node = find_Device_Node(pdev->bus->number, pdev->devfn); | |
298 | printk("pci dev %p (%x.%x), node %p\n", pdev, | |
299 | pdev->bus->number, pdev->devfn, node); | |
300 | ||
301 | if (node != NULL) { | |
302 | ++DeviceCount; | |
303 | pdev->sysdata = (void *)node; | |
252e75a5 | 304 | PCI_DN(node)->pcidev = pdev; |
1da177e4 | 305 | allocate_device_bars(pdev); |
061c063e | 306 | iSeries_Device_Information(pdev, DeviceCount); |
1da177e4 LT |
307 | iommu_devnode_init_iSeries(node); |
308 | } else | |
309 | printk("PCI: Device Tree not found for 0x%016lX\n", | |
310 | (unsigned long)pdev); | |
252e75a5 | 311 | pdev->irq = PCI_DN(node)->Irq; |
1da177e4 LT |
312 | } |
313 | iSeries_activate_IRQs(); | |
314 | mf_display_src(0xC9000200); | |
315 | } | |
316 | ||
317 | void pcibios_fixup_bus(struct pci_bus *PciBus) | |
318 | { | |
1da177e4 LT |
319 | } |
320 | ||
321 | void pcibios_fixup_resources(struct pci_dev *pdev) | |
322 | { | |
d387899f | 323 | } |
1da177e4 LT |
324 | |
325 | /* | |
d387899f | 326 | * Loop through each node function to find usable EADs bridges. |
1da177e4 LT |
327 | */ |
328 | static void scan_PHB_slots(struct pci_controller *Phb) | |
329 | { | |
330 | struct HvCallPci_DeviceInfo *DevInfo; | |
d387899f | 331 | HvBusNumber bus = Phb->local_number; /* System Bus */ |
1da177e4 LT |
332 | const HvSubBusNumber SubBus = 0; /* EADs is always 0. */ |
333 | int HvRc = 0; | |
d387899f | 334 | int IdSel; |
1da177e4 LT |
335 | const int MaxAgents = 8; |
336 | ||
337 | DevInfo = (struct HvCallPci_DeviceInfo*) | |
338 | kmalloc(sizeof(struct HvCallPci_DeviceInfo), GFP_KERNEL); | |
339 | if (DevInfo == NULL) | |
340 | return; | |
341 | ||
342 | /* | |
d387899f | 343 | * Probe for EADs Bridges |
1da177e4 LT |
344 | */ |
345 | for (IdSel = 1; IdSel < MaxAgents; ++IdSel) { | |
d387899f | 346 | HvRc = HvCallPci_getDeviceInfo(bus, SubBus, IdSel, |
426c1a11 | 347 | iseries_hv_addr(DevInfo), |
1da177e4 LT |
348 | sizeof(struct HvCallPci_DeviceInfo)); |
349 | if (HvRc == 0) { | |
350 | if (DevInfo->deviceType == HvCallPci_NodeDevice) | |
351 | scan_EADS_bridge(bus, SubBus, IdSel); | |
352 | else | |
353 | printk("PCI: Invalid System Configuration(0x%02X)" | |
354 | " for bus 0x%02x id 0x%02x.\n", | |
355 | DevInfo->deviceType, bus, IdSel); | |
356 | } | |
357 | else | |
358 | pci_Log_Error("getDeviceInfo", bus, SubBus, IdSel, HvRc); | |
359 | } | |
360 | kfree(DevInfo); | |
361 | } | |
362 | ||
363 | static void scan_EADS_bridge(HvBusNumber bus, HvSubBusNumber SubBus, | |
364 | int IdSel) | |
365 | { | |
366 | struct HvCallPci_BridgeInfo *BridgeInfo; | |
367 | HvAgentId AgentId; | |
368 | int Function; | |
369 | int HvRc; | |
370 | ||
371 | BridgeInfo = (struct HvCallPci_BridgeInfo *) | |
372 | kmalloc(sizeof(struct HvCallPci_BridgeInfo), GFP_KERNEL); | |
373 | if (BridgeInfo == NULL) | |
374 | return; | |
375 | ||
376 | /* Note: hvSubBus and irq is always be 0 at this level! */ | |
377 | for (Function = 0; Function < 8; ++Function) { | |
d387899f | 378 | AgentId = ISERIES_PCI_AGENTID(IdSel, Function); |
1da177e4 | 379 | HvRc = HvCallXm_connectBusUnit(bus, SubBus, AgentId, 0); |
d387899f | 380 | if (HvRc == 0) { |
1da177e4 LT |
381 | printk("found device at bus %d idsel %d func %d (AgentId %x)\n", |
382 | bus, IdSel, Function, AgentId); | |
d387899f | 383 | /* Connect EADs: 0x18.00.12 = 0x00 */ |
d387899f | 384 | HvRc = HvCallPci_getBusUnitInfo(bus, SubBus, AgentId, |
426c1a11 | 385 | iseries_hv_addr(BridgeInfo), |
1da177e4 | 386 | sizeof(struct HvCallPci_BridgeInfo)); |
d387899f | 387 | if (HvRc == 0) { |
1da177e4 LT |
388 | printk("bridge info: type %x subbus %x maxAgents %x maxsubbus %x logslot %x\n", |
389 | BridgeInfo->busUnitInfo.deviceType, | |
390 | BridgeInfo->subBusNumber, | |
391 | BridgeInfo->maxAgents, | |
392 | BridgeInfo->maxSubBusNumber, | |
393 | BridgeInfo->logicalSlotNumber); | |
1da177e4 LT |
394 | if (BridgeInfo->busUnitInfo.deviceType == |
395 | HvCallPci_BridgeDevice) { | |
396 | /* Scan_Bridge_Slot...: 0x18.00.12 */ | |
397 | scan_bridge_slot(bus, BridgeInfo); | |
398 | } else | |
399 | printk("PCI: Invalid Bridge Configuration(0x%02X)", | |
400 | BridgeInfo->busUnitInfo.deviceType); | |
401 | } | |
d387899f | 402 | } else if (HvRc != 0x000B) |
1da177e4 LT |
403 | pci_Log_Error("EADs Connect", |
404 | bus, SubBus, AgentId, HvRc); | |
405 | } | |
406 | kfree(BridgeInfo); | |
407 | } | |
408 | ||
409 | /* | |
410 | * This assumes that the node slot is always on the primary bus! | |
411 | */ | |
412 | static int scan_bridge_slot(HvBusNumber Bus, | |
413 | struct HvCallPci_BridgeInfo *BridgeInfo) | |
414 | { | |
252e75a5 | 415 | struct device_node *node; |
1da177e4 LT |
416 | HvSubBusNumber SubBus = BridgeInfo->subBusNumber; |
417 | u16 VendorId = 0; | |
418 | int HvRc = 0; | |
419 | u8 Irq = 0; | |
420 | int IdSel = ISERIES_GET_DEVICE_FROM_SUBBUS(SubBus); | |
421 | int Function = ISERIES_GET_FUNCTION_FROM_SUBBUS(SubBus); | |
422 | HvAgentId EADsIdSel = ISERIES_PCI_AGENTID(IdSel, Function); | |
423 | ||
424 | /* iSeries_allocate_IRQ.: 0x18.00.12(0xA3) */ | |
d387899f | 425 | Irq = iSeries_allocate_IRQ(Bus, 0, EADsIdSel); |
1da177e4 LT |
426 | |
427 | /* | |
d387899f | 428 | * Connect all functions of any device found. |
1da177e4 | 429 | */ |
d387899f SR |
430 | for (IdSel = 1; IdSel <= BridgeInfo->maxAgents; ++IdSel) { |
431 | for (Function = 0; Function < 8; ++Function) { | |
1da177e4 LT |
432 | HvAgentId AgentId = ISERIES_PCI_AGENTID(IdSel, Function); |
433 | HvRc = HvCallXm_connectBusUnit(Bus, SubBus, | |
434 | AgentId, Irq); | |
435 | if (HvRc != 0) { | |
436 | pci_Log_Error("Connect Bus Unit", | |
437 | Bus, SubBus, AgentId, HvRc); | |
438 | continue; | |
439 | } | |
440 | ||
441 | HvRc = HvCallPci_configLoad16(Bus, SubBus, AgentId, | |
442 | PCI_VENDOR_ID, &VendorId); | |
443 | if (HvRc != 0) { | |
444 | pci_Log_Error("Read Vendor", | |
445 | Bus, SubBus, AgentId, HvRc); | |
446 | continue; | |
447 | } | |
448 | printk("read vendor ID: %x\n", VendorId); | |
449 | ||
450 | /* FoundDevice: 0x18.28.10 = 0x12AE */ | |
1da177e4 | 451 | HvRc = HvCallPci_configStore8(Bus, SubBus, AgentId, |
d387899f | 452 | PCI_INTERRUPT_LINE, Irq); |
1da177e4 LT |
453 | if (HvRc != 0) |
454 | pci_Log_Error("PciCfgStore Irq Failed!", | |
455 | Bus, SubBus, AgentId, HvRc); | |
456 | ||
457 | ++DeviceCount; | |
458 | node = build_device_node(Bus, SubBus, EADsIdSel, Function); | |
252e75a5 SR |
459 | PCI_DN(node)->Irq = Irq; |
460 | PCI_DN(node)->LogicalSlot = BridgeInfo->logicalSlotNumber; | |
1da177e4 LT |
461 | |
462 | } /* for (Function = 0; Function < 8; ++Function) */ | |
463 | } /* for (IdSel = 1; IdSel <= MaxAgents; ++IdSel) */ | |
464 | return HvRc; | |
465 | } | |
466 | ||
467 | /* | |
468 | * I/0 Memory copy MUST use mmio commands on iSeries | |
469 | * To do; For performance, include the hv call directly | |
470 | */ | |
471 | void iSeries_memset_io(volatile void __iomem *dest, char c, size_t Count) | |
472 | { | |
473 | u8 ByteValue = c; | |
474 | long NumberOfBytes = Count; | |
475 | ||
476 | while (NumberOfBytes > 0) { | |
477 | iSeries_Write_Byte(ByteValue, dest++); | |
478 | -- NumberOfBytes; | |
479 | } | |
480 | } | |
481 | EXPORT_SYMBOL(iSeries_memset_io); | |
482 | ||
483 | void iSeries_memcpy_toio(volatile void __iomem *dest, void *source, size_t count) | |
484 | { | |
485 | char *src = source; | |
486 | long NumberOfBytes = count; | |
487 | ||
488 | while (NumberOfBytes > 0) { | |
489 | iSeries_Write_Byte(*src++, dest++); | |
490 | -- NumberOfBytes; | |
491 | } | |
492 | } | |
493 | EXPORT_SYMBOL(iSeries_memcpy_toio); | |
494 | ||
495 | void iSeries_memcpy_fromio(void *dest, const volatile void __iomem *src, size_t count) | |
496 | { | |
497 | char *dst = dest; | |
498 | long NumberOfBytes = count; | |
499 | ||
500 | while (NumberOfBytes > 0) { | |
501 | *dst++ = iSeries_Read_Byte(src++); | |
502 | -- NumberOfBytes; | |
503 | } | |
504 | } | |
505 | EXPORT_SYMBOL(iSeries_memcpy_fromio); | |
506 | ||
507 | /* | |
508 | * Look down the chain to find the matching Device Device | |
509 | */ | |
252e75a5 | 510 | static struct device_node *find_Device_Node(int bus, int devfn) |
1da177e4 | 511 | { |
76f9f87f | 512 | struct pci_dn *pdn; |
1da177e4 | 513 | |
76f9f87f | 514 | list_for_each_entry(pdn, &iSeries_Global_Device_List, Device_List) { |
20f48ccf | 515 | if ((bus == pdn->busno) && (devfn == pdn->devfn)) |
76f9f87f | 516 | return pdn->node; |
1da177e4 LT |
517 | } |
518 | return NULL; | |
519 | } | |
520 | ||
521 | #if 0 | |
522 | /* | |
523 | * Returns the device node for the passed pci_dev | |
524 | * Sanity Check Node PciDev to passed pci_dev | |
525 | * If none is found, returns a NULL which the client must handle. | |
526 | */ | |
252e75a5 | 527 | static struct device_node *get_Device_Node(struct pci_dev *pdev) |
1da177e4 | 528 | { |
252e75a5 | 529 | struct device_node *node; |
1da177e4 LT |
530 | |
531 | node = pdev->sysdata; | |
252e75a5 | 532 | if (node == NULL || PCI_DN(node)->pcidev != pdev) |
1da177e4 LT |
533 | node = find_Device_Node(pdev->bus->number, pdev->devfn); |
534 | return node; | |
535 | } | |
536 | #endif | |
537 | ||
538 | /* | |
539 | * Config space read and write functions. | |
540 | * For now at least, we look for the device node for the bus and devfn | |
541 | * that we are asked to access. It may be possible to translate the devfn | |
542 | * to a subbus and deviceid more directly. | |
543 | */ | |
544 | static u64 hv_cfg_read_func[4] = { | |
545 | HvCallPciConfigLoad8, HvCallPciConfigLoad16, | |
546 | HvCallPciConfigLoad32, HvCallPciConfigLoad32 | |
547 | }; | |
548 | ||
549 | static u64 hv_cfg_write_func[4] = { | |
550 | HvCallPciConfigStore8, HvCallPciConfigStore16, | |
551 | HvCallPciConfigStore32, HvCallPciConfigStore32 | |
552 | }; | |
553 | ||
554 | /* | |
555 | * Read PCI config space | |
556 | */ | |
557 | static int iSeries_pci_read_config(struct pci_bus *bus, unsigned int devfn, | |
558 | int offset, int size, u32 *val) | |
559 | { | |
252e75a5 | 560 | struct device_node *node = find_Device_Node(bus->number, devfn); |
1da177e4 LT |
561 | u64 fn; |
562 | struct HvCallPci_LoadReturn ret; | |
563 | ||
564 | if (node == NULL) | |
565 | return PCIBIOS_DEVICE_NOT_FOUND; | |
566 | if (offset > 255) { | |
567 | *val = ~0; | |
568 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
569 | } | |
570 | ||
571 | fn = hv_cfg_read_func[(size - 1) & 3]; | |
20f48ccf | 572 | HvCall3Ret16(fn, &ret, iseries_ds_addr(node), offset, 0); |
1da177e4 LT |
573 | |
574 | if (ret.rc != 0) { | |
575 | *val = ~0; | |
576 | return PCIBIOS_DEVICE_NOT_FOUND; /* or something */ | |
577 | } | |
578 | ||
579 | *val = ret.value; | |
580 | return 0; | |
581 | } | |
582 | ||
583 | /* | |
584 | * Write PCI config space | |
585 | */ | |
586 | ||
587 | static int iSeries_pci_write_config(struct pci_bus *bus, unsigned int devfn, | |
588 | int offset, int size, u32 val) | |
589 | { | |
252e75a5 | 590 | struct device_node *node = find_Device_Node(bus->number, devfn); |
1da177e4 LT |
591 | u64 fn; |
592 | u64 ret; | |
593 | ||
594 | if (node == NULL) | |
595 | return PCIBIOS_DEVICE_NOT_FOUND; | |
596 | if (offset > 255) | |
597 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
598 | ||
599 | fn = hv_cfg_write_func[(size - 1) & 3]; | |
20f48ccf | 600 | ret = HvCall4(fn, iseries_ds_addr(node), offset, val, 0); |
1da177e4 LT |
601 | |
602 | if (ret != 0) | |
603 | return PCIBIOS_DEVICE_NOT_FOUND; | |
604 | ||
605 | return 0; | |
606 | } | |
607 | ||
608 | static struct pci_ops iSeries_pci_ops = { | |
609 | .read = iSeries_pci_read_config, | |
610 | .write = iSeries_pci_write_config | |
611 | }; | |
612 | ||
613 | /* | |
614 | * Check Return Code | |
615 | * -> On Failure, print and log information. | |
616 | * Increment Retry Count, if exceeds max, panic partition. | |
1da177e4 LT |
617 | * |
618 | * PCI: Device 23.90 ReadL I/O Error( 0): 0x1234 | |
619 | * PCI: Device 23.90 ReadL Retry( 1) | |
620 | * PCI: Device 23.90 ReadL Retry Successful(1) | |
621 | */ | |
252e75a5 | 622 | static int CheckReturnCode(char *TextHdr, struct device_node *DevNode, |
a2ebaf25 | 623 | int *retry, u64 ret) |
1da177e4 LT |
624 | { |
625 | if (ret != 0) { | |
252e75a5 SR |
626 | struct pci_dn *pdn = PCI_DN(DevNode); |
627 | ||
1da177e4 | 628 | ++Pci_Error_Count; |
a2ebaf25 | 629 | (*retry)++; |
1da177e4 | 630 | printk("PCI: %s: Device 0x%04X:%02X I/O Error(%2d): 0x%04X\n", |
20f48ccf | 631 | TextHdr, pdn->busno, pdn->devfn, |
a2ebaf25 | 632 | *retry, (int)ret); |
1da177e4 LT |
633 | /* |
634 | * Bump the retry and check for retry count exceeded. | |
635 | * If, Exceeded, panic the system. | |
636 | */ | |
a2ebaf25 | 637 | if (((*retry) > Pci_Retry_Max) && |
1da177e4 LT |
638 | (Pci_Error_Flag > 0)) { |
639 | mf_display_src(0xB6000103); | |
a2ebaf25 | 640 | panic_timeout = 0; |
1da177e4 LT |
641 | panic("PCI: Hardware I/O Error, SRC B6000103, " |
642 | "Automatic Reboot Disabled.\n"); | |
643 | } | |
644 | return -1; /* Retry Try */ | |
645 | } | |
a2ebaf25 | 646 | return 0; |
1da177e4 LT |
647 | } |
648 | ||
649 | /* | |
650 | * Translate the I/O Address into a device node, bar, and bar offset. | |
651 | * Note: Make sure the passed variable end up on the stack to avoid | |
652 | * the exposure of being device global. | |
653 | */ | |
252e75a5 | 654 | static inline struct device_node *xlate_iomm_address( |
1da177e4 LT |
655 | const volatile void __iomem *IoAddress, |
656 | u64 *dsaptr, u64 *BarOffsetPtr) | |
657 | { | |
658 | unsigned long OrigIoAddr; | |
659 | unsigned long BaseIoAddr; | |
660 | unsigned long TableIndex; | |
252e75a5 | 661 | struct device_node *DevNode; |
1da177e4 LT |
662 | |
663 | OrigIoAddr = (unsigned long __force)IoAddress; | |
664 | if ((OrigIoAddr < BASE_IO_MEMORY) || (OrigIoAddr >= max_io_memory)) | |
665 | return NULL; | |
666 | BaseIoAddr = OrigIoAddr - BASE_IO_MEMORY; | |
667 | TableIndex = BaseIoAddr / IOMM_TABLE_ENTRY_SIZE; | |
668 | DevNode = iomm_table[TableIndex]; | |
669 | ||
670 | if (DevNode != NULL) { | |
671 | int barnum = iobar_table[TableIndex]; | |
20f48ccf | 672 | *dsaptr = iseries_ds_addr(DevNode) | (barnum << 24); |
1da177e4 LT |
673 | *BarOffsetPtr = BaseIoAddr % IOMM_TABLE_ENTRY_SIZE; |
674 | } else | |
675 | panic("PCI: Invalid PCI IoAddress detected!\n"); | |
676 | return DevNode; | |
677 | } | |
678 | ||
679 | /* | |
680 | * Read MM I/O Instructions for the iSeries | |
681 | * On MM I/O error, all ones are returned and iSeries_pci_IoError is cal | |
682 | * else, data is returned in big Endian format. | |
683 | * | |
684 | * iSeries_Read_Byte = Read Byte ( 8 bit) | |
685 | * iSeries_Read_Word = Read Word (16 bit) | |
686 | * iSeries_Read_Long = Read Long (32 bit) | |
687 | */ | |
688 | u8 iSeries_Read_Byte(const volatile void __iomem *IoAddress) | |
689 | { | |
690 | u64 BarOffset; | |
691 | u64 dsa; | |
a2ebaf25 | 692 | int retry = 0; |
1da177e4 | 693 | struct HvCallPci_LoadReturn ret; |
252e75a5 | 694 | struct device_node *DevNode = |
1da177e4 LT |
695 | xlate_iomm_address(IoAddress, &dsa, &BarOffset); |
696 | ||
697 | if (DevNode == NULL) { | |
698 | static unsigned long last_jiffies; | |
699 | static int num_printed; | |
700 | ||
701 | if ((jiffies - last_jiffies) > 60 * HZ) { | |
702 | last_jiffies = jiffies; | |
703 | num_printed = 0; | |
704 | } | |
705 | if (num_printed++ < 10) | |
706 | printk(KERN_ERR "iSeries_Read_Byte: invalid access at IO address %p\n", IoAddress); | |
707 | return 0xff; | |
708 | } | |
709 | do { | |
710 | ++Pci_Io_Read_Count; | |
711 | HvCall3Ret16(HvCallPciBarLoad8, &ret, dsa, BarOffset, 0); | |
a2ebaf25 | 712 | } while (CheckReturnCode("RDB", DevNode, &retry, ret.rc) != 0); |
1da177e4 LT |
713 | |
714 | return (u8)ret.value; | |
715 | } | |
716 | EXPORT_SYMBOL(iSeries_Read_Byte); | |
717 | ||
718 | u16 iSeries_Read_Word(const volatile void __iomem *IoAddress) | |
719 | { | |
720 | u64 BarOffset; | |
721 | u64 dsa; | |
a2ebaf25 | 722 | int retry = 0; |
1da177e4 | 723 | struct HvCallPci_LoadReturn ret; |
252e75a5 | 724 | struct device_node *DevNode = |
1da177e4 LT |
725 | xlate_iomm_address(IoAddress, &dsa, &BarOffset); |
726 | ||
727 | if (DevNode == NULL) { | |
728 | static unsigned long last_jiffies; | |
729 | static int num_printed; | |
730 | ||
731 | if ((jiffies - last_jiffies) > 60 * HZ) { | |
732 | last_jiffies = jiffies; | |
733 | num_printed = 0; | |
734 | } | |
735 | if (num_printed++ < 10) | |
736 | printk(KERN_ERR "iSeries_Read_Word: invalid access at IO address %p\n", IoAddress); | |
737 | return 0xffff; | |
738 | } | |
739 | do { | |
740 | ++Pci_Io_Read_Count; | |
741 | HvCall3Ret16(HvCallPciBarLoad16, &ret, dsa, | |
742 | BarOffset, 0); | |
a2ebaf25 | 743 | } while (CheckReturnCode("RDW", DevNode, &retry, ret.rc) != 0); |
1da177e4 LT |
744 | |
745 | return swab16((u16)ret.value); | |
746 | } | |
747 | EXPORT_SYMBOL(iSeries_Read_Word); | |
748 | ||
749 | u32 iSeries_Read_Long(const volatile void __iomem *IoAddress) | |
750 | { | |
751 | u64 BarOffset; | |
752 | u64 dsa; | |
a2ebaf25 | 753 | int retry = 0; |
1da177e4 | 754 | struct HvCallPci_LoadReturn ret; |
252e75a5 | 755 | struct device_node *DevNode = |
1da177e4 LT |
756 | xlate_iomm_address(IoAddress, &dsa, &BarOffset); |
757 | ||
758 | if (DevNode == NULL) { | |
759 | static unsigned long last_jiffies; | |
760 | static int num_printed; | |
761 | ||
762 | if ((jiffies - last_jiffies) > 60 * HZ) { | |
763 | last_jiffies = jiffies; | |
764 | num_printed = 0; | |
765 | } | |
766 | if (num_printed++ < 10) | |
767 | printk(KERN_ERR "iSeries_Read_Long: invalid access at IO address %p\n", IoAddress); | |
768 | return 0xffffffff; | |
769 | } | |
770 | do { | |
771 | ++Pci_Io_Read_Count; | |
772 | HvCall3Ret16(HvCallPciBarLoad32, &ret, dsa, | |
773 | BarOffset, 0); | |
a2ebaf25 | 774 | } while (CheckReturnCode("RDL", DevNode, &retry, ret.rc) != 0); |
1da177e4 LT |
775 | |
776 | return swab32((u32)ret.value); | |
777 | } | |
778 | EXPORT_SYMBOL(iSeries_Read_Long); | |
779 | ||
780 | /* | |
781 | * Write MM I/O Instructions for the iSeries | |
782 | * | |
783 | * iSeries_Write_Byte = Write Byte (8 bit) | |
784 | * iSeries_Write_Word = Write Word(16 bit) | |
785 | * iSeries_Write_Long = Write Long(32 bit) | |
786 | */ | |
787 | void iSeries_Write_Byte(u8 data, volatile void __iomem *IoAddress) | |
788 | { | |
789 | u64 BarOffset; | |
790 | u64 dsa; | |
a2ebaf25 | 791 | int retry = 0; |
1da177e4 | 792 | u64 rc; |
252e75a5 | 793 | struct device_node *DevNode = |
1da177e4 LT |
794 | xlate_iomm_address(IoAddress, &dsa, &BarOffset); |
795 | ||
796 | if (DevNode == NULL) { | |
797 | static unsigned long last_jiffies; | |
798 | static int num_printed; | |
799 | ||
800 | if ((jiffies - last_jiffies) > 60 * HZ) { | |
801 | last_jiffies = jiffies; | |
802 | num_printed = 0; | |
803 | } | |
804 | if (num_printed++ < 10) | |
805 | printk(KERN_ERR "iSeries_Write_Byte: invalid access at IO address %p\n", IoAddress); | |
806 | return; | |
807 | } | |
808 | do { | |
809 | ++Pci_Io_Write_Count; | |
810 | rc = HvCall4(HvCallPciBarStore8, dsa, BarOffset, data, 0); | |
a2ebaf25 | 811 | } while (CheckReturnCode("WWB", DevNode, &retry, rc) != 0); |
1da177e4 LT |
812 | } |
813 | EXPORT_SYMBOL(iSeries_Write_Byte); | |
814 | ||
815 | void iSeries_Write_Word(u16 data, volatile void __iomem *IoAddress) | |
816 | { | |
817 | u64 BarOffset; | |
818 | u64 dsa; | |
a2ebaf25 | 819 | int retry = 0; |
1da177e4 | 820 | u64 rc; |
252e75a5 | 821 | struct device_node *DevNode = |
1da177e4 LT |
822 | xlate_iomm_address(IoAddress, &dsa, &BarOffset); |
823 | ||
824 | if (DevNode == NULL) { | |
825 | static unsigned long last_jiffies; | |
826 | static int num_printed; | |
827 | ||
828 | if ((jiffies - last_jiffies) > 60 * HZ) { | |
829 | last_jiffies = jiffies; | |
830 | num_printed = 0; | |
831 | } | |
832 | if (num_printed++ < 10) | |
833 | printk(KERN_ERR "iSeries_Write_Word: invalid access at IO address %p\n", IoAddress); | |
834 | return; | |
835 | } | |
836 | do { | |
837 | ++Pci_Io_Write_Count; | |
838 | rc = HvCall4(HvCallPciBarStore16, dsa, BarOffset, swab16(data), 0); | |
a2ebaf25 | 839 | } while (CheckReturnCode("WWW", DevNode, &retry, rc) != 0); |
1da177e4 LT |
840 | } |
841 | EXPORT_SYMBOL(iSeries_Write_Word); | |
842 | ||
843 | void iSeries_Write_Long(u32 data, volatile void __iomem *IoAddress) | |
844 | { | |
845 | u64 BarOffset; | |
846 | u64 dsa; | |
a2ebaf25 | 847 | int retry = 0; |
1da177e4 | 848 | u64 rc; |
252e75a5 | 849 | struct device_node *DevNode = |
1da177e4 LT |
850 | xlate_iomm_address(IoAddress, &dsa, &BarOffset); |
851 | ||
852 | if (DevNode == NULL) { | |
853 | static unsigned long last_jiffies; | |
854 | static int num_printed; | |
855 | ||
856 | if ((jiffies - last_jiffies) > 60 * HZ) { | |
857 | last_jiffies = jiffies; | |
858 | num_printed = 0; | |
859 | } | |
860 | if (num_printed++ < 10) | |
861 | printk(KERN_ERR "iSeries_Write_Long: invalid access at IO address %p\n", IoAddress); | |
862 | return; | |
863 | } | |
864 | do { | |
865 | ++Pci_Io_Write_Count; | |
866 | rc = HvCall4(HvCallPciBarStore32, dsa, BarOffset, swab32(data), 0); | |
a2ebaf25 | 867 | } while (CheckReturnCode("WWL", DevNode, &retry, rc) != 0); |
1da177e4 LT |
868 | } |
869 | EXPORT_SYMBOL(iSeries_Write_Long); |