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1 | #include <linux/types.h> |
2 | #include <linux/init.h> | |
3 | #include <linux/delay.h> | |
4 | #include <linux/kernel.h> | |
5 | #include <linux/interrupt.h> | |
6 | #include <linux/spinlock.h> | |
7 | ||
8 | #include <asm/pmac_feature.h> | |
9 | #include <asm/pmac_pfunc.h> | |
10 | ||
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11 | #undef DEBUG |
12 | #ifdef DEBUG | |
5b9ca526 | 13 | #define DBG(fmt...) printk(fmt) |
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14 | #else |
15 | #define DBG(fmt...) | |
16 | #endif | |
5b9ca526 | 17 | |
7d12e780 | 18 | static irqreturn_t macio_gpio_irq(int irq, void *data) |
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19 | { |
20 | pmf_do_irq(data); | |
21 | ||
22 | return IRQ_HANDLED; | |
23 | } | |
24 | ||
25 | static int macio_do_gpio_irq_enable(struct pmf_function *func) | |
26 | { | |
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27 | unsigned int irq = irq_of_parse_and_map(func->node, 0); |
28 | if (irq == NO_IRQ) | |
5b9ca526 | 29 | return -EINVAL; |
0ebfff14 | 30 | return request_irq(irq, macio_gpio_irq, 0, func->node->name, func); |
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31 | } |
32 | ||
33 | static int macio_do_gpio_irq_disable(struct pmf_function *func) | |
34 | { | |
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35 | unsigned int irq = irq_of_parse_and_map(func->node, 0); |
36 | if (irq == NO_IRQ) | |
5b9ca526 | 37 | return -EINVAL; |
0ebfff14 | 38 | free_irq(irq, func); |
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39 | return 0; |
40 | } | |
41 | ||
42 | static int macio_do_gpio_write(PMF_STD_ARGS, u8 value, u8 mask) | |
43 | { | |
44 | u8 __iomem *addr = (u8 __iomem *)func->driver_data; | |
45 | unsigned long flags; | |
46 | u8 tmp; | |
47 | ||
48 | /* Check polarity */ | |
49 | if (args && args->count && !args->u[0].v) | |
50 | value = ~value; | |
51 | ||
52 | /* Toggle the GPIO */ | |
53 | spin_lock_irqsave(&feature_lock, flags); | |
54 | tmp = readb(addr); | |
55 | tmp = (tmp & ~mask) | (value & mask); | |
56 | DBG("Do write 0x%02x to GPIO %s (%p)\n", | |
57 | tmp, func->node->full_name, addr); | |
58 | writeb(tmp, addr); | |
59 | spin_unlock_irqrestore(&feature_lock, flags); | |
60 | ||
61 | return 0; | |
62 | } | |
63 | ||
64 | static int macio_do_gpio_read(PMF_STD_ARGS, u8 mask, int rshift, u8 xor) | |
65 | { | |
66 | u8 __iomem *addr = (u8 __iomem *)func->driver_data; | |
67 | u32 value; | |
68 | ||
69 | /* Check if we have room for reply */ | |
70 | if (args == NULL || args->count == 0 || args->u[0].p == NULL) | |
71 | return -EINVAL; | |
72 | ||
73 | value = readb(addr); | |
74 | *args->u[0].p = ((value & mask) >> rshift) ^ xor; | |
75 | ||
76 | return 0; | |
77 | } | |
78 | ||
79 | static int macio_do_delay(PMF_STD_ARGS, u32 duration) | |
80 | { | |
81 | /* assume we can sleep ! */ | |
82 | msleep((duration + 999) / 1000); | |
83 | return 0; | |
84 | } | |
85 | ||
86 | static struct pmf_handlers macio_gpio_handlers = { | |
87 | .irq_enable = macio_do_gpio_irq_enable, | |
88 | .irq_disable = macio_do_gpio_irq_disable, | |
89 | .write_gpio = macio_do_gpio_write, | |
90 | .read_gpio = macio_do_gpio_read, | |
91 | .delay = macio_do_delay, | |
92 | }; | |
93 | ||
94 | static void macio_gpio_init_one(struct macio_chip *macio) | |
95 | { | |
96 | struct device_node *gparent, *gp; | |
97 | ||
98 | /* | |
99 | * Find the "gpio" parent node | |
100 | */ | |
101 | ||
102 | for (gparent = NULL; | |
103 | (gparent = of_get_next_child(macio->of_node, gparent)) != NULL;) | |
104 | if (strcmp(gparent->name, "gpio") == 0) | |
105 | break; | |
106 | if (gparent == NULL) | |
107 | return; | |
108 | ||
109 | DBG("Installing GPIO functions for macio %s\n", | |
110 | macio->of_node->full_name); | |
111 | ||
112 | /* | |
113 | * Ok, got one, we dont need anything special to track them down, so | |
114 | * we just create them all | |
115 | */ | |
116 | for (gp = NULL; (gp = of_get_next_child(gparent, gp)) != NULL;) { | |
018a3d1d | 117 | const u32 *reg = get_property(gp, "reg", NULL); |
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118 | unsigned long offset; |
119 | if (reg == NULL) | |
120 | continue; | |
121 | offset = *reg; | |
122 | /* Deal with old style device-tree. We can safely hard code the | |
123 | * offset for now too even if it's a bit gross ... | |
124 | */ | |
125 | if (offset < 0x50) | |
126 | offset += 0x50; | |
127 | offset += (unsigned long)macio->base; | |
128 | pmf_register_driver(gp, &macio_gpio_handlers, (void *)offset); | |
129 | } | |
130 | ||
131 | DBG("Calling initial GPIO functions for macio %s\n", | |
132 | macio->of_node->full_name); | |
133 | ||
134 | /* And now we run all the init ones */ | |
135 | for (gp = NULL; (gp = of_get_next_child(gparent, gp)) != NULL;) | |
136 | pmf_do_functions(gp, NULL, 0, PMF_FLAGS_ON_INIT, NULL); | |
137 | ||
138 | /* Note: We do not at this point implement the "at sleep" or "at wake" | |
139 | * functions. I yet to find any for GPIOs anyway | |
140 | */ | |
141 | } | |
142 | ||
143 | static int macio_do_write_reg32(PMF_STD_ARGS, u32 offset, u32 value, u32 mask) | |
144 | { | |
145 | struct macio_chip *macio = func->driver_data; | |
146 | unsigned long flags; | |
147 | ||
148 | spin_lock_irqsave(&feature_lock, flags); | |
149 | MACIO_OUT32(offset, (MACIO_IN32(offset) & ~mask) | (value & mask)); | |
150 | spin_unlock_irqrestore(&feature_lock, flags); | |
151 | return 0; | |
152 | } | |
153 | ||
154 | static int macio_do_read_reg32(PMF_STD_ARGS, u32 offset) | |
155 | { | |
156 | struct macio_chip *macio = func->driver_data; | |
157 | ||
158 | /* Check if we have room for reply */ | |
159 | if (args == NULL || args->count == 0 || args->u[0].p == NULL) | |
160 | return -EINVAL; | |
161 | ||
162 | *args->u[0].p = MACIO_IN32(offset); | |
163 | return 0; | |
164 | } | |
165 | ||
166 | static int macio_do_write_reg8(PMF_STD_ARGS, u32 offset, u8 value, u8 mask) | |
167 | { | |
168 | struct macio_chip *macio = func->driver_data; | |
169 | unsigned long flags; | |
170 | ||
171 | spin_lock_irqsave(&feature_lock, flags); | |
172 | MACIO_OUT8(offset, (MACIO_IN8(offset) & ~mask) | (value & mask)); | |
173 | spin_unlock_irqrestore(&feature_lock, flags); | |
174 | return 0; | |
175 | } | |
176 | ||
177 | static int macio_do_read_reg8(PMF_STD_ARGS, u32 offset) | |
178 | { | |
179 | struct macio_chip *macio = func->driver_data; | |
180 | ||
181 | /* Check if we have room for reply */ | |
182 | if (args == NULL || args->count == 0 || args->u[0].p == NULL) | |
183 | return -EINVAL; | |
184 | ||
185 | *((u8 *)(args->u[0].p)) = MACIO_IN8(offset); | |
186 | return 0; | |
187 | } | |
188 | ||
189 | static int macio_do_read_reg32_msrx(PMF_STD_ARGS, u32 offset, u32 mask, | |
190 | u32 shift, u32 xor) | |
191 | { | |
192 | struct macio_chip *macio = func->driver_data; | |
193 | ||
194 | /* Check if we have room for reply */ | |
195 | if (args == NULL || args->count == 0 || args->u[0].p == NULL) | |
196 | return -EINVAL; | |
197 | ||
198 | *args->u[0].p = ((MACIO_IN32(offset) & mask) >> shift) ^ xor; | |
199 | return 0; | |
200 | } | |
201 | ||
202 | static int macio_do_read_reg8_msrx(PMF_STD_ARGS, u32 offset, u32 mask, | |
203 | u32 shift, u32 xor) | |
204 | { | |
205 | struct macio_chip *macio = func->driver_data; | |
206 | ||
207 | /* Check if we have room for reply */ | |
208 | if (args == NULL || args->count == 0 || args->u[0].p == NULL) | |
209 | return -EINVAL; | |
210 | ||
211 | *((u8 *)(args->u[0].p)) = ((MACIO_IN8(offset) & mask) >> shift) ^ xor; | |
212 | return 0; | |
213 | } | |
214 | ||
215 | static int macio_do_write_reg32_slm(PMF_STD_ARGS, u32 offset, u32 shift, | |
216 | u32 mask) | |
217 | { | |
218 | struct macio_chip *macio = func->driver_data; | |
219 | unsigned long flags; | |
220 | u32 tmp, val; | |
221 | ||
222 | /* Check args */ | |
223 | if (args == NULL || args->count == 0) | |
224 | return -EINVAL; | |
225 | ||
226 | spin_lock_irqsave(&feature_lock, flags); | |
227 | tmp = MACIO_IN32(offset); | |
228 | val = args->u[0].v << shift; | |
229 | tmp = (tmp & ~mask) | (val & mask); | |
230 | MACIO_OUT32(offset, tmp); | |
231 | spin_unlock_irqrestore(&feature_lock, flags); | |
232 | return 0; | |
233 | } | |
234 | ||
235 | static int macio_do_write_reg8_slm(PMF_STD_ARGS, u32 offset, u32 shift, | |
236 | u32 mask) | |
237 | { | |
238 | struct macio_chip *macio = func->driver_data; | |
239 | unsigned long flags; | |
240 | u32 tmp, val; | |
241 | ||
242 | /* Check args */ | |
243 | if (args == NULL || args->count == 0) | |
244 | return -EINVAL; | |
245 | ||
246 | spin_lock_irqsave(&feature_lock, flags); | |
247 | tmp = MACIO_IN8(offset); | |
248 | val = args->u[0].v << shift; | |
249 | tmp = (tmp & ~mask) | (val & mask); | |
250 | MACIO_OUT8(offset, tmp); | |
251 | spin_unlock_irqrestore(&feature_lock, flags); | |
252 | return 0; | |
253 | } | |
254 | ||
255 | static struct pmf_handlers macio_mmio_handlers = { | |
256 | .write_reg32 = macio_do_write_reg32, | |
257 | .read_reg32 = macio_do_read_reg32, | |
258 | .write_reg8 = macio_do_write_reg8, | |
8f277949 | 259 | .read_reg8 = macio_do_read_reg8, |
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260 | .read_reg32_msrx = macio_do_read_reg32_msrx, |
261 | .read_reg8_msrx = macio_do_read_reg8_msrx, | |
262 | .write_reg32_slm = macio_do_write_reg32_slm, | |
263 | .write_reg8_slm = macio_do_write_reg8_slm, | |
264 | .delay = macio_do_delay, | |
265 | }; | |
266 | ||
267 | static void macio_mmio_init_one(struct macio_chip *macio) | |
268 | { | |
269 | DBG("Installing MMIO functions for macio %s\n", | |
270 | macio->of_node->full_name); | |
271 | ||
272 | pmf_register_driver(macio->of_node, &macio_mmio_handlers, macio); | |
273 | } | |
274 | ||
275 | static struct device_node *unin_hwclock; | |
276 | ||
277 | static int unin_do_write_reg32(PMF_STD_ARGS, u32 offset, u32 value, u32 mask) | |
278 | { | |
279 | unsigned long flags; | |
280 | ||
281 | spin_lock_irqsave(&feature_lock, flags); | |
282 | /* This is fairly bogus in darwin, but it should work for our needs | |
283 | * implemeted that way: | |
284 | */ | |
285 | UN_OUT(offset, (UN_IN(offset) & ~mask) | (value & mask)); | |
286 | spin_unlock_irqrestore(&feature_lock, flags); | |
287 | return 0; | |
288 | } | |
289 | ||
290 | ||
291 | static struct pmf_handlers unin_mmio_handlers = { | |
292 | .write_reg32 = unin_do_write_reg32, | |
293 | .delay = macio_do_delay, | |
294 | }; | |
295 | ||
296 | static void uninorth_install_pfunc(void) | |
297 | { | |
298 | struct device_node *np; | |
299 | ||
300 | DBG("Installing functions for UniN %s\n", | |
301 | uninorth_node->full_name); | |
302 | ||
303 | /* | |
304 | * Install handlers for the bridge itself | |
305 | */ | |
306 | pmf_register_driver(uninorth_node, &unin_mmio_handlers, NULL); | |
307 | pmf_do_functions(uninorth_node, NULL, 0, PMF_FLAGS_ON_INIT, NULL); | |
308 | ||
309 | ||
310 | /* | |
311 | * Install handlers for the hwclock child if any | |
312 | */ | |
313 | for (np = NULL; (np = of_get_next_child(uninorth_node, np)) != NULL;) | |
314 | if (strcmp(np->name, "hw-clock") == 0) { | |
315 | unin_hwclock = np; | |
316 | break; | |
317 | } | |
318 | if (unin_hwclock) { | |
319 | DBG("Installing functions for UniN clock %s\n", | |
320 | unin_hwclock->full_name); | |
321 | pmf_register_driver(unin_hwclock, &unin_mmio_handlers, NULL); | |
322 | pmf_do_functions(unin_hwclock, NULL, 0, PMF_FLAGS_ON_INIT, | |
323 | NULL); | |
324 | } | |
325 | } | |
326 | ||
327 | /* We export this as the SMP code might init us early */ | |
328 | int __init pmac_pfunc_base_install(void) | |
329 | { | |
330 | static int pfbase_inited; | |
331 | int i; | |
332 | ||
333 | if (pfbase_inited) | |
334 | return 0; | |
335 | pfbase_inited = 1; | |
336 | ||
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337 | if (!machine_is(powermac)) |
338 | return 0; | |
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339 | |
340 | DBG("Installing base platform functions...\n"); | |
341 | ||
342 | /* | |
343 | * Locate mac-io chips and install handlers | |
344 | */ | |
345 | for (i = 0 ; i < MAX_MACIO_CHIPS; i++) { | |
346 | if (macio_chips[i].of_node) { | |
347 | macio_mmio_init_one(&macio_chips[i]); | |
348 | macio_gpio_init_one(&macio_chips[i]); | |
349 | } | |
350 | } | |
351 | ||
352 | /* | |
353 | * Install handlers for northbridge and direct mapped hwclock | |
354 | * if any. We do not implement the config space access callback | |
355 | * which is only ever used for functions that we do not call in | |
356 | * the current driver (enabling/disabling cells in U2, mostly used | |
357 | * to restore the PCI settings, we do that differently) | |
358 | */ | |
359 | if (uninorth_node && uninorth_base) | |
360 | uninorth_install_pfunc(); | |
361 | ||
362 | DBG("All base functions installed\n"); | |
363 | ||
364 | return 0; | |
365 | } | |
366 | ||
367 | arch_initcall(pmac_pfunc_base_install); | |
368 | ||
369 | #ifdef CONFIG_PM | |
370 | ||
371 | /* Those can be called by pmac_feature. Ultimately, I should use a sysdev | |
372 | * or a device, but for now, that's good enough until I sort out some | |
373 | * ordering issues. Also, we do not bother with GPIOs, as so far I yet have | |
374 | * to see a case where a GPIO function has the on-suspend or on-resume bit | |
375 | */ | |
376 | void pmac_pfunc_base_suspend(void) | |
377 | { | |
378 | int i; | |
379 | ||
380 | for (i = 0 ; i < MAX_MACIO_CHIPS; i++) { | |
381 | if (macio_chips[i].of_node) | |
382 | pmf_do_functions(macio_chips[i].of_node, NULL, 0, | |
383 | PMF_FLAGS_ON_SLEEP, NULL); | |
384 | } | |
385 | if (uninorth_node) | |
386 | pmf_do_functions(uninorth_node, NULL, 0, | |
387 | PMF_FLAGS_ON_SLEEP, NULL); | |
388 | if (unin_hwclock) | |
389 | pmf_do_functions(unin_hwclock, NULL, 0, | |
390 | PMF_FLAGS_ON_SLEEP, NULL); | |
391 | } | |
392 | ||
393 | void pmac_pfunc_base_resume(void) | |
394 | { | |
395 | int i; | |
396 | ||
397 | if (unin_hwclock) | |
398 | pmf_do_functions(unin_hwclock, NULL, 0, | |
399 | PMF_FLAGS_ON_WAKE, NULL); | |
400 | if (uninorth_node) | |
401 | pmf_do_functions(uninorth_node, NULL, 0, | |
402 | PMF_FLAGS_ON_WAKE, NULL); | |
403 | for (i = 0 ; i < MAX_MACIO_CHIPS; i++) { | |
404 | if (macio_chips[i].of_node) | |
405 | pmf_do_functions(macio_chips[i].of_node, NULL, 0, | |
406 | PMF_FLAGS_ON_WAKE, NULL); | |
407 | } | |
408 | } | |
409 | ||
410 | #endif /* CONFIG_PM */ |