[deliverable/linux.git] / arch / powerpc / platforms / powernv / pci.h

#ifndef __POWERNV_PCI_H
#define __POWERNV_PCI_H

struct pci_dn;

enum pnv_phb_type {
	PNV_PHB_IODA1	= 0,
	PNV_PHB_IODA2	= 1,
	PNV_PHB_NPU	= 2,
};

/* Precise PHB model for error management */
enum pnv_phb_model {
	PNV_PHB_MODEL_UNKNOWN,
	PNV_PHB_MODEL_P7IOC,
	PNV_PHB_MODEL_PHB3,
	PNV_PHB_MODEL_NPU,
};

#define PNV_PCI_DIAG_BUF_SIZE	8192
#define PNV_IODA_PE_DEV		(1 << 0)	/* PE has single PCI device	*/
#define PNV_IODA_PE_BUS		(1 << 1)	/* PE has primary PCI bus	*/
#define PNV_IODA_PE_BUS_ALL	(1 << 2)	/* PE has subordinate buses	*/
#define PNV_IODA_PE_MASTER	(1 << 3)	/* Master PE in compound case	*/
#define PNV_IODA_PE_SLAVE	(1 << 4)	/* Slave PE in compound case	*/
#define PNV_IODA_PE_VF		(1 << 5)	/* PE for one VF 		*/
#define PNV_IODA_PE_PEER	(1 << 6)	/* PE has peers			*/

/* Data associated with a PE, including IOMMU tracking etc.. */
struct pnv_phb;
struct pnv_ioda_pe {
	unsigned long		flags;
	struct pnv_phb		*phb;

#define PNV_IODA_MAX_PEER_PES	8
	struct pnv_ioda_pe	*peers[PNV_IODA_MAX_PEER_PES];

	/* A PE can be associated with a single device or an
	 * entire bus (& children). In the former case, pdev
	 * is populated, in the later case, pbus is.
	 */
#ifdef CONFIG_PCI_IOV
	struct pci_dev          *parent_dev;
#endif
	struct pci_dev		*pdev;
	struct pci_bus		*pbus;

	/* Effective RID (device RID for a device PE and base bus
	 * RID with devfn 0 for a bus PE)
	 */
	unsigned int		rid;

	/* PE number */
	unsigned int		pe_number;

	/* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
	struct iommu_table_group table_group;

	/* 64-bit TCE bypass region */
	bool			tce_bypass_enabled;
	uint64_t		tce_bypass_base;

	/* MSIs. MVE index is identical for for 32 and 64 bit MSI
	 * and -1 if not supported. (It's actually identical to the
	 * PE number)
	 */
	int			mve_number;

	/* PEs in compound case */
	struct pnv_ioda_pe	*master;
	struct list_head	slaves;

	/* Link in list of PE#s */
	struct list_head	list;
};

#define PNV_PHB_FLAG_EEH	(1 << 0)

struct pnv_phb {
	struct pci_controller	*hose;
	enum pnv_phb_type	type;
	enum pnv_phb_model	model;
	u64			hub_id;
	u64			opal_id;
	int			flags;
	void __iomem		*regs;
	int			initialized;
	spinlock_t		lock;

#ifdef CONFIG_DEBUG_FS
	int			has_dbgfs;
	struct dentry		*dbgfs;
#endif

#ifdef CONFIG_PCI_MSI
	unsigned int		msi_base;
	unsigned int		msi32_support;
	struct msi_bitmap	msi_bmp;
#endif
	int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev,
			 unsigned int hwirq, unsigned int virq,
			 unsigned int is_64, struct msi_msg *msg);
	void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev);
	void (*fixup_phb)(struct pci_controller *hose);
	int (*init_m64)(struct pnv_phb *phb);
	void (*reserve_m64_pe)(struct pci_bus *bus,
			       unsigned long *pe_bitmap, bool all);
	unsigned int (*pick_m64_pe)(struct pci_bus *bus, bool all);
	int (*get_pe_state)(struct pnv_phb *phb, int pe_no);
	void (*freeze_pe)(struct pnv_phb *phb, int pe_no);
	int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt);

	struct {
		/* Global bridge info */
		unsigned int		total_pe_num;
		unsigned int		reserved_pe_idx;

		/* 32-bit MMIO window */
		unsigned int		m32_size;
		unsigned int		m32_segsize;
		unsigned int		m32_pci_base;

		/* 64-bit MMIO window */
		unsigned int		m64_bar_idx;
		unsigned long		m64_size;
		unsigned long		m64_segsize;
		unsigned long		m64_base;
		unsigned long		m64_bar_alloc;

		/* IO ports */
		unsigned int		io_size;
		unsigned int		io_segsize;
		unsigned int		io_pci_base;

		/* PE allocation */
		struct mutex		pe_alloc_mutex;
		unsigned long		*pe_alloc;
		struct pnv_ioda_pe	*pe_array;

		/* M32 & IO segment maps */
		unsigned int		*m64_segmap;
		unsigned int		*m32_segmap;
		unsigned int		*io_segmap;

		/* DMA32 segment maps - IODA1 only */
		unsigned int		dma32_count;
		unsigned int		*dma32_segmap;

		/* IRQ chip */
		int			irq_chip_init;
		struct irq_chip		irq_chip;

		/* Sorted list of used PE's based
		 * on the sequence of creation
		 */
		struct list_head	pe_list;
		struct mutex            pe_list_mutex;

		/* Reverse map of PEs, will have to extend if
		 * we are to support more than 256 PEs, indexed
		 * bus { bus, devfn }
		 */
		unsigned char		pe_rmap[0x10000];

		/* TCE cache invalidate registers (physical and
		 * remapped)
		 */
		phys_addr_t		tce_inval_reg_phys;
		__be64 __iomem		*tce_inval_reg;
	} ioda;

	/* PHB and hub status structure */
	union {
		unsigned char			blob[PNV_PCI_DIAG_BUF_SIZE];
		struct OpalIoP7IOCPhbErrorData	p7ioc;
		struct OpalIoPhb3ErrorData	phb3;
		struct OpalIoP7IOCErrorData 	hub_diag;
	} diag;

};

extern struct pci_ops pnv_pci_ops;
extern int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
		unsigned long uaddr, enum dma_data_direction direction,
		struct dma_attrs *attrs);
extern void pnv_tce_free(struct iommu_table *tbl, long index, long npages);
extern int pnv_tce_xchg(struct iommu_table *tbl, long index,
		unsigned long *hpa, enum dma_data_direction *direction);
extern unsigned long pnv_tce_get(struct iommu_table *tbl, long index);

void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
				unsigned char *log_buff);
int pnv_pci_cfg_read(struct pci_dn *pdn,
		     int where, int size, u32 *val);
int pnv_pci_cfg_write(struct pci_dn *pdn,
		      int where, int size, u32 val);
extern struct iommu_table *pnv_pci_table_alloc(int nid);

extern long pnv_pci_link_table_and_group(int node, int num,
		struct iommu_table *tbl,
		struct iommu_table_group *table_group);
extern void pnv_pci_unlink_table_and_group(struct iommu_table *tbl,
		struct iommu_table_group *table_group);
extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
				      void *tce_mem, u64 tce_size,
				      u64 dma_offset, unsigned page_shift);
extern void pnv_pci_init_ioda_hub(struct device_node *np);
extern void pnv_pci_init_ioda2_phb(struct device_node *np);
extern void pnv_pci_init_npu_phb(struct device_node *np);
extern void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl,
					__be64 *startp, __be64 *endp, bool rm);
extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev);
extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option);

extern void pnv_pci_dma_dev_setup(struct pci_dev *pdev);
extern void pnv_pci_dma_bus_setup(struct pci_bus *bus);
extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
extern void pnv_teardown_msi_irqs(struct pci_dev *pdev);

/* Nvlink functions */
extern void pnv_npu_tce_invalidate_entire(struct pnv_ioda_pe *npe);
extern void pnv_npu_tce_invalidate(struct pnv_ioda_pe *npe,
				       struct iommu_table *tbl,
				       unsigned long index,
				       unsigned long npages,
				       bool rm);
extern void pnv_npu_init_dma_pe(struct pnv_ioda_pe *npe);
extern void pnv_npu_setup_dma_pe(struct pnv_ioda_pe *npe);
extern int pnv_npu_dma_set_bypass(struct pnv_ioda_pe *npe, bool enabled);
extern int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask);

#endif /* __POWERNV_PCI_H */
Commit	Line	Data
61305a96 BH	1	#ifndef __POWERNV_PCI_H
	2	#define __POWERNV_PCI_H
	3
	4	struct pci_dn;
	5
	6	enum pnv_phb_type {
2de50e96 RC	7	PNV_PHB_IODA1 = 0,
	8	PNV_PHB_IODA2 = 1,
	9	PNV_PHB_NPU = 2,
61305a96 BH	10	};
61305a96 BH	11
cee72d5b BH	12	/* Precise PHB model for error management */
	13	enum pnv_phb_model {
	14	PNV_PHB_MODEL_UNKNOWN,
cee72d5b	15	PNV_PHB_MODEL_P7IOC,
aa0c033f	16	PNV_PHB_MODEL_PHB3,
5d2aa710	17	PNV_PHB_MODEL_NPU,
cee72d5b BH	18	};
cee72d5b BH	19
5c9d6d75	20	#define PNV_PCI_DIAG_BUF_SIZE 8192
7ebdf956 GS	21	#define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */
	22	#define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */
	23	#define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */
262af557 GC	24	#define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */
262af557 GC	25	#define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */
781a868f	26	#define PNV_IODA_PE_VF (1 << 5) /* PE for one VF */
5d2aa710	27	#define PNV_IODA_PE_PEER (1 << 6) /* PE has peers */
cee72d5b	28
184cd4a3	29	/* Data associated with a PE, including IOMMU tracking etc.. */
4cce9550	30	struct pnv_phb;
184cd4a3	31	struct pnv_ioda_pe {
7ebdf956	32	unsigned long flags;
4cce9550	33	struct pnv_phb *phb;
7ebdf956	34
5d2aa710 AP	35	#define PNV_IODA_MAX_PEER_PES 8
	36	struct pnv_ioda_pe *peers[PNV_IODA_MAX_PEER_PES];
	37
184cd4a3 BH	38	/* A PE can be associated with a single device or an
	39	* entire bus (& children). In the former case, pdev
	40	* is populated, in the later case, pbus is.
	41	*/
781a868f WY	42	#ifdef CONFIG_PCI_IOV
	43	struct pci_dev *parent_dev;
	44	#endif
184cd4a3 BH	45	struct pci_dev *pdev;
	46	struct pci_bus *pbus;
	47
	48	/* Effective RID (device RID for a device PE and base bus
	49	* RID with devfn 0 for a bus PE)
	50	*/
	51	unsigned int rid;
	52
	53	/* PE number */
	54	unsigned int pe_number;
	55
184cd4a3	56	/* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
b348aa65	57	struct iommu_table_group table_group;
184cd4a3	58
cd15b048 BH	59	/* 64-bit TCE bypass region */
	60	bool tce_bypass_enabled;
	61	uint64_t tce_bypass_base;
184cd4a3 BH	62
	63	/* MSIs. MVE index is identical for for 32 and 64 bit MSI
	64	* and -1 if not supported. (It's actually identical to the
	65	* PE number)
	66	*/
	67	int mve_number;
	68
262af557 GC	69	/* PEs in compound case */
	70	struct pnv_ioda_pe *master;
	71	struct list_head slaves;
	72
184cd4a3	73	/* Link in list of PE#s */
7ebdf956	74	struct list_head list;
184cd4a3 BH	75	};
184cd4a3 BH	76
f5bc6b70 GS	77	#define PNV_PHB_FLAG_EEH (1 << 0)
f5bc6b70 GS	78
61305a96 BH	79	struct pnv_phb {
	80	struct pci_controller *hose;
	81	enum pnv_phb_type type;
cee72d5b	82	enum pnv_phb_model model;
8747f363	83	u64 hub_id;
61305a96	84	u64 opal_id;
f5bc6b70	85	int flags;
61305a96	86	void __iomem *regs;
db1266c8	87	int initialized;
61305a96 BH	88	spinlock_t lock;
61305a96 BH	89
37c367f2	90	#ifdef CONFIG_DEBUG_FS
7f52a526	91	int has_dbgfs;
37c367f2 GS	92	struct dentry *dbgfs;
	93	#endif
	94
c1a2562a	95	#ifdef CONFIG_PCI_MSI
c1a2562a	96	unsigned int msi_base;
c1a2562a	97	unsigned int msi32_support;
fb1b55d6	98	struct msi_bitmap msi_bmp;
c1a2562a BH	99	#endif
c1a2562a BH	100	int (msi_setup)(struct pnv_phb phb, struct pci_dev *dev,
137436c9 GS	101	unsigned int hwirq, unsigned int virq,
137436c9 GS	102	unsigned int is_64, struct msi_msg *msg);
61305a96 BH	103	void (dma_dev_setup)(struct pnv_phb phb, struct pci_dev *pdev);
61305a96 BH	104	void (fixup_phb)(struct pci_controller hose);
262af557	105	int (init_m64)(struct pnv_phb phb);
96a2f92b GS	106	void (reserve_m64_pe)(struct pci_bus bus,
96a2f92b GS	107	unsigned long *pe_bitmap, bool all);
689ee8c9	108	unsigned int (pick_m64_pe)(struct pci_bus bus, bool all);
49dec922 GS	109	int (get_pe_state)(struct pnv_phb phb, int pe_no);
	110	void (freeze_pe)(struct pnv_phb phb, int pe_no);
	111	int (unfreeze_pe)(struct pnv_phb phb, int pe_no, int opt);
61305a96	112
2de50e96 RC	113	struct {
2de50e96 RC	114	/* Global bridge info */
92b8f137 GS	115	unsigned int total_pe_num;
92b8f137 GS	116	unsigned int reserved_pe_idx;
2de50e96 RC	117
	118	/* 32-bit MMIO window */
	119	unsigned int m32_size;
	120	unsigned int m32_segsize;
	121	unsigned int m32_pci_base;
	122
	123	/* 64-bit MMIO window */
	124	unsigned int m64_bar_idx;
	125	unsigned long m64_size;
	126	unsigned long m64_segsize;
	127	unsigned long m64_base;
	128	unsigned long m64_bar_alloc;
	129
	130	/* IO ports */
	131	unsigned int io_size;
	132	unsigned int io_segsize;
	133	unsigned int io_pci_base;
	134
13ce7598	135	/* PE allocation */
2de50e96	136	struct mutex pe_alloc_mutex;
13ce7598 GS	137	unsigned long *pe_alloc;
13ce7598 GS	138	struct pnv_ioda_pe *pe_array;
2de50e96 RC	139
2de50e96 RC	140	/* M32 & IO segment maps */
93289d8c	141	unsigned int *m64_segmap;
2de50e96 RC	142	unsigned int *m32_segmap;
2de50e96 RC	143	unsigned int *io_segmap;
2de50e96	144
2b923ed1 GS	145	/* DMA32 segment maps - IODA1 only */
	146	unsigned int dma32_count;
	147	unsigned int *dma32_segmap;
	148
2de50e96 RC	149	/* IRQ chip */
	150	int irq_chip_init;
	151	struct irq_chip irq_chip;
	152
	153	/* Sorted list of used PE's based
	154	* on the sequence of creation
	155	*/
	156	struct list_head pe_list;
	157	struct mutex pe_list_mutex;
	158
	159	/* Reverse map of PEs, will have to extend if
	160	* we are to support more than 256 PEs, indexed
	161	* bus { bus, devfn }
	162	*/
	163	unsigned char pe_rmap[0x10000];
	164
2de50e96 RC	165	/* TCE cache invalidate registers (physical and
	166	* remapped)
	167	*/
	168	phys_addr_t tce_inval_reg_phys;
	169	__be64 __iomem *tce_inval_reg;
	170	} ioda;
cee72d5b	171
ca1de5de	172	/* PHB and hub status structure */
cee72d5b BH	173	union {
	174	unsigned char blob[PNV_PCI_DIAG_BUF_SIZE];
	175	struct OpalIoP7IOCPhbErrorData p7ioc;
93aef2a7	176	struct OpalIoPhb3ErrorData phb3;
ca1de5de	177	struct OpalIoP7IOCErrorData hub_diag;
cee72d5b	178	} diag;
ca1de5de	179
61305a96 BH	180	};
	181
	182	extern struct pci_ops pnv_pci_ops;
da004c36 AK	183	extern int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
	184	unsigned long uaddr, enum dma_data_direction direction,
	185	struct dma_attrs *attrs);
	186	extern void pnv_tce_free(struct iommu_table *tbl, long index, long npages);
05c6cfb9 AK	187	extern int pnv_tce_xchg(struct iommu_table *tbl, long index,
05c6cfb9 AK	188	unsigned long hpa, enum dma_data_direction direction);
da004c36	189	extern unsigned long pnv_tce_get(struct iommu_table *tbl, long index);
61305a96	190
93aef2a7 GS	191	void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
93aef2a7 GS	192	unsigned char *log_buff);
3532a741	193	int pnv_pci_cfg_read(struct pci_dn *pdn,
9bf41be6	194	int where, int size, u32 *val);
3532a741	195	int pnv_pci_cfg_write(struct pci_dn *pdn,
9bf41be6	196	int where, int size, u32 val);
0eaf4def AK	197	extern struct iommu_table *pnv_pci_table_alloc(int nid);
	198
	199	extern long pnv_pci_link_table_and_group(int node, int num,
	200	struct iommu_table *tbl,
	201	struct iommu_table_group *table_group);
	202	extern void pnv_pci_unlink_table_and_group(struct iommu_table *tbl,
	203	struct iommu_table_group *table_group);
61305a96 BH	204	extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
61305a96 BH	205	void *tce_mem, u64 tce_size,
8fa5d454	206	u64 dma_offset, unsigned page_shift);
184cd4a3	207	extern void pnv_pci_init_ioda_hub(struct device_node *np);
aa0c033f	208	extern void pnv_pci_init_ioda2_phb(struct device_node *np);
5d2aa710	209	extern void pnv_pci_init_npu_phb(struct device_node *np);
4cce9550	210	extern void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl,
3ad26e5c	211	__be64 startp, __be64 endp, bool rm);
d92a208d	212	extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev);
cadf364d	213	extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option);
73ed148a	214
92ae0353	215	extern void pnv_pci_dma_dev_setup(struct pci_dev *pdev);
1bc74f1c	216	extern void pnv_pci_dma_bus_setup(struct pci_bus *bus);
92ae0353 DA	217	extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
	218	extern void pnv_teardown_msi_irqs(struct pci_dev *pdev);
	219
5d2aa710 AP	220	/* Nvlink functions */
	221	extern void pnv_npu_tce_invalidate_entire(struct pnv_ioda_pe *npe);
	222	extern void pnv_npu_tce_invalidate(struct pnv_ioda_pe *npe,
	223	struct iommu_table *tbl,
	224	unsigned long index,
	225	unsigned long npages,
	226	bool rm);
	227	extern void pnv_npu_init_dma_pe(struct pnv_ioda_pe *npe);
	228	extern void pnv_npu_setup_dma_pe(struct pnv_ioda_pe *npe);
	229	extern int pnv_npu_dma_set_bypass(struct pnv_ioda_pe *npe, bool enabled);
	230	extern int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask);
	231
61305a96	232	#endif /* __POWERNV_PCI_H */