[deliverable/linux.git] / arch / powerpc / platforms / ps3 / spu.c

/*
 *  PS3 Platform spu routines.
 *
 *  Copyright (C) 2006 Sony Computer Entertainment Inc.
 *  Copyright 2006 Sony Corp.
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; version 2 of the License.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/mmzone.h>
#include <linux/io.h>
#include <linux/mm.h>

#include <asm/spu.h>
#include <asm/spu_priv1.h>
#include <asm/lv1call.h>
#include <asm/ps3.h>

#include "../cell/spufs/spufs.h"
#include "platform.h"

/* spu_management_ops */

/**
 * enum spe_type - Type of spe to create.
 * @spe_type_logical: Standard logical spe.
 *
 * For use with lv1_construct_logical_spe().  The current HV does not support
 * any types other than those listed.
 */

enum spe_type {
	SPE_TYPE_LOGICAL = 0,
};

/**
 * struct spe_shadow - logical spe shadow register area.
 *
 * Read-only shadow of spe registers.
 */

struct spe_shadow {
	u8 padding_0140[0x0140];
	u64 int_status_class0_RW;       /* 0x0140 */
	u64 int_status_class1_RW;       /* 0x0148 */
	u64 int_status_class2_RW;       /* 0x0150 */
	u8 padding_0158[0x0610-0x0158];
	u64 mfc_dsisr_RW;               /* 0x0610 */
	u8 padding_0618[0x0620-0x0618];
	u64 mfc_dar_RW;                 /* 0x0620 */
	u8 padding_0628[0x0800-0x0628];
	u64 mfc_dsipr_R;                /* 0x0800 */
	u8 padding_0808[0x0810-0x0808];
	u64 mfc_lscrr_R;                /* 0x0810 */
	u8 padding_0818[0x0c00-0x0818];
	u64 mfc_cer_R;                  /* 0x0c00 */
	u8 padding_0c08[0x0f00-0x0c08];
	u64 spe_execution_status;       /* 0x0f00 */
	u8 padding_0f08[0x1000-0x0f08];
};

/**
 * enum spe_ex_state - Logical spe execution state.
 * @spe_ex_state_unexecutable: Uninitialized.
 * @spe_ex_state_executable: Enabled, not ready.
 * @spe_ex_state_executed: Ready for use.
 *
 * The execution state (status) of the logical spe as reported in
 * struct spe_shadow:spe_execution_status.
 */

enum spe_ex_state {
	SPE_EX_STATE_UNEXECUTABLE = 0,
	SPE_EX_STATE_EXECUTABLE = 2,
	SPE_EX_STATE_EXECUTED = 3,
};

/**
 * struct priv1_cache - Cached values of priv1 registers.
 * @masks[]: Array of cached spe interrupt masks, indexed by class.
 * @sr1: Cached mfc_sr1 register.
 * @tclass_id: Cached mfc_tclass_id register.
 */

struct priv1_cache {
	u64 masks[3];
	u64 sr1;
	u64 tclass_id;
};

/**
 * struct spu_pdata - Platform state variables.
 * @spe_id: HV spe id returned by lv1_construct_logical_spe().
 * @resource_id: HV spe resource id returned by
 * 	ps3_repository_read_spe_resource_id().
 * @priv2_addr: lpar address of spe priv2 area returned by
 * 	lv1_construct_logical_spe().
 * @shadow_addr: lpar address of spe register shadow area returned by
 * 	lv1_construct_logical_spe().
 * @shadow: Virtual (ioremap) address of spe register shadow area.
 * @cache: Cached values of priv1 registers.
 */

struct spu_pdata {
	u64 spe_id;
	u64 resource_id;
	u64 priv2_addr;
	u64 shadow_addr;
	struct spe_shadow __iomem *shadow;
	struct priv1_cache cache;
};

static struct spu_pdata *spu_pdata(struct spu *spu)
{
	return spu->pdata;
}

#define dump_areas(_a, _b, _c, _d, _e) \
	_dump_areas(_a, _b, _c, _d, _e, __func__, __LINE__)
static void _dump_areas(unsigned int spe_id, unsigned long priv2,
	unsigned long problem, unsigned long ls, unsigned long shadow,
	const char* func, int line)
{
	pr_debug("%s:%d: spe_id:  %xh (%u)\n", func, line, spe_id, spe_id);
	pr_debug("%s:%d: priv2:   %lxh\n", func, line, priv2);
	pr_debug("%s:%d: problem: %lxh\n", func, line, problem);
	pr_debug("%s:%d: ls:      %lxh\n", func, line, ls);
	pr_debug("%s:%d: shadow:  %lxh\n", func, line, shadow);
}

inline u64 ps3_get_spe_id(void *arg)
{
	return spu_pdata(arg)->spe_id;
}
EXPORT_SYMBOL_GPL(ps3_get_spe_id);

static unsigned long get_vas_id(void)
{
	unsigned long id;

	lv1_get_logical_ppe_id(&id);
	lv1_get_virtual_address_space_id_of_ppe(id, &id);

	return id;
}

static int __init construct_spu(struct spu *spu)
{
	int result;
	unsigned long unused;

	result = lv1_construct_logical_spe(PAGE_SHIFT, PAGE_SHIFT, PAGE_SHIFT,
		PAGE_SHIFT, PAGE_SHIFT, get_vas_id(), SPE_TYPE_LOGICAL,
		&spu_pdata(spu)->priv2_addr, &spu->problem_phys,
		&spu->local_store_phys, &unused,
		&spu_pdata(spu)->shadow_addr,
		&spu_pdata(spu)->spe_id);

	if (result) {
		pr_debug("%s:%d: lv1_construct_logical_spe failed: %s\n",
			__func__, __LINE__, ps3_result(result));
		return result;
	}

	return result;
}

static void spu_unmap(struct spu *spu)
{
	iounmap(spu->priv2);
	iounmap(spu->problem);
	iounmap((__force u8 __iomem *)spu->local_store);
	iounmap(spu_pdata(spu)->shadow);
}

/**
 * setup_areas - Map the spu regions into the address space.
 *
 * The current HV requires the spu shadow regs to be mapped with the
 * PTE page protection bits set as read-only (PP=3).  This implementation
 * uses the low level __ioremap() to bypass the page protection settings
 * inforced by ioremap_flags() to get the needed PTE bits set for the
 * shadow regs.
 */

static int __init setup_areas(struct spu *spu)
{
	struct table {char* name; unsigned long addr; unsigned long size;};
	static const unsigned long shadow_flags = _PAGE_NO_CACHE | 3;

	spu_pdata(spu)->shadow = __ioremap(spu_pdata(spu)->shadow_addr,
					   sizeof(struct spe_shadow),
					   shadow_flags);
	if (!spu_pdata(spu)->shadow) {
		pr_debug("%s:%d: ioremap shadow failed\n", __func__, __LINE__);
		goto fail_ioremap;
	}

	spu->local_store = (__force void *)ioremap_flags(spu->local_store_phys,
		LS_SIZE, _PAGE_NO_CACHE);

	if (!spu->local_store) {
		pr_debug("%s:%d: ioremap local_store failed\n",
			__func__, __LINE__);
		goto fail_ioremap;
	}

	spu->problem = ioremap(spu->problem_phys,
		sizeof(struct spu_problem));

	if (!spu->problem) {
		pr_debug("%s:%d: ioremap problem failed\n", __func__, __LINE__);
		goto fail_ioremap;
	}

	spu->priv2 = ioremap(spu_pdata(spu)->priv2_addr,
		sizeof(struct spu_priv2));

	if (!spu->priv2) {
		pr_debug("%s:%d: ioremap priv2 failed\n", __func__, __LINE__);
		goto fail_ioremap;
	}

	dump_areas(spu_pdata(spu)->spe_id, spu_pdata(spu)->priv2_addr,
		spu->problem_phys, spu->local_store_phys,
		spu_pdata(spu)->shadow_addr);
	dump_areas(spu_pdata(spu)->spe_id, (unsigned long)spu->priv2,
		(unsigned long)spu->problem, (unsigned long)spu->local_store,
		(unsigned long)spu_pdata(spu)->shadow);

	return 0;

fail_ioremap:
	spu_unmap(spu);

	return -ENOMEM;
}

static int __init setup_interrupts(struct spu *spu)
{
	int result;

	result = ps3_spe_irq_setup(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id,
		0, &spu->irqs[0]);

	if (result)
		goto fail_alloc_0;

	result = ps3_spe_irq_setup(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id,
		1, &spu->irqs[1]);

	if (result)
		goto fail_alloc_1;

	result = ps3_spe_irq_setup(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id,
		2, &spu->irqs[2]);

	if (result)
		goto fail_alloc_2;

	return result;

fail_alloc_2:
	ps3_spe_irq_destroy(spu->irqs[1]);
fail_alloc_1:
	ps3_spe_irq_destroy(spu->irqs[0]);
fail_alloc_0:
	spu->irqs[0] = spu->irqs[1] = spu->irqs[2] = NO_IRQ;
	return result;
}

static int __init enable_spu(struct spu *spu)
{
	int result;

	result = lv1_enable_logical_spe(spu_pdata(spu)->spe_id,
		spu_pdata(spu)->resource_id);

	if (result) {
		pr_debug("%s:%d: lv1_enable_logical_spe failed: %s\n",
			__func__, __LINE__, ps3_result(result));
		goto fail_enable;
	}

	result = setup_areas(spu);

	if (result)
		goto fail_areas;

	result = setup_interrupts(spu);

	if (result)
		goto fail_interrupts;

	return 0;

fail_interrupts:
	spu_unmap(spu);
fail_areas:
	lv1_disable_logical_spe(spu_pdata(spu)->spe_id, 0);
fail_enable:
	return result;
}

static int ps3_destroy_spu(struct spu *spu)
{
	int result;

	pr_debug("%s:%d spu_%d\n", __func__, __LINE__, spu->number);

	result = lv1_disable_logical_spe(spu_pdata(spu)->spe_id, 0);
	BUG_ON(result);

	ps3_spe_irq_destroy(spu->irqs[2]);
	ps3_spe_irq_destroy(spu->irqs[1]);
	ps3_spe_irq_destroy(spu->irqs[0]);

	spu->irqs[0] = spu->irqs[1] = spu->irqs[2] = NO_IRQ;

	spu_unmap(spu);

	result = lv1_destruct_logical_spe(spu_pdata(spu)->spe_id);
	BUG_ON(result);

	kfree(spu->pdata);
	spu->pdata = NULL;

	return 0;
}

static int __init ps3_create_spu(struct spu *spu, void *data)
{
	int result;

	pr_debug("%s:%d spu_%d\n", __func__, __LINE__, spu->number);

	spu->pdata = kzalloc(sizeof(struct spu_pdata),
		GFP_KERNEL);

	if (!spu->pdata) {
		result = -ENOMEM;
		goto fail_malloc;
	}

	spu_pdata(spu)->resource_id = (unsigned long)data;

	/* Init cached reg values to HV defaults. */

	spu_pdata(spu)->cache.sr1 = 0x33;

	result = construct_spu(spu);

	if (result)
		goto fail_construct;

	/* For now, just go ahead and enable it. */

	result = enable_spu(spu);

	if (result)
		goto fail_enable;

	/* Make sure the spu is in SPE_EX_STATE_EXECUTED. */

	/* need something better here!!! */
	while (in_be64(&spu_pdata(spu)->shadow->spe_execution_status)
		!= SPE_EX_STATE_EXECUTED)
		(void)0;

	return result;

fail_enable:
fail_construct:
	ps3_destroy_spu(spu);
fail_malloc:
	return result;
}

static int __init ps3_enumerate_spus(int (*fn)(void *data))
{
	int result;
	unsigned int num_resource_id;
	unsigned int i;

	result = ps3_repository_read_num_spu_resource_id(&num_resource_id);

	pr_debug("%s:%d: num_resource_id %u\n", __func__, __LINE__,
		num_resource_id);

	/*
	 * For now, just create logical spus equal to the number
	 * of physical spus reserved for the partition.
	 */

	for (i = 0; i < num_resource_id; i++) {
		enum ps3_spu_resource_type resource_type;
		unsigned int resource_id;

		result = ps3_repository_read_spu_resource_id(i,
			&resource_type, &resource_id);

		if (result)
			break;

		if (resource_type == PS3_SPU_RESOURCE_TYPE_EXCLUSIVE) {
			result = fn((void*)(unsigned long)resource_id);

			if (result)
				break;
		}
	}

	if (result) {
		printk(KERN_WARNING "%s:%d: Error initializing spus\n",
			__func__, __LINE__);
		return result;
	}

	return num_resource_id;
}

static int ps3_init_affinity(void)
{
	return 0;
}

/**
 * ps3_enable_spu - Enable SPU run control.
 *
 * An outstanding enhancement for the PS3 would be to add a guard to check
 * for incorrect access to the spu problem state when the spu context is
 * disabled.  This check could be implemented with a flag added to the spu
 * context that would inhibit mapping problem state pages, and a routine
 * to unmap spu problem state pages.  When the spu is enabled with
 * ps3_enable_spu() the flag would be set allowing pages to be mapped,
 * and when the spu is disabled with ps3_disable_spu() the flag would be
 * cleared and the mapped problem state pages would be unmapped.
 */

static void ps3_enable_spu(struct spu_context *ctx)
{
}

static void ps3_disable_spu(struct spu_context *ctx)
{
	ctx->ops->runcntl_stop(ctx);
}

const struct spu_management_ops spu_management_ps3_ops = {
	.enumerate_spus = ps3_enumerate_spus,
	.create_spu = ps3_create_spu,
	.destroy_spu = ps3_destroy_spu,
	.enable_spu = ps3_enable_spu,
	.disable_spu = ps3_disable_spu,
	.init_affinity = ps3_init_affinity,
};

/* spu_priv1_ops */

static void int_mask_and(struct spu *spu, int class, u64 mask)
{
	u64 old_mask;

	/* are these serialized by caller??? */
	old_mask = spu_int_mask_get(spu, class);
	spu_int_mask_set(spu, class, old_mask & mask);
}

static void int_mask_or(struct spu *spu, int class, u64 mask)
{
	u64 old_mask;

	old_mask = spu_int_mask_get(spu, class);
	spu_int_mask_set(spu, class, old_mask | mask);
}

static void int_mask_set(struct spu *spu, int class, u64 mask)
{
	spu_pdata(spu)->cache.masks[class] = mask;
	lv1_set_spe_interrupt_mask(spu_pdata(spu)->spe_id, class,
		spu_pdata(spu)->cache.masks[class]);
}

static u64 int_mask_get(struct spu *spu, int class)
{
	return spu_pdata(spu)->cache.masks[class];
}

static void int_stat_clear(struct spu *spu, int class, u64 stat)
{
	/* Note that MFC_DSISR will be cleared when class1[MF] is set. */

	lv1_clear_spe_interrupt_status(spu_pdata(spu)->spe_id, class,
		stat, 0);
}

static u64 int_stat_get(struct spu *spu, int class)
{
	u64 stat;

	lv1_get_spe_interrupt_status(spu_pdata(spu)->spe_id, class, &stat);
	return stat;
}

static void cpu_affinity_set(struct spu *spu, int cpu)
{
	/* No support. */
}

static u64 mfc_dar_get(struct spu *spu)
{
	return in_be64(&spu_pdata(spu)->shadow->mfc_dar_RW);
}

static void mfc_dsisr_set(struct spu *spu, u64 dsisr)
{
	/* Nothing to do, cleared in int_stat_clear(). */
}

static u64 mfc_dsisr_get(struct spu *spu)
{
	return in_be64(&spu_pdata(spu)->shadow->mfc_dsisr_RW);
}

static void mfc_sdr_setup(struct spu *spu)
{
	/* Nothing to do. */
}

static void mfc_sr1_set(struct spu *spu, u64 sr1)
{
	/* Check bits allowed by HV. */

	static const u64 allowed = ~(MFC_STATE1_LOCAL_STORAGE_DECODE_MASK
		| MFC_STATE1_PROBLEM_STATE_MASK);

	BUG_ON((sr1 & allowed) != (spu_pdata(spu)->cache.sr1 & allowed));

	spu_pdata(spu)->cache.sr1 = sr1;
	lv1_set_spe_privilege_state_area_1_register(
		spu_pdata(spu)->spe_id,
		offsetof(struct spu_priv1, mfc_sr1_RW),
		spu_pdata(spu)->cache.sr1);
}

static u64 mfc_sr1_get(struct spu *spu)
{
	return spu_pdata(spu)->cache.sr1;
}

static void mfc_tclass_id_set(struct spu *spu, u64 tclass_id)
{
	spu_pdata(spu)->cache.tclass_id = tclass_id;
	lv1_set_spe_privilege_state_area_1_register(
		spu_pdata(spu)->spe_id,
		offsetof(struct spu_priv1, mfc_tclass_id_RW),
		spu_pdata(spu)->cache.tclass_id);
}

static u64 mfc_tclass_id_get(struct spu *spu)
{
	return spu_pdata(spu)->cache.tclass_id;
}

static void tlb_invalidate(struct spu *spu)
{
	/* Nothing to do. */
}

static void resource_allocation_groupID_set(struct spu *spu, u64 id)
{
	/* No support. */
}

static u64 resource_allocation_groupID_get(struct spu *spu)
{
	return 0; /* No support. */
}

static void resource_allocation_enable_set(struct spu *spu, u64 enable)
{
	/* No support. */
}

static u64 resource_allocation_enable_get(struct spu *spu)
{
	return 0; /* No support. */
}

const struct spu_priv1_ops spu_priv1_ps3_ops = {
	.int_mask_and = int_mask_and,
	.int_mask_or = int_mask_or,
	.int_mask_set = int_mask_set,
	.int_mask_get = int_mask_get,
	.int_stat_clear = int_stat_clear,
	.int_stat_get = int_stat_get,
	.cpu_affinity_set = cpu_affinity_set,
	.mfc_dar_get = mfc_dar_get,
	.mfc_dsisr_set = mfc_dsisr_set,
	.mfc_dsisr_get = mfc_dsisr_get,
	.mfc_sdr_setup = mfc_sdr_setup,
	.mfc_sr1_set = mfc_sr1_set,
	.mfc_sr1_get = mfc_sr1_get,
	.mfc_tclass_id_set = mfc_tclass_id_set,
	.mfc_tclass_id_get = mfc_tclass_id_get,
	.tlb_invalidate = tlb_invalidate,
	.resource_allocation_groupID_set = resource_allocation_groupID_set,
	.resource_allocation_groupID_get = resource_allocation_groupID_get,
	.resource_allocation_enable_set = resource_allocation_enable_set,
	.resource_allocation_enable_get = resource_allocation_enable_get,
};

void ps3_spu_set_platform(void)
{
	spu_priv1_ops = &spu_priv1_ps3_ops;
	spu_management_ops = &spu_management_ps3_ops;
}
Commit	Line	Data
de91a534 GL	1	/*
	2	* PS3 Platform spu routines.
	3	*
	4	* Copyright (C) 2006 Sony Computer Entertainment Inc.
	5	* Copyright 2006 Sony Corp.
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; version 2 of the License.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20
	21	#include <linux/kernel.h>
	22	#include <linux/init.h>
	23	#include <linux/mmzone.h>
	24	#include <linux/io.h>
	25	#include <linux/mm.h>
	26
	27	#include <asm/spu.h>
	28	#include <asm/spu_priv1.h>
de91a534	29	#include <asm/lv1call.h>
23afcb4e	30	#include <asm/ps3.h>
de91a534	31
c25620d7	32	#include "../cell/spufs/spufs.h"
2a08ea69 GL	33	#include "platform.h"
2a08ea69 GL	34
de91a534 GL	35	/* spu_management_ops */
	36
	37	/**
	38	* enum spe_type - Type of spe to create.
	39	* @spe_type_logical: Standard logical spe.
	40	*
	41	* For use with lv1_construct_logical_spe(). The current HV does not support
	42	* any types other than those listed.
	43	*/
	44
	45	enum spe_type {
	46	SPE_TYPE_LOGICAL = 0,
	47	};
	48
	49	/**
	50	* struct spe_shadow - logical spe shadow register area.
	51	*
	52	* Read-only shadow of spe registers.
	53	*/
	54
	55	struct spe_shadow {
a8229a9e	56	u8 padding_0140[0x0140];
de91a534 GL	57	u64 int_status_class0_RW; /* 0x0140 */
	58	u64 int_status_class1_RW; /* 0x0148 */
	59	u64 int_status_class2_RW; /* 0x0150 */
	60	u8 padding_0158[0x0610-0x0158];
	61	u64 mfc_dsisr_RW; /* 0x0610 */
	62	u8 padding_0618[0x0620-0x0618];
	63	u64 mfc_dar_RW; /* 0x0620 */
	64	u8 padding_0628[0x0800-0x0628];
	65	u64 mfc_dsipr_R; /* 0x0800 */
	66	u8 padding_0808[0x0810-0x0808];
	67	u64 mfc_lscrr_R; /* 0x0810 */
	68	u8 padding_0818[0x0c00-0x0818];
	69	u64 mfc_cer_R; /* 0x0c00 */
	70	u8 padding_0c08[0x0f00-0x0c08];
	71	u64 spe_execution_status; /* 0x0f00 */
	72	u8 padding_0f08[0x1000-0x0f08];
a8229a9e	73	};
de91a534 GL	74
	75	/**
	76	* enum spe_ex_state - Logical spe execution state.
	77	* @spe_ex_state_unexecutable: Uninitialized.
	78	* @spe_ex_state_executable: Enabled, not ready.
	79	* @spe_ex_state_executed: Ready for use.
	80	*
	81	* The execution state (status) of the logical spe as reported in
	82	* struct spe_shadow:spe_execution_status.
	83	*/
	84
	85	enum spe_ex_state {
	86	SPE_EX_STATE_UNEXECUTABLE = 0,
	87	SPE_EX_STATE_EXECUTABLE = 2,
	88	SPE_EX_STATE_EXECUTED = 3,
	89	};
	90
	91	/**
	92	* struct priv1_cache - Cached values of priv1 registers.
	93	* @masks[]: Array of cached spe interrupt masks, indexed by class.
	94	* @sr1: Cached mfc_sr1 register.
	95	* @tclass_id: Cached mfc_tclass_id register.
	96	*/
	97
	98	struct priv1_cache {
	99	u64 masks[3];
	100	u64 sr1;
	101	u64 tclass_id;
	102	};
	103
	104	/**
	105	* struct spu_pdata - Platform state variables.
	106	* @spe_id: HV spe id returned by lv1_construct_logical_spe().
	107	* @resource_id: HV spe resource id returned by
	108	* ps3_repository_read_spe_resource_id().
	109	* @priv2_addr: lpar address of spe priv2 area returned by
	110	* lv1_construct_logical_spe().
	111	* @shadow_addr: lpar address of spe register shadow area returned by
	112	* lv1_construct_logical_spe().
	113	* @shadow: Virtual (ioremap) address of spe register shadow area.
	114	* @cache: Cached values of priv1 registers.
	115	*/
	116
	117	struct spu_pdata {
	118	u64 spe_id;
	119	u64 resource_id;
	120	u64 priv2_addr;
	121	u64 shadow_addr;
	122	struct spe_shadow __iomem *shadow;
	123	struct priv1_cache cache;
	124	};
	125
	126	static struct spu_pdata spu_pdata(struct spu spu)
	127	{
	128	return spu->pdata;
	129	}
	130
	131	#define dump_areas(_a, _b, _c, _d, _e) \
	132	_dump_areas(_a, _b, _c, _d, _e, __func__, __LINE__)
	133	static void _dump_areas(unsigned int spe_id, unsigned long priv2,
	134	unsigned long problem, unsigned long ls, unsigned long shadow,
	135	const char* func, int line)
	136	{
	137	pr_debug("%s:%d: spe_id: %xh (%u)\n", func, line, spe_id, spe_id);
138	pr_debug("%s:%d: priv2: %lxh\n", func, line, priv2);
139	pr_debug("%s:%d: problem: %lxh\n", func, line, problem);
140	pr_debug("%s:%d: ls: %lxh\n", func, line, ls);
141	pr_debug("%s:%d: shadow: %lxh\n", func, line, shadow);
142	}
143
23afcb4e TY	144	inline u64 ps3_get_spe_id(void *arg)
	145	{
	146	return spu_pdata(arg)->spe_id;
	147	}
	148	EXPORT_SYMBOL_GPL(ps3_get_spe_id);
	149
de91a534 GL	150	static unsigned long get_vas_id(void)
	151	{
	152	unsigned long id;
	153
	154	lv1_get_logical_ppe_id(&id);
	155	lv1_get_virtual_address_space_id_of_ppe(id, &id);
	156
	157	return id;
	158	}
	159
	160	static int __init construct_spu(struct spu *spu)
	161	{
	162	int result;
	163	unsigned long unused;
	164
	165	result = lv1_construct_logical_spe(PAGE_SHIFT, PAGE_SHIFT, PAGE_SHIFT,
	166	PAGE_SHIFT, PAGE_SHIFT, get_vas_id(), SPE_TYPE_LOGICAL,
	167	&spu_pdata(spu)->priv2_addr, &spu->problem_phys,
	168	&spu->local_store_phys, &unused,
	169	&spu_pdata(spu)->shadow_addr,
	170	&spu_pdata(spu)->spe_id);
	171
	172	if (result) {
	173	pr_debug("%s:%d: lv1_construct_logical_spe failed: %s\n",
	174	__func__, __LINE__, ps3_result(result));
	175	return result;
	176	}
	177
	178	return result;
	179	}
	180
de91a534 GL	181	static void spu_unmap(struct spu *spu)
	182	{
	183	iounmap(spu->priv2);
	184	iounmap(spu->problem);
	185	iounmap((__force u8 __iomem *)spu->local_store);
	186	iounmap(spu_pdata(spu)->shadow);
	187	}
	188
b4702779 MM	189	/**
	190	* setup_areas - Map the spu regions into the address space.
	191	*
	192	* The current HV requires the spu shadow regs to be mapped with the
	193	* PTE page protection bits set as read-only (PP=3). This implementation
	194	* uses the low level __ioremap() to bypass the page protection settings
	195	* inforced by ioremap_flags() to get the needed PTE bits set for the
	196	* shadow regs.
	197	*/
	198
de91a534 GL	199	static int __init setup_areas(struct spu *spu)
	200	{
	201	struct table {char* name; unsigned long addr; unsigned long size;};
b4702779	202	static const unsigned long shadow_flags = _PAGE_NO_CACHE \| 3;
de91a534	203
b4702779 MM	204	spu_pdata(spu)->shadow = __ioremap(spu_pdata(spu)->shadow_addr,
	205	sizeof(struct spe_shadow),
	206	shadow_flags);
de91a534 GL	207	if (!spu_pdata(spu)->shadow) {
	208	pr_debug("%s:%d: ioremap shadow failed\n", __func__, __LINE__);
	209	goto fail_ioremap;
	210	}
	211
53f7c545 GL	212	spu->local_store = (__force void *)ioremap_flags(spu->local_store_phys,
	213	LS_SIZE, _PAGE_NO_CACHE);
	214
de91a534 GL	215	if (!spu->local_store) {
	216	pr_debug("%s:%d: ioremap local_store failed\n",
	217	__func__, __LINE__);
	218	goto fail_ioremap;
	219	}
	220
	221	spu->problem = ioremap(spu->problem_phys,
	222	sizeof(struct spu_problem));
53f7c545	223
de91a534 GL	224	if (!spu->problem) {
	225	pr_debug("%s:%d: ioremap problem failed\n", __func__, __LINE__);
	226	goto fail_ioremap;
	227	}
	228
	229	spu->priv2 = ioremap(spu_pdata(spu)->priv2_addr,
	230	sizeof(struct spu_priv2));
53f7c545	231
de91a534 GL	232	if (!spu->priv2) {
	233	pr_debug("%s:%d: ioremap priv2 failed\n", __func__, __LINE__);
	234	goto fail_ioremap;
	235	}
	236
	237	dump_areas(spu_pdata(spu)->spe_id, spu_pdata(spu)->priv2_addr,
	238	spu->problem_phys, spu->local_store_phys,
	239	spu_pdata(spu)->shadow_addr);
	240	dump_areas(spu_pdata(spu)->spe_id, (unsigned long)spu->priv2,
	241	(unsigned long)spu->problem, (unsigned long)spu->local_store,
	242	(unsigned long)spu_pdata(spu)->shadow);
	243
	244	return 0;
	245
	246	fail_ioremap:
	247	spu_unmap(spu);
44430e0d BH	248
44430e0d BH	249	return -ENOMEM;
de91a534 GL	250	}
	251
	252	static int __init setup_interrupts(struct spu *spu)
	253	{
	254	int result;
	255
dc4f60c2	256	result = ps3_spe_irq_setup(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id,
861be32c	257	0, &spu->irqs[0]);
de91a534 GL	258
	259	if (result)
	260	goto fail_alloc_0;
	261
dc4f60c2	262	result = ps3_spe_irq_setup(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id,
861be32c	263	1, &spu->irqs[1]);
de91a534 GL	264
	265	if (result)
	266	goto fail_alloc_1;
	267
dc4f60c2	268	result = ps3_spe_irq_setup(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id,
861be32c	269	2, &spu->irqs[2]);
de91a534 GL	270
	271	if (result)
	272	goto fail_alloc_2;
	273
	274	return result;
	275
	276	fail_alloc_2:
dc4f60c2	277	ps3_spe_irq_destroy(spu->irqs[1]);
de91a534	278	fail_alloc_1:
dc4f60c2	279	ps3_spe_irq_destroy(spu->irqs[0]);
de91a534 GL	280	fail_alloc_0:
	281	spu->irqs[0] = spu->irqs[1] = spu->irqs[2] = NO_IRQ;
	282	return result;
	283	}
	284
	285	static int __init enable_spu(struct spu *spu)
	286	{
	287	int result;
	288
	289	result = lv1_enable_logical_spe(spu_pdata(spu)->spe_id,
	290	spu_pdata(spu)->resource_id);
	291
	292	if (result) {
	293	pr_debug("%s:%d: lv1_enable_logical_spe failed: %s\n",
	294	__func__, __LINE__, ps3_result(result));
	295	goto fail_enable;
	296	}
	297
	298	result = setup_areas(spu);
	299
	300	if (result)
	301	goto fail_areas;
	302
	303	result = setup_interrupts(spu);
	304
	305	if (result)
	306	goto fail_interrupts;
	307
	308	return 0;
	309
	310	fail_interrupts:
	311	spu_unmap(spu);
	312	fail_areas:
	313	lv1_disable_logical_spe(spu_pdata(spu)->spe_id, 0);
	314	fail_enable:
	315	return result;
	316	}
	317
	318	static int ps3_destroy_spu(struct spu *spu)
	319	{
	320	int result;
	321
	322	pr_debug("%s:%d spu_%d\n", __func__, __LINE__, spu->number);
	323
	324	result = lv1_disable_logical_spe(spu_pdata(spu)->spe_id, 0);
	325	BUG_ON(result);
	326
dc4f60c2 GL	327	ps3_spe_irq_destroy(spu->irqs[2]);
	328	ps3_spe_irq_destroy(spu->irqs[1]);
	329	ps3_spe_irq_destroy(spu->irqs[0]);
de91a534 GL	330
	331	spu->irqs[0] = spu->irqs[1] = spu->irqs[2] = NO_IRQ;
	332
	333	spu_unmap(spu);
	334
	335	result = lv1_destruct_logical_spe(spu_pdata(spu)->spe_id);
	336	BUG_ON(result);
	337
	338	kfree(spu->pdata);
	339	spu->pdata = NULL;
	340
	341	return 0;
	342	}
	343
	344	static int __init ps3_create_spu(struct spu spu, void data)
	345	{
	346	int result;
	347
	348	pr_debug("%s:%d spu_%d\n", __func__, __LINE__, spu->number);
	349
	350	spu->pdata = kzalloc(sizeof(struct spu_pdata),
	351	GFP_KERNEL);
	352
	353	if (!spu->pdata) {
	354	result = -ENOMEM;
	355	goto fail_malloc;
	356	}
	357
	358	spu_pdata(spu)->resource_id = (unsigned long)data;
	359
	360	/* Init cached reg values to HV defaults. */
	361
	362	spu_pdata(spu)->cache.sr1 = 0x33;
	363
	364	result = construct_spu(spu);
	365
	366	if (result)
	367	goto fail_construct;
	368
	369	/* For now, just go ahead and enable it. */
	370
	371	result = enable_spu(spu);
	372
	373	if (result)
	374	goto fail_enable;
	375
	376	/* Make sure the spu is in SPE_EX_STATE_EXECUTED. */
	377
	378	/* need something better here!!! */
	379	while (in_be64(&spu_pdata(spu)->shadow->spe_execution_status)
	380	!= SPE_EX_STATE_EXECUTED)
	381	(void)0;
	382
	383	return result;
	384
	385	fail_enable:
	386	fail_construct:
	387	ps3_destroy_spu(spu);
	388	fail_malloc:
	389	return result;
	390	}
	391
	392	static int __init ps3_enumerate_spus(int (fn)(void data))
	393	{
394	int result;
395	unsigned int num_resource_id;
396	unsigned int i;
397
398	result = ps3_repository_read_num_spu_resource_id(&num_resource_id);
399
400	pr_debug("%s:%d: num_resource_id %u\n", __func__, __LINE__,
401	num_resource_id);
402
403	/*
404	* For now, just create logical spus equal to the number
405	* of physical spus reserved for the partition.
406	*/
407
408	for (i = 0; i < num_resource_id; i++) {
409	enum ps3_spu_resource_type resource_type;
410	unsigned int resource_id;
411
412	result = ps3_repository_read_spu_resource_id(i,
413	&resource_type, &resource_id);
414
415	if (result)
416	break;
417
418	if (resource_type == PS3_SPU_RESOURCE_TYPE_EXCLUSIVE) {
419	result = fn((void*)(unsigned long)resource_id);
420
421	if (result)
422	break;
423	}
424	}
425
bce94513	426	if (result) {
de91a534 GL	427	printk(KERN_WARNING "%s:%d: Error initializing spus\n",
de91a534 GL	428	__func__, __LINE__);
bce94513 GU	429	return result;
bce94513 GU	430	}
de91a534	431
bce94513	432	return num_resource_id;
de91a534 GL	433	}
de91a534 GL	434
f5996449 AD	435	static int ps3_init_affinity(void)
	436	{
	437	return 0;
	438	}
	439
c25620d7 MN	440	/**
	441	* ps3_enable_spu - Enable SPU run control.
	442	*
	443	* An outstanding enhancement for the PS3 would be to add a guard to check
	444	* for incorrect access to the spu problem state when the spu context is
	445	* disabled. This check could be implemented with a flag added to the spu
	446	* context that would inhibit mapping problem state pages, and a routine
	447	* to unmap spu problem state pages. When the spu is enabled with
	448	* ps3_enable_spu() the flag would be set allowing pages to be mapped,
	449	* and when the spu is disabled with ps3_disable_spu() the flag would be
	450	* cleared and the mapped problem state pages would be unmapped.
	451	*/
	452
	453	static void ps3_enable_spu(struct spu_context *ctx)
	454	{
	455	}
	456
	457	static void ps3_disable_spu(struct spu_context *ctx)
	458	{
	459	ctx->ops->runcntl_stop(ctx);
	460	}
	461
de91a534 GL	462	const struct spu_management_ops spu_management_ps3_ops = {
	463	.enumerate_spus = ps3_enumerate_spus,
	464	.create_spu = ps3_create_spu,
	465	.destroy_spu = ps3_destroy_spu,
c25620d7 MN	466	.enable_spu = ps3_enable_spu,
c25620d7 MN	467	.disable_spu = ps3_disable_spu,
f5996449	468	.init_affinity = ps3_init_affinity,
de91a534 GL	469	};
	470
	471	/* spu_priv1_ops */
	472
	473	static void int_mask_and(struct spu *spu, int class, u64 mask)
	474	{
	475	u64 old_mask;
	476
	477	/* are these serialized by caller??? */
	478	old_mask = spu_int_mask_get(spu, class);
	479	spu_int_mask_set(spu, class, old_mask & mask);
	480	}
	481
	482	static void int_mask_or(struct spu *spu, int class, u64 mask)
	483	{
	484	u64 old_mask;
	485
	486	old_mask = spu_int_mask_get(spu, class);
	487	spu_int_mask_set(spu, class, old_mask \| mask);
	488	}
	489
	490	static void int_mask_set(struct spu *spu, int class, u64 mask)
	491	{
	492	spu_pdata(spu)->cache.masks[class] = mask;
	493	lv1_set_spe_interrupt_mask(spu_pdata(spu)->spe_id, class,
	494	spu_pdata(spu)->cache.masks[class]);
	495	}
	496
	497	static u64 int_mask_get(struct spu *spu, int class)
	498	{
	499	return spu_pdata(spu)->cache.masks[class];
	500	}
	501
	502	static void int_stat_clear(struct spu *spu, int class, u64 stat)
	503	{
	504	/* Note that MFC_DSISR will be cleared when class1[MF] is set. */
	505
	506	lv1_clear_spe_interrupt_status(spu_pdata(spu)->spe_id, class,
	507	stat, 0);
	508	}
	509
	510	static u64 int_stat_get(struct spu *spu, int class)
	511	{
	512	u64 stat;
	513
	514	lv1_get_spe_interrupt_status(spu_pdata(spu)->spe_id, class, &stat);
	515	return stat;
	516	}
	517
	518	static void cpu_affinity_set(struct spu *spu, int cpu)
	519	{
	520	/* No support. */
	521	}
	522
	523	static u64 mfc_dar_get(struct spu *spu)
	524	{
	525	return in_be64(&spu_pdata(spu)->shadow->mfc_dar_RW);
	526	}
	527
	528	static void mfc_dsisr_set(struct spu *spu, u64 dsisr)
	529	{
	530	/* Nothing to do, cleared in int_stat_clear(). */
	531	}
	532
533	static u64 mfc_dsisr_get(struct spu *spu)
534	{
535	return in_be64(&spu_pdata(spu)->shadow->mfc_dsisr_RW);
536	}
537
538	static void mfc_sdr_setup(struct spu *spu)
539	{
540	/* Nothing to do. */
541	}
542
543	static void mfc_sr1_set(struct spu *spu, u64 sr1)
544	{
545	/* Check bits allowed by HV. */
546
547	static const u64 allowed = ~(MFC_STATE1_LOCAL_STORAGE_DECODE_MASK
548	\| MFC_STATE1_PROBLEM_STATE_MASK);
549
550	BUG_ON((sr1 & allowed) != (spu_pdata(spu)->cache.sr1 & allowed));
551
552	spu_pdata(spu)->cache.sr1 = sr1;
553	lv1_set_spe_privilege_state_area_1_register(
554	spu_pdata(spu)->spe_id,
555	offsetof(struct spu_priv1, mfc_sr1_RW),
556	spu_pdata(spu)->cache.sr1);
557	}
558
559	static u64 mfc_sr1_get(struct spu *spu)
560	{
561	return spu_pdata(spu)->cache.sr1;
562	}
563
564	static void mfc_tclass_id_set(struct spu *spu, u64 tclass_id)
565	{
566	spu_pdata(spu)->cache.tclass_id = tclass_id;
567	lv1_set_spe_privilege_state_area_1_register(
568	spu_pdata(spu)->spe_id,
569	offsetof(struct spu_priv1, mfc_tclass_id_RW),
570	spu_pdata(spu)->cache.tclass_id);
571	}
572
573	static u64 mfc_tclass_id_get(struct spu *spu)
574	{
575	return spu_pdata(spu)->cache.tclass_id;
576	}
577
578	static void tlb_invalidate(struct spu *spu)
579	{
580	/* Nothing to do. */
581	}
582
583	static void resource_allocation_groupID_set(struct spu *spu, u64 id)
584	{
585	/* No support. */
586	}
587
588	static u64 resource_allocation_groupID_get(struct spu *spu)
589	{
590	return 0; /* No support. */
591	}
592
593	static void resource_allocation_enable_set(struct spu *spu, u64 enable)
594	{
595	/* No support. */
596	}
597
598	static u64 resource_allocation_enable_get(struct spu *spu)
599	{
600	return 0; /* No support. */
601	}
602
603	const struct spu_priv1_ops spu_priv1_ps3_ops = {
604	.int_mask_and = int_mask_and,
605	.int_mask_or = int_mask_or,
606	.int_mask_set = int_mask_set,
607	.int_mask_get = int_mask_get,
608	.int_stat_clear = int_stat_clear,
609	.int_stat_get = int_stat_get,
610	.cpu_affinity_set = cpu_affinity_set,
611	.mfc_dar_get = mfc_dar_get,
612	.mfc_dsisr_set = mfc_dsisr_set,
613	.mfc_dsisr_get = mfc_dsisr_get,
614	.mfc_sdr_setup = mfc_sdr_setup,
615	.mfc_sr1_set = mfc_sr1_set,
616	.mfc_sr1_get = mfc_sr1_get,
617	.mfc_tclass_id_set = mfc_tclass_id_set,
618	.mfc_tclass_id_get = mfc_tclass_id_get,
619	.tlb_invalidate = tlb_invalidate,
620	.resource_allocation_groupID_set = resource_allocation_groupID_set,
621	.resource_allocation_groupID_get = resource_allocation_groupID_get,
622	.resource_allocation_enable_set = resource_allocation_enable_set,
623	.resource_allocation_enable_get = resource_allocation_enable_get,
624	};
625
626	void ps3_spu_set_platform(void)
627	{
628	spu_priv1_ops = &spu_priv1_ps3_ops;
629	spu_management_ops = &spu_management_ps3_ops;
630	}