Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation |
3 | * | |
bc97ce95 | 4 | * Rewrite, cleanup: |
1da177e4 | 5 | * |
91f14480 | 6 | * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation |
bc97ce95 | 7 | * Copyright (C) 2006 Olof Johansson <olof@lixom.net> |
1da177e4 LT |
8 | * |
9 | * Dynamic DMA mapping support, pSeries-specific parts, both SMP and LPAR. | |
10 | * | |
bc97ce95 | 11 | * |
1da177e4 LT |
12 | * This program is free software; you can redistribute it and/or modify |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
bc97ce95 | 16 | * |
1da177e4 LT |
17 | * This program is distributed in the hope that it will be useful, |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
bc97ce95 | 21 | * |
1da177e4 LT |
22 | * You should have received a copy of the GNU General Public License |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
25 | */ | |
26 | ||
1da177e4 LT |
27 | #include <linux/init.h> |
28 | #include <linux/types.h> | |
29 | #include <linux/slab.h> | |
30 | #include <linux/mm.h> | |
31 | #include <linux/spinlock.h> | |
32 | #include <linux/string.h> | |
33 | #include <linux/pci.h> | |
34 | #include <linux/dma-mapping.h> | |
62a8bd6c | 35 | #include <linux/crash_dump.h> |
1da177e4 LT |
36 | #include <asm/io.h> |
37 | #include <asm/prom.h> | |
38 | #include <asm/rtas.h> | |
1da177e4 LT |
39 | #include <asm/iommu.h> |
40 | #include <asm/pci-bridge.h> | |
41 | #include <asm/machdep.h> | |
42 | #include <asm/abs_addr.h> | |
1da177e4 | 43 | #include <asm/pSeries_reconfig.h> |
1ababe11 | 44 | #include <asm/firmware.h> |
c707ffcf | 45 | #include <asm/tce.h> |
d387899f | 46 | #include <asm/ppc-pci.h> |
2249ca9d | 47 | #include <asm/udbg.h> |
1da177e4 | 48 | |
a1218720 ME |
49 | #include "plpar_wrappers.h" |
50 | ||
1da177e4 | 51 | |
6490c490 | 52 | static int tce_build_pSeries(struct iommu_table *tbl, long index, |
bc97ce95 | 53 | long npages, unsigned long uaddr, |
4f3dd8a0 MN |
54 | enum dma_data_direction direction, |
55 | struct dma_attrs *attrs) | |
1da177e4 | 56 | { |
bc97ce95 OJ |
57 | u64 proto_tce; |
58 | u64 *tcep; | |
59 | u64 rpn; | |
1da177e4 | 60 | |
bc97ce95 | 61 | proto_tce = TCE_PCI_READ; // Read allowed |
1da177e4 LT |
62 | |
63 | if (direction != DMA_TO_DEVICE) | |
bc97ce95 | 64 | proto_tce |= TCE_PCI_WRITE; |
1da177e4 | 65 | |
bc97ce95 | 66 | tcep = ((u64 *)tbl->it_base) + index; |
1da177e4 LT |
67 | |
68 | while (npages--) { | |
69 | /* can't move this out since we might cross LMB boundary */ | |
bc97ce95 OJ |
70 | rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT; |
71 | *tcep = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT; | |
1da177e4 | 72 | |
d0035c62 | 73 | uaddr += TCE_PAGE_SIZE; |
bc97ce95 | 74 | tcep++; |
1da177e4 | 75 | } |
6490c490 | 76 | return 0; |
1da177e4 LT |
77 | } |
78 | ||
79 | ||
80 | static void tce_free_pSeries(struct iommu_table *tbl, long index, long npages) | |
81 | { | |
bc97ce95 | 82 | u64 *tcep; |
1da177e4 | 83 | |
bc97ce95 OJ |
84 | tcep = ((u64 *)tbl->it_base) + index; |
85 | ||
86 | while (npages--) | |
87 | *(tcep++) = 0; | |
1da177e4 LT |
88 | } |
89 | ||
5f50867b HM |
90 | static unsigned long tce_get_pseries(struct iommu_table *tbl, long index) |
91 | { | |
92 | u64 *tcep; | |
93 | ||
5f50867b HM |
94 | tcep = ((u64 *)tbl->it_base) + index; |
95 | ||
96 | return *tcep; | |
97 | } | |
1da177e4 | 98 | |
6490c490 RJ |
99 | static void tce_free_pSeriesLP(struct iommu_table*, long, long); |
100 | static void tce_freemulti_pSeriesLP(struct iommu_table*, long, long); | |
101 | ||
102 | static int tce_build_pSeriesLP(struct iommu_table *tbl, long tcenum, | |
1da177e4 | 103 | long npages, unsigned long uaddr, |
4f3dd8a0 MN |
104 | enum dma_data_direction direction, |
105 | struct dma_attrs *attrs) | |
1da177e4 | 106 | { |
6490c490 | 107 | u64 rc = 0; |
bc97ce95 OJ |
108 | u64 proto_tce, tce; |
109 | u64 rpn; | |
6490c490 RJ |
110 | int ret = 0; |
111 | long tcenum_start = tcenum, npages_start = npages; | |
1da177e4 | 112 | |
bc97ce95 OJ |
113 | rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT; |
114 | proto_tce = TCE_PCI_READ; | |
1da177e4 | 115 | if (direction != DMA_TO_DEVICE) |
bc97ce95 | 116 | proto_tce |= TCE_PCI_WRITE; |
1da177e4 LT |
117 | |
118 | while (npages--) { | |
bc97ce95 OJ |
119 | tce = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT; |
120 | rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, tce); | |
121 | ||
6490c490 RJ |
122 | if (unlikely(rc == H_NOT_ENOUGH_RESOURCES)) { |
123 | ret = (int)rc; | |
124 | tce_free_pSeriesLP(tbl, tcenum_start, | |
125 | (npages_start - (npages + 1))); | |
126 | break; | |
127 | } | |
128 | ||
1da177e4 | 129 | if (rc && printk_ratelimit()) { |
fe333321 IM |
130 | printk("tce_build_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc); |
131 | printk("\tindex = 0x%llx\n", (u64)tbl->it_index); | |
132 | printk("\ttcenum = 0x%llx\n", (u64)tcenum); | |
133 | printk("\ttce val = 0x%llx\n", tce ); | |
1da177e4 LT |
134 | show_stack(current, (unsigned long *)__get_SP()); |
135 | } | |
bc97ce95 | 136 | |
1da177e4 | 137 | tcenum++; |
bc97ce95 | 138 | rpn++; |
1da177e4 | 139 | } |
6490c490 | 140 | return ret; |
1da177e4 LT |
141 | } |
142 | ||
bc97ce95 | 143 | static DEFINE_PER_CPU(u64 *, tce_page) = NULL; |
1da177e4 | 144 | |
6490c490 | 145 | static int tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum, |
1da177e4 | 146 | long npages, unsigned long uaddr, |
4f3dd8a0 MN |
147 | enum dma_data_direction direction, |
148 | struct dma_attrs *attrs) | |
1da177e4 | 149 | { |
6490c490 | 150 | u64 rc = 0; |
bc97ce95 OJ |
151 | u64 proto_tce; |
152 | u64 *tcep; | |
153 | u64 rpn; | |
1da177e4 | 154 | long l, limit; |
6490c490 RJ |
155 | long tcenum_start = tcenum, npages_start = npages; |
156 | int ret = 0; | |
1da177e4 | 157 | |
541b2755 | 158 | if (npages == 1) { |
6490c490 RJ |
159 | return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr, |
160 | direction, attrs); | |
541b2755 | 161 | } |
1da177e4 LT |
162 | |
163 | tcep = __get_cpu_var(tce_page); | |
164 | ||
165 | /* This is safe to do since interrupts are off when we're called | |
166 | * from iommu_alloc{,_sg}() | |
167 | */ | |
168 | if (!tcep) { | |
bc97ce95 | 169 | tcep = (u64 *)__get_free_page(GFP_ATOMIC); |
1da177e4 | 170 | /* If allocation fails, fall back to the loop implementation */ |
541b2755 | 171 | if (!tcep) { |
6490c490 | 172 | return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr, |
4f3dd8a0 | 173 | direction, attrs); |
541b2755 | 174 | } |
1da177e4 LT |
175 | __get_cpu_var(tce_page) = tcep; |
176 | } | |
177 | ||
bc97ce95 OJ |
178 | rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT; |
179 | proto_tce = TCE_PCI_READ; | |
1da177e4 | 180 | if (direction != DMA_TO_DEVICE) |
bc97ce95 | 181 | proto_tce |= TCE_PCI_WRITE; |
1da177e4 LT |
182 | |
183 | /* We can map max one pageful of TCEs at a time */ | |
184 | do { | |
185 | /* | |
186 | * Set up the page with TCE data, looping through and setting | |
187 | * the values. | |
188 | */ | |
bc97ce95 | 189 | limit = min_t(long, npages, 4096/TCE_ENTRY_SIZE); |
1da177e4 LT |
190 | |
191 | for (l = 0; l < limit; l++) { | |
bc97ce95 OJ |
192 | tcep[l] = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT; |
193 | rpn++; | |
1da177e4 LT |
194 | } |
195 | ||
196 | rc = plpar_tce_put_indirect((u64)tbl->it_index, | |
197 | (u64)tcenum << 12, | |
198 | (u64)virt_to_abs(tcep), | |
199 | limit); | |
200 | ||
201 | npages -= limit; | |
202 | tcenum += limit; | |
203 | } while (npages > 0 && !rc); | |
204 | ||
6490c490 RJ |
205 | if (unlikely(rc == H_NOT_ENOUGH_RESOURCES)) { |
206 | ret = (int)rc; | |
207 | tce_freemulti_pSeriesLP(tbl, tcenum_start, | |
208 | (npages_start - (npages + limit))); | |
209 | return ret; | |
210 | } | |
211 | ||
1da177e4 | 212 | if (rc && printk_ratelimit()) { |
fe333321 IM |
213 | printk("tce_buildmulti_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc); |
214 | printk("\tindex = 0x%llx\n", (u64)tbl->it_index); | |
215 | printk("\tnpages = 0x%llx\n", (u64)npages); | |
216 | printk("\ttce[0] val = 0x%llx\n", tcep[0]); | |
1da177e4 LT |
217 | show_stack(current, (unsigned long *)__get_SP()); |
218 | } | |
6490c490 | 219 | return ret; |
1da177e4 LT |
220 | } |
221 | ||
222 | static void tce_free_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages) | |
223 | { | |
224 | u64 rc; | |
1da177e4 | 225 | |
1da177e4 | 226 | while (npages--) { |
bc97ce95 | 227 | rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, 0); |
1da177e4 LT |
228 | |
229 | if (rc && printk_ratelimit()) { | |
fe333321 IM |
230 | printk("tce_free_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc); |
231 | printk("\tindex = 0x%llx\n", (u64)tbl->it_index); | |
232 | printk("\ttcenum = 0x%llx\n", (u64)tcenum); | |
1da177e4 LT |
233 | show_stack(current, (unsigned long *)__get_SP()); |
234 | } | |
235 | ||
236 | tcenum++; | |
237 | } | |
238 | } | |
239 | ||
240 | ||
241 | static void tce_freemulti_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages) | |
242 | { | |
243 | u64 rc; | |
1da177e4 | 244 | |
bc97ce95 | 245 | rc = plpar_tce_stuff((u64)tbl->it_index, (u64)tcenum << 12, 0, npages); |
1da177e4 LT |
246 | |
247 | if (rc && printk_ratelimit()) { | |
248 | printk("tce_freemulti_pSeriesLP: plpar_tce_stuff failed\n"); | |
fe333321 IM |
249 | printk("\trc = %lld\n", rc); |
250 | printk("\tindex = 0x%llx\n", (u64)tbl->it_index); | |
251 | printk("\tnpages = 0x%llx\n", (u64)npages); | |
1da177e4 LT |
252 | show_stack(current, (unsigned long *)__get_SP()); |
253 | } | |
254 | } | |
255 | ||
5f50867b HM |
256 | static unsigned long tce_get_pSeriesLP(struct iommu_table *tbl, long tcenum) |
257 | { | |
258 | u64 rc; | |
259 | unsigned long tce_ret; | |
260 | ||
5f50867b HM |
261 | rc = plpar_tce_get((u64)tbl->it_index, (u64)tcenum << 12, &tce_ret); |
262 | ||
263 | if (rc && printk_ratelimit()) { | |
fe333321 IM |
264 | printk("tce_get_pSeriesLP: plpar_tce_get failed. rc=%lld\n", rc); |
265 | printk("\tindex = 0x%llx\n", (u64)tbl->it_index); | |
266 | printk("\ttcenum = 0x%llx\n", (u64)tcenum); | |
5f50867b HM |
267 | show_stack(current, (unsigned long *)__get_SP()); |
268 | } | |
269 | ||
270 | return tce_ret; | |
271 | } | |
272 | ||
bed59275 | 273 | #ifdef CONFIG_PCI |
1da177e4 LT |
274 | static void iommu_table_setparms(struct pci_controller *phb, |
275 | struct device_node *dn, | |
bc97ce95 | 276 | struct iommu_table *tbl) |
1da177e4 LT |
277 | { |
278 | struct device_node *node; | |
9938c474 NL |
279 | const unsigned long *basep; |
280 | const u32 *sizep; | |
1da177e4 | 281 | |
44ef3390 | 282 | node = phb->dn; |
1da177e4 | 283 | |
e2eb6392 SR |
284 | basep = of_get_property(node, "linux,tce-base", NULL); |
285 | sizep = of_get_property(node, "linux,tce-size", NULL); | |
1da177e4 LT |
286 | if (basep == NULL || sizep == NULL) { |
287 | printk(KERN_ERR "PCI_DMA: iommu_table_setparms: %s has " | |
288 | "missing tce entries !\n", dn->full_name); | |
289 | return; | |
290 | } | |
291 | ||
292 | tbl->it_base = (unsigned long)__va(*basep); | |
5f50867b | 293 | |
62a8bd6c | 294 | if (!is_kdump_kernel()) |
54622f10 | 295 | memset((void *)tbl->it_base, 0, *sizep); |
1da177e4 LT |
296 | |
297 | tbl->it_busno = phb->bus->number; | |
bc97ce95 | 298 | |
1da177e4 | 299 | /* Units of tce entries */ |
5d2efba6 | 300 | tbl->it_offset = phb->dma_window_base_cur >> IOMMU_PAGE_SHIFT; |
bc97ce95 | 301 | |
1da177e4 | 302 | /* Test if we are going over 2GB of DMA space */ |
3c2822cc OJ |
303 | if (phb->dma_window_base_cur + phb->dma_window_size > 0x80000000ul) { |
304 | udbg_printf("PCI_DMA: Unexpected number of IOAs under this PHB.\n"); | |
bc97ce95 | 305 | panic("PCI_DMA: Unexpected number of IOAs under this PHB.\n"); |
3c2822cc | 306 | } |
bc97ce95 | 307 | |
1da177e4 LT |
308 | phb->dma_window_base_cur += phb->dma_window_size; |
309 | ||
310 | /* Set the tce table size - measured in entries */ | |
5d2efba6 | 311 | tbl->it_size = phb->dma_window_size >> IOMMU_PAGE_SHIFT; |
1da177e4 LT |
312 | |
313 | tbl->it_index = 0; | |
314 | tbl->it_blocksize = 16; | |
315 | tbl->it_type = TCE_PCI; | |
316 | } | |
317 | ||
318 | /* | |
319 | * iommu_table_setparms_lpar | |
320 | * | |
321 | * Function: On pSeries LPAR systems, return TCE table info, given a pci bus. | |
1da177e4 LT |
322 | */ |
323 | static void iommu_table_setparms_lpar(struct pci_controller *phb, | |
324 | struct device_node *dn, | |
325 | struct iommu_table *tbl, | |
96188ce5 SR |
326 | const void *dma_window, |
327 | int bussubno) | |
1da177e4 | 328 | { |
4c76e0bc JK |
329 | unsigned long offset, size; |
330 | ||
96188ce5 | 331 | tbl->it_busno = bussubno; |
4c76e0bc | 332 | of_parse_dma_window(dn, dma_window, &tbl->it_index, &offset, &size); |
1da177e4 | 333 | |
1da177e4 | 334 | tbl->it_base = 0; |
1da177e4 LT |
335 | tbl->it_blocksize = 16; |
336 | tbl->it_type = TCE_PCI; | |
5d2efba6 LV |
337 | tbl->it_offset = offset >> IOMMU_PAGE_SHIFT; |
338 | tbl->it_size = size >> IOMMU_PAGE_SHIFT; | |
1da177e4 LT |
339 | } |
340 | ||
12d04eef | 341 | static void pci_dma_bus_setup_pSeries(struct pci_bus *bus) |
1da177e4 | 342 | { |
3c2822cc | 343 | struct device_node *dn; |
1da177e4 | 344 | struct iommu_table *tbl; |
3c2822cc OJ |
345 | struct device_node *isa_dn, *isa_dn_orig; |
346 | struct device_node *tmp; | |
347 | struct pci_dn *pci; | |
348 | int children; | |
1da177e4 | 349 | |
3c2822cc | 350 | dn = pci_bus_to_OF_node(bus); |
12d04eef | 351 | |
f7ebf352 | 352 | pr_debug("pci_dma_bus_setup_pSeries: setting up bus %s\n", dn->full_name); |
3c2822cc OJ |
353 | |
354 | if (bus->self) { | |
355 | /* This is not a root bus, any setup will be done for the | |
356 | * device-side of the bridge in iommu_dev_setup_pSeries(). | |
357 | */ | |
358 | return; | |
359 | } | |
12d04eef | 360 | pci = PCI_DN(dn); |
3c2822cc OJ |
361 | |
362 | /* Check if the ISA bus on the system is under | |
363 | * this PHB. | |
1da177e4 | 364 | */ |
3c2822cc | 365 | isa_dn = isa_dn_orig = of_find_node_by_type(NULL, "isa"); |
1da177e4 | 366 | |
3c2822cc OJ |
367 | while (isa_dn && isa_dn != dn) |
368 | isa_dn = isa_dn->parent; | |
369 | ||
370 | if (isa_dn_orig) | |
371 | of_node_put(isa_dn_orig); | |
1da177e4 | 372 | |
d3c58fb1 | 373 | /* Count number of direct PCI children of the PHB. */ |
3c2822cc | 374 | for (children = 0, tmp = dn->child; tmp; tmp = tmp->sibling) |
d3c58fb1 | 375 | children++; |
1da177e4 | 376 | |
f7ebf352 | 377 | pr_debug("Children: %d\n", children); |
1da177e4 | 378 | |
3c2822cc OJ |
379 | /* Calculate amount of DMA window per slot. Each window must be |
380 | * a power of two (due to pci_alloc_consistent requirements). | |
381 | * | |
382 | * Keep 256MB aside for PHBs with ISA. | |
383 | */ | |
1da177e4 | 384 | |
3c2822cc OJ |
385 | if (!isa_dn) { |
386 | /* No ISA/IDE - just set window size and return */ | |
387 | pci->phb->dma_window_size = 0x80000000ul; /* To be divided */ | |
388 | ||
389 | while (pci->phb->dma_window_size * children > 0x80000000ul) | |
390 | pci->phb->dma_window_size >>= 1; | |
f7ebf352 ME |
391 | pr_debug("No ISA/IDE, window size is 0x%lx\n", |
392 | pci->phb->dma_window_size); | |
3c2822cc OJ |
393 | pci->phb->dma_window_base_cur = 0; |
394 | ||
395 | return; | |
1da177e4 | 396 | } |
3c2822cc OJ |
397 | |
398 | /* If we have ISA, then we probably have an IDE | |
399 | * controller too. Allocate a 128MB table but | |
400 | * skip the first 128MB to avoid stepping on ISA | |
401 | * space. | |
402 | */ | |
403 | pci->phb->dma_window_size = 0x8000000ul; | |
404 | pci->phb->dma_window_base_cur = 0x8000000ul; | |
405 | ||
ca1588e7 AB |
406 | tbl = kmalloc_node(sizeof(struct iommu_table), GFP_KERNEL, |
407 | pci->phb->node); | |
3c2822cc OJ |
408 | |
409 | iommu_table_setparms(pci->phb, dn, tbl); | |
ca1588e7 | 410 | pci->iommu_table = iommu_init_table(tbl, pci->phb->node); |
3c2822cc OJ |
411 | |
412 | /* Divide the rest (1.75GB) among the children */ | |
413 | pci->phb->dma_window_size = 0x80000000ul; | |
414 | while (pci->phb->dma_window_size * children > 0x70000000ul) | |
415 | pci->phb->dma_window_size >>= 1; | |
416 | ||
f7ebf352 | 417 | pr_debug("ISA/IDE, window size is 0x%lx\n", pci->phb->dma_window_size); |
1da177e4 LT |
418 | } |
419 | ||
420 | ||
12d04eef | 421 | static void pci_dma_bus_setup_pSeriesLP(struct pci_bus *bus) |
1da177e4 LT |
422 | { |
423 | struct iommu_table *tbl; | |
424 | struct device_node *dn, *pdn; | |
1635317f | 425 | struct pci_dn *ppci; |
954a46e2 | 426 | const void *dma_window = NULL; |
1da177e4 | 427 | |
1da177e4 LT |
428 | dn = pci_bus_to_OF_node(bus); |
429 | ||
f7ebf352 ME |
430 | pr_debug("pci_dma_bus_setup_pSeriesLP: setting up bus %s\n", |
431 | dn->full_name); | |
12d04eef | 432 | |
1da177e4 LT |
433 | /* Find nearest ibm,dma-window, walking up the device tree */ |
434 | for (pdn = dn; pdn != NULL; pdn = pdn->parent) { | |
e2eb6392 | 435 | dma_window = of_get_property(pdn, "ibm,dma-window", NULL); |
1da177e4 LT |
436 | if (dma_window != NULL) |
437 | break; | |
438 | } | |
439 | ||
440 | if (dma_window == NULL) { | |
f7ebf352 | 441 | pr_debug(" no ibm,dma-window property !\n"); |
1da177e4 LT |
442 | return; |
443 | } | |
444 | ||
e07102db | 445 | ppci = PCI_DN(pdn); |
12d04eef | 446 | |
f7ebf352 ME |
447 | pr_debug(" parent is %s, iommu_table: 0x%p\n", |
448 | pdn->full_name, ppci->iommu_table); | |
12d04eef | 449 | |
1635317f | 450 | if (!ppci->iommu_table) { |
ca1588e7 AB |
451 | tbl = kmalloc_node(sizeof(struct iommu_table), GFP_KERNEL, |
452 | ppci->phb->node); | |
96188ce5 SR |
453 | iommu_table_setparms_lpar(ppci->phb, pdn, tbl, dma_window, |
454 | bus->number); | |
ca1588e7 | 455 | ppci->iommu_table = iommu_init_table(tbl, ppci->phb->node); |
f7ebf352 | 456 | pr_debug(" created table: %p\n", ppci->iommu_table); |
1da177e4 LT |
457 | } |
458 | ||
459 | if (pdn != dn) | |
1635317f | 460 | PCI_DN(dn)->iommu_table = ppci->iommu_table; |
1da177e4 LT |
461 | } |
462 | ||
463 | ||
12d04eef | 464 | static void pci_dma_dev_setup_pSeries(struct pci_dev *dev) |
1da177e4 | 465 | { |
12d04eef | 466 | struct device_node *dn; |
3c2822cc | 467 | struct iommu_table *tbl; |
1da177e4 | 468 | |
f7ebf352 | 469 | pr_debug("pci_dma_dev_setup_pSeries: %s\n", pci_name(dev)); |
1da177e4 | 470 | |
12d04eef | 471 | dn = dev->dev.archdata.of_node; |
1da177e4 | 472 | |
3c2822cc OJ |
473 | /* If we're the direct child of a root bus, then we need to allocate |
474 | * an iommu table ourselves. The bus setup code should have setup | |
475 | * the window sizes already. | |
476 | */ | |
477 | if (!dev->bus->self) { | |
12d04eef BH |
478 | struct pci_controller *phb = PCI_DN(dn)->phb; |
479 | ||
f7ebf352 | 480 | pr_debug(" --> first child, no bridge. Allocating iommu table.\n"); |
ca1588e7 | 481 | tbl = kmalloc_node(sizeof(struct iommu_table), GFP_KERNEL, |
12d04eef BH |
482 | phb->node); |
483 | iommu_table_setparms(phb, dn, tbl); | |
77319254 LV |
484 | PCI_DN(dn)->iommu_table = iommu_init_table(tbl, phb->node); |
485 | dev->dev.archdata.dma_data = PCI_DN(dn)->iommu_table; | |
3c2822cc OJ |
486 | return; |
487 | } | |
488 | ||
489 | /* If this device is further down the bus tree, search upwards until | |
490 | * an already allocated iommu table is found and use that. | |
491 | */ | |
492 | ||
e07102db | 493 | while (dn && PCI_DN(dn) && PCI_DN(dn)->iommu_table == NULL) |
1da177e4 LT |
494 | dn = dn->parent; |
495 | ||
12d04eef BH |
496 | if (dn && PCI_DN(dn)) |
497 | dev->dev.archdata.dma_data = PCI_DN(dn)->iommu_table; | |
498 | else | |
499 | printk(KERN_WARNING "iommu: Device %s has no iommu table\n", | |
500 | pci_name(dev)); | |
1da177e4 LT |
501 | } |
502 | ||
12d04eef | 503 | static void pci_dma_dev_setup_pSeriesLP(struct pci_dev *dev) |
1da177e4 LT |
504 | { |
505 | struct device_node *pdn, *dn; | |
506 | struct iommu_table *tbl; | |
954a46e2 | 507 | const void *dma_window = NULL; |
1635317f | 508 | struct pci_dn *pci; |
1da177e4 | 509 | |
f7ebf352 | 510 | pr_debug("pci_dma_dev_setup_pSeriesLP: %s\n", pci_name(dev)); |
12d04eef | 511 | |
1da177e4 LT |
512 | /* dev setup for LPAR is a little tricky, since the device tree might |
513 | * contain the dma-window properties per-device and not neccesarily | |
514 | * for the bus. So we need to search upwards in the tree until we | |
515 | * either hit a dma-window property, OR find a parent with a table | |
516 | * already allocated. | |
517 | */ | |
518 | dn = pci_device_to_OF_node(dev); | |
f7ebf352 | 519 | pr_debug(" node is %s\n", dn->full_name); |
5d2efba6 | 520 | |
e07102db | 521 | for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->iommu_table; |
1635317f | 522 | pdn = pdn->parent) { |
e2eb6392 | 523 | dma_window = of_get_property(pdn, "ibm,dma-window", NULL); |
1da177e4 LT |
524 | if (dma_window) |
525 | break; | |
526 | } | |
527 | ||
650f7b3b LV |
528 | if (!pdn || !PCI_DN(pdn)) { |
529 | printk(KERN_WARNING "pci_dma_dev_setup_pSeriesLP: " | |
530 | "no DMA window found for pci dev=%s dn=%s\n", | |
531 | pci_name(dev), dn? dn->full_name : "<null>"); | |
532 | return; | |
533 | } | |
f7ebf352 | 534 | pr_debug(" parent is %s\n", pdn->full_name); |
12d04eef | 535 | |
1da177e4 LT |
536 | /* Check for parent == NULL so we don't try to setup the empty EADS |
537 | * slots on POWER4 machines. | |
538 | */ | |
539 | if (dma_window == NULL || pdn->parent == NULL) { | |
f7ebf352 | 540 | pr_debug(" no dma window for device, linking to parent\n"); |
12d04eef | 541 | dev->dev.archdata.dma_data = PCI_DN(pdn)->iommu_table; |
1da177e4 | 542 | return; |
1da177e4 LT |
543 | } |
544 | ||
e07102db | 545 | pci = PCI_DN(pdn); |
1635317f | 546 | if (!pci->iommu_table) { |
ca1588e7 AB |
547 | tbl = kmalloc_node(sizeof(struct iommu_table), GFP_KERNEL, |
548 | pci->phb->node); | |
96188ce5 SR |
549 | iommu_table_setparms_lpar(pci->phb, pdn, tbl, dma_window, |
550 | pci->phb->bus->number); | |
ca1588e7 | 551 | pci->iommu_table = iommu_init_table(tbl, pci->phb->node); |
f7ebf352 | 552 | pr_debug(" created table: %p\n", pci->iommu_table); |
de113217 | 553 | } else { |
f7ebf352 | 554 | pr_debug(" found DMA window, table: %p\n", pci->iommu_table); |
1da177e4 LT |
555 | } |
556 | ||
12d04eef | 557 | dev->dev.archdata.dma_data = pci->iommu_table; |
1da177e4 | 558 | } |
bed59275 SR |
559 | #else /* CONFIG_PCI */ |
560 | #define pci_dma_bus_setup_pSeries NULL | |
561 | #define pci_dma_dev_setup_pSeries NULL | |
562 | #define pci_dma_bus_setup_pSeriesLP NULL | |
563 | #define pci_dma_dev_setup_pSeriesLP NULL | |
564 | #endif /* !CONFIG_PCI */ | |
565 | ||
566 | static int iommu_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *node) | |
567 | { | |
568 | int err = NOTIFY_OK; | |
569 | struct device_node *np = node; | |
570 | struct pci_dn *pci = PCI_DN(np); | |
571 | ||
572 | switch (action) { | |
573 | case PSERIES_RECONFIG_REMOVE: | |
574 | if (pci && pci->iommu_table && | |
e2eb6392 | 575 | of_get_property(np, "ibm,dma-window", NULL)) |
68d315f5 | 576 | iommu_free_table(pci->iommu_table, np->full_name); |
bed59275 SR |
577 | break; |
578 | default: | |
579 | err = NOTIFY_DONE; | |
580 | break; | |
581 | } | |
582 | return err; | |
583 | } | |
584 | ||
585 | static struct notifier_block iommu_reconfig_nb = { | |
586 | .notifier_call = iommu_reconfig_notifier, | |
587 | }; | |
1da177e4 | 588 | |
1da177e4 LT |
589 | /* These are called very early. */ |
590 | void iommu_init_early_pSeries(void) | |
591 | { | |
e2eb6392 | 592 | if (of_chosen && of_get_property(of_chosen, "linux,iommu-off", NULL)) { |
1da177e4 | 593 | /* Direct I/O, IOMMU off */ |
12d04eef BH |
594 | ppc_md.pci_dma_dev_setup = NULL; |
595 | ppc_md.pci_dma_bus_setup = NULL; | |
98747770 | 596 | set_pci_dma_ops(&dma_direct_ops); |
1da177e4 LT |
597 | return; |
598 | } | |
599 | ||
57cfb814 | 600 | if (firmware_has_feature(FW_FEATURE_LPAR)) { |
1ababe11 | 601 | if (firmware_has_feature(FW_FEATURE_MULTITCE)) { |
1da177e4 LT |
602 | ppc_md.tce_build = tce_buildmulti_pSeriesLP; |
603 | ppc_md.tce_free = tce_freemulti_pSeriesLP; | |
604 | } else { | |
605 | ppc_md.tce_build = tce_build_pSeriesLP; | |
606 | ppc_md.tce_free = tce_free_pSeriesLP; | |
607 | } | |
5f50867b | 608 | ppc_md.tce_get = tce_get_pSeriesLP; |
12d04eef BH |
609 | ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_pSeriesLP; |
610 | ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_pSeriesLP; | |
1da177e4 LT |
611 | } else { |
612 | ppc_md.tce_build = tce_build_pSeries; | |
613 | ppc_md.tce_free = tce_free_pSeries; | |
5f50867b | 614 | ppc_md.tce_get = tce_get_pseries; |
12d04eef BH |
615 | ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_pSeries; |
616 | ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_pSeries; | |
1da177e4 LT |
617 | } |
618 | ||
619 | ||
620 | pSeries_reconfig_notifier_register(&iommu_reconfig_nb); | |
621 | ||
98747770 | 622 | set_pci_dma_ops(&dma_iommu_ops); |
1da177e4 LT |
623 | } |
624 |