Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
033ef338 | 2 | * 64-bit pSeries and RS/6000 setup code. |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 1995 Linus Torvalds | |
5 | * Adapted from 'alpha' version by Gary Thomas | |
6 | * Modified by Cort Dougan (cort@cs.nmt.edu) | |
7 | * Modified by PPC64 Team, IBM Corp | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * as published by the Free Software Foundation; either version | |
12 | * 2 of the License, or (at your option) any later version. | |
13 | */ | |
14 | ||
15 | /* | |
16 | * bootup setup stuff.. | |
17 | */ | |
18 | ||
19 | #undef DEBUG | |
20 | ||
21 | #include <linux/config.h> | |
62d60e9f | 22 | #include <linux/cpu.h> |
1da177e4 LT |
23 | #include <linux/errno.h> |
24 | #include <linux/sched.h> | |
25 | #include <linux/kernel.h> | |
26 | #include <linux/mm.h> | |
27 | #include <linux/stddef.h> | |
28 | #include <linux/unistd.h> | |
29 | #include <linux/slab.h> | |
30 | #include <linux/user.h> | |
31 | #include <linux/a.out.h> | |
32 | #include <linux/tty.h> | |
33 | #include <linux/major.h> | |
34 | #include <linux/interrupt.h> | |
35 | #include <linux/reboot.h> | |
36 | #include <linux/init.h> | |
37 | #include <linux/ioport.h> | |
38 | #include <linux/console.h> | |
39 | #include <linux/pci.h> | |
cebb2b15 | 40 | #include <linux/utsname.h> |
1da177e4 LT |
41 | #include <linux/adb.h> |
42 | #include <linux/module.h> | |
43 | #include <linux/delay.h> | |
44 | #include <linux/irq.h> | |
45 | #include <linux/seq_file.h> | |
46 | #include <linux/root_dev.h> | |
47 | ||
48 | #include <asm/mmu.h> | |
49 | #include <asm/processor.h> | |
50 | #include <asm/io.h> | |
51 | #include <asm/pgtable.h> | |
52 | #include <asm/prom.h> | |
53 | #include <asm/rtas.h> | |
54 | #include <asm/pci-bridge.h> | |
55 | #include <asm/iommu.h> | |
56 | #include <asm/dma.h> | |
57 | #include <asm/machdep.h> | |
58 | #include <asm/irq.h> | |
3d1229d6 | 59 | #include <asm/kexec.h> |
1da177e4 LT |
60 | #include <asm/time.h> |
61 | #include <asm/nvram.h> | |
007e8f51 | 62 | #include "xics.h" |
180a3362 | 63 | #include <asm/pmc.h> |
bbeb3f4c | 64 | #include <asm/mpic.h> |
d387899f | 65 | #include <asm/ppc-pci.h> |
69a80d3f PM |
66 | #include <asm/i8259.h> |
67 | #include <asm/udbg.h> | |
2249ca9d | 68 | #include <asm/smp.h> |
1da177e4 | 69 | |
a1218720 | 70 | #include "plpar_wrappers.h" |
c902be71 | 71 | #include "ras.h" |
1965746b | 72 | #include "firmware.h" |
a1218720 | 73 | |
1da177e4 LT |
74 | #ifdef DEBUG |
75 | #define DBG(fmt...) udbg_printf(fmt) | |
76 | #else | |
77 | #define DBG(fmt...) | |
78 | #endif | |
79 | ||
1da177e4 | 80 | extern void find_udbg_vterm(void); |
1da177e4 LT |
81 | |
82 | int fwnmi_active; /* TRUE if an FWNMI handler is present */ | |
83 | ||
143a1dec PM |
84 | static void pseries_shared_idle(void); |
85 | static void pseries_dedicated_idle(void); | |
62d60e9f | 86 | |
1da177e4 LT |
87 | struct mpic *pSeries_mpic; |
88 | ||
8446196a | 89 | static void pSeries_show_cpuinfo(struct seq_file *m) |
1da177e4 LT |
90 | { |
91 | struct device_node *root; | |
92 | const char *model = ""; | |
93 | ||
94 | root = of_find_node_by_path("/"); | |
95 | if (root) | |
96 | model = get_property(root, "model", NULL); | |
97 | seq_printf(m, "machine\t\t: CHRP %s\n", model); | |
98 | of_node_put(root); | |
99 | } | |
100 | ||
101 | /* Initialize firmware assisted non-maskable interrupts if | |
102 | * the firmware supports this feature. | |
1da177e4 LT |
103 | */ |
104 | static void __init fwnmi_init(void) | |
105 | { | |
8c4f1f29 ME |
106 | unsigned long system_reset_addr, machine_check_addr; |
107 | ||
1da177e4 LT |
108 | int ibm_nmi_register = rtas_token("ibm,nmi-register"); |
109 | if (ibm_nmi_register == RTAS_UNKNOWN_SERVICE) | |
110 | return; | |
8c4f1f29 ME |
111 | |
112 | /* If the kernel's not linked at zero we point the firmware at low | |
113 | * addresses anyway, and use a trampoline to get to the real code. */ | |
114 | system_reset_addr = __pa(system_reset_fwnmi) - PHYSICAL_START; | |
115 | machine_check_addr = __pa(machine_check_fwnmi) - PHYSICAL_START; | |
116 | ||
117 | if (0 == rtas_call(ibm_nmi_register, 2, 1, NULL, system_reset_addr, | |
118 | machine_check_addr)) | |
1da177e4 LT |
119 | fwnmi_active = 1; |
120 | } | |
121 | ||
1da177e4 LT |
122 | static void __init pSeries_init_mpic(void) |
123 | { | |
124 | unsigned int *addrp; | |
125 | struct device_node *np; | |
f9bd170a | 126 | unsigned long intack = 0; |
1da177e4 LT |
127 | |
128 | /* All ISUs are setup, complete initialization */ | |
129 | mpic_init(pSeries_mpic); | |
130 | ||
131 | /* Check what kind of cascade ACK we have */ | |
132 | if (!(np = of_find_node_by_name(NULL, "pci")) | |
133 | || !(addrp = (unsigned int *) | |
134 | get_property(np, "8259-interrupt-acknowledge", NULL))) | |
135 | printk(KERN_ERR "Cannot find pci to get ack address\n"); | |
136 | else | |
f9bd170a | 137 | intack = addrp[prom_n_addr_cells(np)-1]; |
1da177e4 LT |
138 | of_node_put(np); |
139 | ||
140 | /* Setup the legacy interrupts & controller */ | |
f9bd170a | 141 | i8259_init(intack, 0); |
1da177e4 LT |
142 | |
143 | /* Hook cascade to mpic */ | |
f9bd170a | 144 | mpic_setup_cascade(NUM_ISA_INTERRUPTS, i8259_irq_cascade, NULL); |
1da177e4 LT |
145 | } |
146 | ||
147 | static void __init pSeries_setup_mpic(void) | |
148 | { | |
149 | unsigned int *opprop; | |
150 | unsigned long openpic_addr = 0; | |
151 | unsigned char senses[NR_IRQS - NUM_ISA_INTERRUPTS]; | |
152 | struct device_node *root; | |
153 | int irq_count; | |
154 | ||
155 | /* Find the Open PIC if present */ | |
156 | root = of_find_node_by_path("/"); | |
157 | opprop = (unsigned int *) get_property(root, "platform-open-pic", NULL); | |
158 | if (opprop != 0) { | |
159 | int n = prom_n_addr_cells(root); | |
160 | ||
161 | for (openpic_addr = 0; n > 0; --n) | |
162 | openpic_addr = (openpic_addr << 32) + *opprop++; | |
163 | printk(KERN_DEBUG "OpenPIC addr: %lx\n", openpic_addr); | |
164 | } | |
165 | of_node_put(root); | |
166 | ||
167 | BUG_ON(openpic_addr == 0); | |
168 | ||
169 | /* Get the sense values from OF */ | |
170 | prom_get_irq_senses(senses, NUM_ISA_INTERRUPTS, NR_IRQS); | |
171 | ||
172 | /* Setup the openpic driver */ | |
173 | irq_count = NR_IRQS - NUM_ISA_INTERRUPTS - 4; /* leave room for IPIs */ | |
174 | pSeries_mpic = mpic_alloc(openpic_addr, MPIC_PRIMARY, | |
175 | 16, 16, irq_count, /* isu size, irq offset, irq count */ | |
176 | NR_IRQS - 4, /* ipi offset */ | |
177 | senses, irq_count, /* sense & sense size */ | |
178 | " MPIC "); | |
179 | } | |
180 | ||
180a3362 ME |
181 | static void pseries_lpar_enable_pmcs(void) |
182 | { | |
183 | unsigned long set, reset; | |
184 | ||
185 | power4_enable_pmcs(); | |
186 | ||
187 | set = 1UL << 63; | |
188 | reset = 0; | |
189 | plpar_hcall_norets(H_PERFMON, set, reset); | |
190 | ||
191 | /* instruct hypervisor to maintain PMCs */ | |
192 | if (firmware_has_feature(FW_FEATURE_SPLPAR)) | |
3356bb9f | 193 | get_lppaca()->pmcregs_in_use = 1; |
180a3362 ME |
194 | } |
195 | ||
1da177e4 LT |
196 | static void __init pSeries_setup_arch(void) |
197 | { | |
198 | /* Fixup ppc_md depending on the type of interrupt controller */ | |
199 | if (ppc64_interrupt_controller == IC_OPEN_PIC) { | |
fce0d574 | 200 | ppc_md.init_IRQ = pSeries_init_mpic; |
1da177e4 LT |
201 | ppc_md.get_irq = mpic_get_irq; |
202 | /* Allocate the mpic now, so that find_and_init_phbs() can | |
203 | * fill the ISUs */ | |
204 | pSeries_setup_mpic(); | |
205 | } else { | |
206 | ppc_md.init_IRQ = xics_init_IRQ; | |
207 | ppc_md.get_irq = xics_get_irq; | |
208 | } | |
209 | ||
210 | #ifdef CONFIG_SMP | |
211 | smp_init_pSeries(); | |
212 | #endif | |
213 | /* openpic global configuration register (64-bit format). */ | |
214 | /* openpic Interrupt Source Unit pointer (64-bit format). */ | |
215 | /* python0 facility area (mmio) (64-bit format) REAL address. */ | |
216 | ||
217 | /* init to some ~sane value until calibrate_delay() runs */ | |
218 | loops_per_jiffy = 50000000; | |
219 | ||
220 | if (ROOT_DEV == 0) { | |
221 | printk("No ramdisk, default root is /dev/sda2\n"); | |
222 | ROOT_DEV = Root_SDA2; | |
223 | } | |
224 | ||
225 | fwnmi_init(); | |
226 | ||
227 | /* Find and initialize PCI host bridges */ | |
228 | init_pci_config_tokens(); | |
1da177e4 | 229 | find_and_init_phbs(); |
0160f53e | 230 | eeh_init(); |
1da177e4 | 231 | |
1da177e4 LT |
232 | pSeries_nvram_init(); |
233 | ||
62d60e9f | 234 | /* Choose an idle loop */ |
1ababe11 | 235 | if (firmware_has_feature(FW_FEATURE_SPLPAR)) { |
8d15a3e5 | 236 | vpa_init(boot_cpuid); |
3356bb9f | 237 | if (get_lppaca()->shared_proc) { |
62d60e9f | 238 | printk(KERN_INFO "Using shared processor idle loop\n"); |
050a0938 | 239 | ppc_md.idle_loop = pseries_shared_idle; |
62d60e9f ME |
240 | } else { |
241 | printk(KERN_INFO "Using dedicated idle loop\n"); | |
050a0938 | 242 | ppc_md.idle_loop = pseries_dedicated_idle; |
62d60e9f ME |
243 | } |
244 | } else { | |
245 | printk(KERN_INFO "Using default idle loop\n"); | |
246 | ppc_md.idle_loop = default_idle; | |
247 | } | |
180a3362 | 248 | |
799d6046 | 249 | if (platform_is_lpar()) |
180a3362 ME |
250 | ppc_md.enable_pmcs = pseries_lpar_enable_pmcs; |
251 | else | |
252 | ppc_md.enable_pmcs = power4_enable_pmcs; | |
1da177e4 LT |
253 | } |
254 | ||
255 | static int __init pSeries_init_panel(void) | |
256 | { | |
257 | /* Manually leave the kernel version on the panel. */ | |
258 | ppc_md.progress("Linux ppc64\n", 0); | |
cebb2b15 | 259 | ppc_md.progress(system_utsname.version, 0); |
1da177e4 LT |
260 | |
261 | return 0; | |
262 | } | |
263 | arch_initcall(pSeries_init_panel); | |
264 | ||
1da177e4 LT |
265 | static void __init pSeries_discover_pic(void) |
266 | { | |
267 | struct device_node *np; | |
268 | char *typep; | |
269 | ||
270 | /* | |
271 | * Setup interrupt mapping options that are needed for finish_device_tree | |
272 | * to properly parse the OF interrupt tree & do the virtual irq mapping | |
273 | */ | |
274 | __irq_offset_value = NUM_ISA_INTERRUPTS; | |
275 | ppc64_interrupt_controller = IC_INVALID; | |
276 | for (np = NULL; (np = of_find_node_by_name(np, "interrupt-controller"));) { | |
277 | typep = (char *)get_property(np, "compatible", NULL); | |
9da5cad6 | 278 | if (strstr(typep, "open-pic")) { |
1da177e4 | 279 | ppc64_interrupt_controller = IC_OPEN_PIC; |
9da5cad6 HM |
280 | break; |
281 | } else if (strstr(typep, "ppc-xicp")) { | |
1da177e4 | 282 | ppc64_interrupt_controller = IC_PPC_XIC; |
9da5cad6 HM |
283 | break; |
284 | } | |
1da177e4 | 285 | } |
9da5cad6 HM |
286 | if (ppc64_interrupt_controller == IC_INVALID) |
287 | printk("pSeries_discover_pic: failed to recognize" | |
288 | " interrupt-controller\n"); | |
289 | ||
1da177e4 LT |
290 | } |
291 | ||
292 | static void pSeries_mach_cpu_die(void) | |
293 | { | |
294 | local_irq_disable(); | |
295 | idle_task_exit(); | |
296 | /* Some hardware requires clearing the CPPR, while other hardware does not | |
297 | * it is safe either way | |
298 | */ | |
299 | pSeriesLP_cppr_info(0, 0); | |
300 | rtas_stop_self(); | |
301 | /* Should never get here... */ | |
302 | BUG(); | |
303 | for(;;); | |
304 | } | |
305 | ||
cab0af98 ME |
306 | static int pseries_set_dabr(unsigned long dabr) |
307 | { | |
76032de8 | 308 | return plpar_hcall_norets(H_SET_DABR, dabr); |
cab0af98 ME |
309 | } |
310 | ||
76032de8 ME |
311 | static int pseries_set_xdabr(unsigned long dabr) |
312 | { | |
313 | /* We want to catch accesses from kernel and userspace */ | |
314 | return plpar_hcall_norets(H_SET_XDABR, dabr, | |
315 | H_DABRX_KERNEL | H_DABRX_USER); | |
316 | } | |
1da177e4 LT |
317 | |
318 | /* | |
319 | * Early initialization. Relocation is on but do not reference unbolted pages | |
320 | */ | |
321 | static void __init pSeries_init_early(void) | |
322 | { | |
1da177e4 LT |
323 | DBG(" -> pSeries_init_early()\n"); |
324 | ||
325 | fw_feature_init(); | |
326 | ||
799d6046 | 327 | if (platform_is_lpar()) |
1da177e4 | 328 | hpte_init_lpar(); |
41520244 | 329 | else |
1da177e4 | 330 | hpte_init_native(); |
1da177e4 | 331 | |
799d6046 | 332 | if (platform_is_lpar()) |
1da177e4 | 333 | find_udbg_vterm(); |
1da177e4 | 334 | |
76032de8 | 335 | if (firmware_has_feature(FW_FEATURE_DABR)) |
cab0af98 | 336 | ppc_md.set_dabr = pseries_set_dabr; |
76032de8 ME |
337 | else if (firmware_has_feature(FW_FEATURE_XDABR)) |
338 | ppc_md.set_dabr = pseries_set_xdabr; | |
1da177e4 LT |
339 | |
340 | iommu_init_early_pSeries(); | |
341 | ||
342 | pSeries_discover_pic(); | |
343 | ||
344 | DBG(" <- pSeries_init_early()\n"); | |
345 | } | |
346 | ||
347 | ||
1da177e4 LT |
348 | static int pSeries_check_legacy_ioport(unsigned int baseport) |
349 | { | |
350 | struct device_node *np; | |
351 | ||
352 | #define I8042_DATA_REG 0x60 | |
353 | #define FDC_BASE 0x3f0 | |
354 | ||
355 | ||
356 | switch(baseport) { | |
357 | case I8042_DATA_REG: | |
358 | np = of_find_node_by_type(NULL, "8042"); | |
359 | if (np == NULL) | |
360 | return -ENODEV; | |
361 | of_node_put(np); | |
362 | break; | |
363 | case FDC_BASE: | |
364 | np = of_find_node_by_type(NULL, "fdc"); | |
365 | if (np == NULL) | |
366 | return -ENODEV; | |
367 | of_node_put(np); | |
368 | break; | |
369 | } | |
370 | return 0; | |
371 | } | |
372 | ||
373 | /* | |
374 | * Called very early, MMU is off, device-tree isn't unflattened | |
375 | */ | |
376 | extern struct machdep_calls pSeries_md; | |
377 | ||
378 | static int __init pSeries_probe(int platform) | |
379 | { | |
380 | if (platform != PLATFORM_PSERIES && | |
381 | platform != PLATFORM_PSERIES_LPAR) | |
382 | return 0; | |
383 | ||
384 | /* if we have some ppc_md fixups for LPAR to do, do | |
385 | * it here ... | |
386 | */ | |
387 | ||
388 | return 1; | |
389 | } | |
390 | ||
c66d5dd6 ME |
391 | DECLARE_PER_CPU(unsigned long, smt_snooze_delay); |
392 | ||
050a0938 AB |
393 | static inline void dedicated_idle_sleep(unsigned int cpu) |
394 | { | |
3356bb9f | 395 | struct lppaca *plppaca = &lppaca[cpu ^ 1]; |
050a0938 AB |
396 | |
397 | /* Only sleep if the other thread is not idle */ | |
3356bb9f | 398 | if (!(plppaca->idle)) { |
050a0938 AB |
399 | local_irq_disable(); |
400 | ||
401 | /* | |
402 | * We are about to sleep the thread and so wont be polling any | |
403 | * more. | |
404 | */ | |
405 | clear_thread_flag(TIF_POLLING_NRFLAG); | |
64c7c8f8 | 406 | smp_mb__after_clear_bit(); |
050a0938 AB |
407 | |
408 | /* | |
409 | * SMT dynamic mode. Cede will result in this thread going | |
410 | * dormant, if the partner thread is still doing work. Thread | |
411 | * wakes up if partner goes idle, an interrupt is presented, or | |
412 | * a prod occurs. Returning from the cede enables external | |
413 | * interrupts. | |
414 | */ | |
415 | if (!need_resched()) | |
416 | cede_processor(); | |
417 | else | |
418 | local_irq_enable(); | |
64c7c8f8 | 419 | set_thread_flag(TIF_POLLING_NRFLAG); |
050a0938 AB |
420 | } else { |
421 | /* | |
422 | * Give the HV an opportunity at the processor, since we are | |
423 | * not doing any work. | |
424 | */ | |
425 | poll_pending(); | |
426 | } | |
427 | } | |
428 | ||
143a1dec PM |
429 | static void pseries_dedicated_idle(void) |
430 | { | |
050a0938 | 431 | unsigned int cpu = smp_processor_id(); |
c66d5dd6 ME |
432 | unsigned long start_snooze; |
433 | unsigned long *smt_snooze_delay = &__get_cpu_var(smt_snooze_delay); | |
64c7c8f8 | 434 | set_thread_flag(TIF_POLLING_NRFLAG); |
c66d5dd6 ME |
435 | |
436 | while (1) { | |
437 | /* | |
438 | * Indicate to the HV that we are idle. Now would be | |
439 | * a good time to find other work to dispatch. | |
440 | */ | |
3356bb9f | 441 | get_lppaca()->idle = 1; |
c66d5dd6 | 442 | |
64c7c8f8 | 443 | if (!need_resched()) { |
6146eed1 | 444 | start_snooze = get_tb() + |
c66d5dd6 | 445 | *smt_snooze_delay * tb_ticks_per_usec; |
050a0938 | 446 | |
c66d5dd6 | 447 | while (!need_resched() && !cpu_is_offline(cpu)) { |
050a0938 AB |
448 | ppc64_runlatch_off(); |
449 | ||
c66d5dd6 ME |
450 | /* |
451 | * Go into low thread priority and possibly | |
452 | * low power mode. | |
453 | */ | |
454 | HMT_low(); | |
455 | HMT_very_low(); | |
456 | ||
050a0938 | 457 | if (*smt_snooze_delay != 0 && |
6146eed1 | 458 | get_tb() > start_snooze) { |
050a0938 AB |
459 | HMT_medium(); |
460 | dedicated_idle_sleep(cpu); | |
c66d5dd6 | 461 | } |
050a0938 | 462 | |
c66d5dd6 ME |
463 | } |
464 | ||
050a0938 | 465 | HMT_medium(); |
c66d5dd6 ME |
466 | } |
467 | ||
3356bb9f | 468 | get_lppaca()->idle = 0; |
050a0938 AB |
469 | ppc64_runlatch_on(); |
470 | ||
5bfb5d69 | 471 | preempt_enable_no_resched(); |
c66d5dd6 | 472 | schedule(); |
5bfb5d69 | 473 | preempt_disable(); |
050a0938 | 474 | |
c66d5dd6 ME |
475 | if (cpu_is_offline(cpu) && system_state == SYSTEM_RUNNING) |
476 | cpu_die(); | |
477 | } | |
c66d5dd6 ME |
478 | } |
479 | ||
143a1dec | 480 | static void pseries_shared_idle(void) |
c66d5dd6 | 481 | { |
c66d5dd6 ME |
482 | unsigned int cpu = smp_processor_id(); |
483 | ||
484 | while (1) { | |
485 | /* | |
486 | * Indicate to the HV that we are idle. Now would be | |
487 | * a good time to find other work to dispatch. | |
488 | */ | |
3356bb9f | 489 | get_lppaca()->idle = 1; |
c66d5dd6 ME |
490 | |
491 | while (!need_resched() && !cpu_is_offline(cpu)) { | |
492 | local_irq_disable(); | |
050a0938 | 493 | ppc64_runlatch_off(); |
c66d5dd6 ME |
494 | |
495 | /* | |
496 | * Yield the processor to the hypervisor. We return if | |
497 | * an external interrupt occurs (which are driven prior | |
498 | * to returning here) or if a prod occurs from another | |
499 | * processor. When returning here, external interrupts | |
500 | * are enabled. | |
501 | * | |
502 | * Check need_resched() again with interrupts disabled | |
503 | * to avoid a race. | |
504 | */ | |
505 | if (!need_resched()) | |
506 | cede_processor(); | |
507 | else | |
508 | local_irq_enable(); | |
050a0938 AB |
509 | |
510 | HMT_medium(); | |
c66d5dd6 ME |
511 | } |
512 | ||
3356bb9f | 513 | get_lppaca()->idle = 0; |
050a0938 AB |
514 | ppc64_runlatch_on(); |
515 | ||
5bfb5d69 | 516 | preempt_enable_no_resched(); |
c66d5dd6 | 517 | schedule(); |
5bfb5d69 | 518 | preempt_disable(); |
050a0938 AB |
519 | |
520 | if (cpu_is_offline(cpu) && system_state == SYSTEM_RUNNING) | |
c66d5dd6 ME |
521 | cpu_die(); |
522 | } | |
c66d5dd6 ME |
523 | } |
524 | ||
4267292b PM |
525 | static int pSeries_pci_probe_mode(struct pci_bus *bus) |
526 | { | |
799d6046 | 527 | if (platform_is_lpar()) |
4267292b PM |
528 | return PCI_PROBE_DEVTREE; |
529 | return PCI_PROBE_NORMAL; | |
530 | } | |
531 | ||
c5e24354 ME |
532 | #ifdef CONFIG_KEXEC |
533 | static void pseries_kexec_cpu_down(int crash_shutdown, int secondary) | |
534 | { | |
535 | /* Don't risk a hypervisor call if we're crashing */ | |
4dc43256 | 536 | if (firmware_has_feature(FW_FEATURE_SPLPAR) && !crash_shutdown) { |
3356bb9f | 537 | unsigned long vpa = __pa(get_lppaca()); |
c5e24354 ME |
538 | |
539 | if (unregister_vpa(hard_smp_processor_id(), vpa)) { | |
540 | printk("VPA deregistration of cpu %u (hw_cpu_id %d) " | |
541 | "failed\n", smp_processor_id(), | |
542 | hard_smp_processor_id()); | |
543 | } | |
544 | } | |
545 | ||
546 | if (ppc64_interrupt_controller == IC_OPEN_PIC) | |
547 | mpic_teardown_this_cpu(secondary); | |
548 | else | |
549 | xics_teardown_cpu(secondary); | |
550 | } | |
551 | #endif | |
552 | ||
1da177e4 LT |
553 | struct machdep_calls __initdata pSeries_md = { |
554 | .probe = pSeries_probe, | |
555 | .setup_arch = pSeries_setup_arch, | |
556 | .init_early = pSeries_init_early, | |
0dd194d0 | 557 | .show_cpuinfo = pSeries_show_cpuinfo, |
1da177e4 LT |
558 | .log_error = pSeries_log_error, |
559 | .pcibios_fixup = pSeries_final_fixup, | |
4267292b | 560 | .pci_probe_mode = pSeries_pci_probe_mode, |
dad32bbf | 561 | .irq_bus_setup = pSeries_irq_bus_setup, |
f4fcbbe9 PM |
562 | .restart = rtas_restart, |
563 | .power_off = rtas_power_off, | |
564 | .halt = rtas_halt, | |
1da177e4 LT |
565 | .panic = rtas_os_term, |
566 | .cpu_die = pSeries_mach_cpu_die, | |
773bf9c4 AB |
567 | .get_boot_time = rtas_get_boot_time, |
568 | .get_rtc_time = rtas_get_rtc_time, | |
569 | .set_rtc_time = rtas_set_rtc_time, | |
10f7e7c1 | 570 | .calibrate_decr = generic_calibrate_decr, |
6566c6f1 | 571 | .progress = rtas_progress, |
1da177e4 LT |
572 | .check_legacy_ioport = pSeries_check_legacy_ioport, |
573 | .system_reset_exception = pSeries_system_reset_exception, | |
574 | .machine_check_exception = pSeries_machine_check_exception, | |
c5e24354 ME |
575 | #ifdef CONFIG_KEXEC |
576 | .kexec_cpu_down = pseries_kexec_cpu_down, | |
3d1229d6 ME |
577 | .machine_kexec = default_machine_kexec, |
578 | .machine_kexec_prepare = default_machine_kexec_prepare, | |
cc532915 | 579 | .machine_crash_shutdown = default_machine_crash_shutdown, |
c5e24354 | 580 | #endif |
1da177e4 | 581 | }; |