Commit | Line | Data |
---|---|---|
007e8f51 DG |
1 | /* |
2 | * arch/powerpc/platforms/pseries/xics.c | |
1da177e4 LT |
3 | * |
4 | * Copyright 2000 IBM Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
0ebfff14 | 11 | |
1da177e4 LT |
12 | #include <linux/types.h> |
13 | #include <linux/threads.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/irq.h> | |
16 | #include <linux/smp.h> | |
17 | #include <linux/interrupt.h> | |
1da177e4 | 18 | #include <linux/init.h> |
1da177e4 LT |
19 | #include <linux/radix-tree.h> |
20 | #include <linux/cpu.h> | |
188bdddd | 21 | #include <linux/of.h> |
0ebfff14 | 22 | |
57cfb814 | 23 | #include <asm/firmware.h> |
1da177e4 LT |
24 | #include <asm/io.h> |
25 | #include <asm/pgtable.h> | |
26 | #include <asm/smp.h> | |
27 | #include <asm/rtas.h> | |
1da177e4 LT |
28 | #include <asm/hvcall.h> |
29 | #include <asm/machdep.h> | |
1da177e4 | 30 | |
007e8f51 | 31 | #include "xics.h" |
b9377ffc | 32 | #include "plpar_wrappers.h" |
007e8f51 | 33 | |
0641cc91 MM |
34 | static struct irq_host *xics_host; |
35 | ||
1da177e4 LT |
36 | #define XICS_IPI 2 |
37 | #define XICS_IRQ_SPURIOUS 0 | |
38 | ||
39 | /* Want a priority other than 0. Various HW issues require this. */ | |
40 | #define DEFAULT_PRIORITY 5 | |
41 | ||
007e8f51 | 42 | /* |
1da177e4 | 43 | * Mark IPIs as higher priority so we can take them inside interrupts that |
6714465e | 44 | * arent marked IRQF_DISABLED |
1da177e4 LT |
45 | */ |
46 | #define IPI_PRIORITY 4 | |
47 | ||
0641cc91 MM |
48 | static unsigned int default_server = 0xFF; |
49 | static unsigned int default_distrib_server = 0; | |
50 | static unsigned int interrupt_server_size = 8; | |
51 | ||
52 | /* RTAS service tokens */ | |
53 | static int ibm_get_xive; | |
54 | static int ibm_set_xive; | |
55 | static int ibm_int_on; | |
56 | static int ibm_int_off; | |
57 | ||
58 | ||
59 | /* Direct hardware low level accessors */ | |
60 | ||
61 | /* The part of the interrupt presentation layer that we care about */ | |
1da177e4 LT |
62 | struct xics_ipl { |
63 | union { | |
64 | u32 word; | |
65 | u8 bytes[4]; | |
66 | } xirr_poll; | |
67 | union { | |
68 | u32 word; | |
69 | u8 bytes[4]; | |
70 | } xirr; | |
71 | u32 dummy; | |
72 | union { | |
73 | u32 word; | |
74 | u8 bytes[4]; | |
75 | } qirr; | |
76 | }; | |
77 | ||
78 | static struct xics_ipl __iomem *xics_per_cpu[NR_CPUS]; | |
79 | ||
d7cf0edb | 80 | static inline unsigned int direct_xirr_info_get(void) |
1da177e4 | 81 | { |
d7cf0edb MM |
82 | int cpu = smp_processor_id(); |
83 | ||
84 | return in_be32(&xics_per_cpu[cpu]->xirr.word); | |
1da177e4 LT |
85 | } |
86 | ||
9dc2d441 | 87 | static inline void direct_xirr_info_set(unsigned int value) |
1da177e4 | 88 | { |
d7cf0edb MM |
89 | int cpu = smp_processor_id(); |
90 | ||
91 | out_be32(&xics_per_cpu[cpu]->xirr.word, value); | |
1da177e4 LT |
92 | } |
93 | ||
d7cf0edb | 94 | static inline void direct_cppr_info(u8 value) |
1da177e4 | 95 | { |
d7cf0edb MM |
96 | int cpu = smp_processor_id(); |
97 | ||
98 | out_8(&xics_per_cpu[cpu]->xirr.bytes[0], value); | |
1da177e4 LT |
99 | } |
100 | ||
b9e5b4e6 | 101 | static inline void direct_qirr_info(int n_cpu, u8 value) |
1da177e4 LT |
102 | { |
103 | out_8(&xics_per_cpu[n_cpu]->qirr.bytes[0], value); | |
104 | } | |
105 | ||
1da177e4 | 106 | |
b9e5b4e6 | 107 | /* LPAR low level accessors */ |
1da177e4 | 108 | |
d7cf0edb | 109 | static inline unsigned int lpar_xirr_info_get(void) |
1da177e4 LT |
110 | { |
111 | unsigned long lpar_rc; | |
007e8f51 | 112 | unsigned long return_value; |
1da177e4 LT |
113 | |
114 | lpar_rc = plpar_xirr(&return_value); | |
706c8c93 | 115 | if (lpar_rc != H_SUCCESS) |
007e8f51 | 116 | panic(" bad return code xirr - rc = %lx \n", lpar_rc); |
0ebfff14 | 117 | return (unsigned int)return_value; |
1da177e4 LT |
118 | } |
119 | ||
9dc2d441 | 120 | static inline void lpar_xirr_info_set(unsigned int value) |
1da177e4 LT |
121 | { |
122 | unsigned long lpar_rc; | |
1da177e4 | 123 | |
9dc2d441 | 124 | lpar_rc = plpar_eoi(value); |
706c8c93 | 125 | if (lpar_rc != H_SUCCESS) |
9dc2d441 MM |
126 | panic("bad return code EOI - rc = %ld, value=%x\n", lpar_rc, |
127 | value); | |
1da177e4 LT |
128 | } |
129 | ||
d7cf0edb | 130 | static inline void lpar_cppr_info(u8 value) |
1da177e4 LT |
131 | { |
132 | unsigned long lpar_rc; | |
133 | ||
134 | lpar_rc = plpar_cppr(value); | |
706c8c93 | 135 | if (lpar_rc != H_SUCCESS) |
007e8f51 | 136 | panic("bad return code cppr - rc = %lx\n", lpar_rc); |
1da177e4 LT |
137 | } |
138 | ||
b9e5b4e6 | 139 | static inline void lpar_qirr_info(int n_cpu , u8 value) |
1da177e4 LT |
140 | { |
141 | unsigned long lpar_rc; | |
142 | ||
143 | lpar_rc = plpar_ipi(get_hard_smp_processor_id(n_cpu), value); | |
706c8c93 | 144 | if (lpar_rc != H_SUCCESS) |
007e8f51 | 145 | panic("bad return code qirr - rc = %lx\n", lpar_rc); |
1da177e4 LT |
146 | } |
147 | ||
1da177e4 | 148 | |
0641cc91 | 149 | /* Interface to generic irq subsystem */ |
1da177e4 LT |
150 | |
151 | #ifdef CONFIG_SMP | |
7ccb4a66 | 152 | static int get_irq_server(unsigned int virq, unsigned int strict_check) |
1da177e4 | 153 | { |
7ccb4a66 | 154 | int server; |
1da177e4 | 155 | /* For the moment only implement delivery to all cpus or one cpu */ |
e65e49d0 | 156 | cpumask_t cpumask; |
1da177e4 LT |
157 | cpumask_t tmp = CPU_MASK_NONE; |
158 | ||
e65e49d0 | 159 | cpumask_copy(&cpumask, irq_desc[virq].affinity); |
1da177e4 LT |
160 | if (!distribute_irqs) |
161 | return default_server; | |
162 | ||
7ccb4a66 | 163 | if (!cpus_equal(cpumask, CPU_MASK_ALL)) { |
1da177e4 LT |
164 | cpus_and(tmp, cpu_online_map, cpumask); |
165 | ||
7ccb4a66 MK |
166 | server = first_cpu(tmp); |
167 | ||
168 | if (server < NR_CPUS) | |
169 | return get_hard_smp_processor_id(server); | |
170 | ||
171 | if (strict_check) | |
172 | return -1; | |
1da177e4 LT |
173 | } |
174 | ||
7ccb4a66 MK |
175 | if (cpus_equal(cpu_online_map, cpu_present_map)) |
176 | return default_distrib_server; | |
1da177e4 | 177 | |
7ccb4a66 | 178 | return default_server; |
1da177e4 LT |
179 | } |
180 | #else | |
7ccb4a66 | 181 | static int get_irq_server(unsigned int virq, unsigned int strict_check) |
1da177e4 LT |
182 | { |
183 | return default_server; | |
184 | } | |
185 | #endif | |
186 | ||
b9e5b4e6 | 187 | static void xics_unmask_irq(unsigned int virq) |
1da177e4 LT |
188 | { |
189 | unsigned int irq; | |
190 | int call_status; | |
7ccb4a66 | 191 | int server; |
1da177e4 | 192 | |
0ebfff14 BH |
193 | pr_debug("xics: unmask virq %d\n", virq); |
194 | ||
195 | irq = (unsigned int)irq_map[virq].hwirq; | |
196 | pr_debug(" -> map to hwirq 0x%x\n", irq); | |
197 | if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS) | |
1da177e4 LT |
198 | return; |
199 | ||
7ccb4a66 | 200 | server = get_irq_server(virq, 0); |
b9e5b4e6 | 201 | |
1da177e4 LT |
202 | call_status = rtas_call(ibm_set_xive, 3, 1, NULL, irq, server, |
203 | DEFAULT_PRIORITY); | |
204 | if (call_status != 0) { | |
2172fe87 MM |
205 | printk(KERN_ERR |
206 | "%s: ibm_set_xive irq %u server %x returned %d\n", | |
207 | __func__, irq, server, call_status); | |
1da177e4 LT |
208 | return; |
209 | } | |
210 | ||
211 | /* Now unmask the interrupt (often a no-op) */ | |
212 | call_status = rtas_call(ibm_int_on, 1, 1, NULL, irq); | |
213 | if (call_status != 0) { | |
2172fe87 MM |
214 | printk(KERN_ERR "%s: ibm_int_on irq=%u returned %d\n", |
215 | __func__, irq, call_status); | |
1da177e4 LT |
216 | return; |
217 | } | |
218 | } | |
219 | ||
0641cc91 MM |
220 | static unsigned int xics_startup(unsigned int virq) |
221 | { | |
222 | /* unmask it */ | |
223 | xics_unmask_irq(virq); | |
224 | return 0; | |
225 | } | |
226 | ||
b9e5b4e6 | 227 | static void xics_mask_real_irq(unsigned int irq) |
1da177e4 LT |
228 | { |
229 | int call_status; | |
1da177e4 LT |
230 | |
231 | if (irq == XICS_IPI) | |
232 | return; | |
233 | ||
234 | call_status = rtas_call(ibm_int_off, 1, 1, NULL, irq); | |
235 | if (call_status != 0) { | |
2172fe87 MM |
236 | printk(KERN_ERR "%s: ibm_int_off irq=%u returned %d\n", |
237 | __func__, irq, call_status); | |
1da177e4 LT |
238 | return; |
239 | } | |
240 | ||
1da177e4 | 241 | /* Have to set XIVE to 0xff to be able to remove a slot */ |
673aeb76 MO |
242 | call_status = rtas_call(ibm_set_xive, 3, 1, NULL, irq, |
243 | default_server, 0xff); | |
1da177e4 | 244 | if (call_status != 0) { |
2172fe87 MM |
245 | printk(KERN_ERR "%s: ibm_set_xive(0xff) irq=%u returned %d\n", |
246 | __func__, irq, call_status); | |
1da177e4 LT |
247 | return; |
248 | } | |
249 | } | |
250 | ||
b9e5b4e6 | 251 | static void xics_mask_irq(unsigned int virq) |
1da177e4 LT |
252 | { |
253 | unsigned int irq; | |
254 | ||
0ebfff14 BH |
255 | pr_debug("xics: mask virq %d\n", virq); |
256 | ||
257 | irq = (unsigned int)irq_map[virq].hwirq; | |
258 | if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS) | |
259 | return; | |
260 | xics_mask_real_irq(irq); | |
b9e5b4e6 BH |
261 | } |
262 | ||
0641cc91 | 263 | static void xics_mask_unknown_vec(unsigned int vec) |
1da177e4 | 264 | { |
0641cc91 MM |
265 | printk(KERN_ERR "Interrupt %u (real) is invalid, disabling it.\n", vec); |
266 | xics_mask_real_irq(vec); | |
1da177e4 LT |
267 | } |
268 | ||
8767e9ba | 269 | static inline unsigned int xics_xirr_vector(unsigned int xirr) |
1da177e4 | 270 | { |
8767e9ba MM |
271 | /* |
272 | * The top byte is the old cppr, to be restored on EOI. | |
273 | * The remaining 24 bits are the vector. | |
274 | */ | |
275 | return xirr & 0x00ffffff; | |
276 | } | |
277 | ||
8767e9ba MM |
278 | static unsigned int xics_get_irq_direct(void) |
279 | { | |
280 | unsigned int xirr = direct_xirr_info_get(); | |
281 | unsigned int vec = xics_xirr_vector(xirr); | |
282 | unsigned int irq; | |
1da177e4 | 283 | |
b9e5b4e6 BH |
284 | if (vec == XICS_IRQ_SPURIOUS) |
285 | return NO_IRQ; | |
8767e9ba | 286 | |
967e012e | 287 | irq = irq_radix_revmap_lookup(xics_host, vec); |
b9e5b4e6 | 288 | if (likely(irq != NO_IRQ)) |
0ebfff14 | 289 | return irq; |
b9e5b4e6 | 290 | |
8767e9ba MM |
291 | /* We don't have a linux mapping, so have rtas mask it. */ |
292 | xics_mask_unknown_vec(vec); | |
1da177e4 | 293 | |
8767e9ba MM |
294 | /* We might learn about it later, so EOI it */ |
295 | direct_xirr_info_set(xirr); | |
296 | return NO_IRQ; | |
b9e5b4e6 BH |
297 | } |
298 | ||
35a84c2f | 299 | static unsigned int xics_get_irq_lpar(void) |
1da177e4 | 300 | { |
8767e9ba MM |
301 | unsigned int xirr = lpar_xirr_info_get(); |
302 | unsigned int vec = xics_xirr_vector(xirr); | |
303 | unsigned int irq; | |
304 | ||
305 | if (vec == XICS_IRQ_SPURIOUS) | |
306 | return NO_IRQ; | |
307 | ||
308 | irq = irq_radix_revmap_lookup(xics_host, vec); | |
309 | if (likely(irq != NO_IRQ)) | |
310 | return irq; | |
311 | ||
312 | /* We don't have a linux mapping, so have RTAS mask it. */ | |
313 | xics_mask_unknown_vec(vec); | |
314 | ||
315 | /* We might learn about it later, so EOI it */ | |
316 | lpar_xirr_info_set(xirr); | |
317 | return NO_IRQ; | |
b9e5b4e6 BH |
318 | } |
319 | ||
0641cc91 | 320 | static void xics_eoi_direct(unsigned int virq) |
b9e5b4e6 | 321 | { |
0641cc91 | 322 | unsigned int irq = (unsigned int)irq_map[virq].hwirq; |
b9e5b4e6 | 323 | |
0641cc91 MM |
324 | iosync(); |
325 | direct_xirr_info_set((0xff << 24) | irq); | |
b9e5b4e6 BH |
326 | } |
327 | ||
0641cc91 | 328 | static void xics_eoi_lpar(unsigned int virq) |
b9e5b4e6 | 329 | { |
0641cc91 | 330 | unsigned int irq = (unsigned int)irq_map[virq].hwirq; |
1da177e4 | 331 | |
b9e5b4e6 | 332 | iosync(); |
0641cc91 | 333 | lpar_xirr_info_set((0xff << 24) | irq); |
b9e5b4e6 BH |
334 | } |
335 | ||
d5dedd45 | 336 | static int xics_set_affinity(unsigned int virq, const struct cpumask *cpumask) |
b9e5b4e6 BH |
337 | { |
338 | unsigned int irq; | |
339 | int status; | |
340 | int xics_status[2]; | |
7ccb4a66 | 341 | int irq_server; |
b9e5b4e6 | 342 | |
0ebfff14 BH |
343 | irq = (unsigned int)irq_map[virq].hwirq; |
344 | if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS) | |
d5dedd45 | 345 | return -1; |
b9e5b4e6 BH |
346 | |
347 | status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq); | |
348 | ||
349 | if (status) { | |
2172fe87 MM |
350 | printk(KERN_ERR "%s: ibm,get-xive irq=%u returns %d\n", |
351 | __func__, irq, status); | |
d5dedd45 | 352 | return -1; |
b9e5b4e6 BH |
353 | } |
354 | ||
7ccb4a66 MK |
355 | /* |
356 | * For the moment only implement delivery to all cpus or one cpu. | |
357 | * Get current irq_server for the given irq | |
358 | */ | |
e48395f1 | 359 | irq_server = get_irq_server(virq, 1); |
7ccb4a66 MK |
360 | if (irq_server == -1) { |
361 | char cpulist[128]; | |
362 | cpumask_scnprintf(cpulist, sizeof(cpulist), cpumask); | |
2172fe87 MM |
363 | printk(KERN_WARNING |
364 | "%s: No online cpus in the mask %s for irq %d\n", | |
365 | __func__, cpulist, virq); | |
d5dedd45 | 366 | return -1; |
b9e5b4e6 BH |
367 | } |
368 | ||
369 | status = rtas_call(ibm_set_xive, 3, 1, NULL, | |
7ccb4a66 | 370 | irq, irq_server, xics_status[1]); |
b9e5b4e6 BH |
371 | |
372 | if (status) { | |
2172fe87 MM |
373 | printk(KERN_ERR "%s: ibm,set-xive irq=%u returns %d\n", |
374 | __func__, irq, status); | |
d5dedd45 | 375 | return -1; |
b9e5b4e6 | 376 | } |
d5dedd45 YL |
377 | |
378 | return 0; | |
b9e5b4e6 BH |
379 | } |
380 | ||
381 | static struct irq_chip xics_pic_direct = { | |
382 | .typename = " XICS ", | |
383 | .startup = xics_startup, | |
384 | .mask = xics_mask_irq, | |
385 | .unmask = xics_unmask_irq, | |
386 | .eoi = xics_eoi_direct, | |
387 | .set_affinity = xics_set_affinity | |
388 | }; | |
389 | ||
b9e5b4e6 BH |
390 | static struct irq_chip xics_pic_lpar = { |
391 | .typename = " XICS ", | |
392 | .startup = xics_startup, | |
393 | .mask = xics_mask_irq, | |
394 | .unmask = xics_unmask_irq, | |
395 | .eoi = xics_eoi_lpar, | |
396 | .set_affinity = xics_set_affinity | |
397 | }; | |
398 | ||
0641cc91 MM |
399 | |
400 | /* Interface to arch irq controller subsystem layer */ | |
401 | ||
1af9fa89 ME |
402 | /* Points to the irq_chip we're actually using */ |
403 | static struct irq_chip *xics_irq_chip; | |
b9e5b4e6 | 404 | |
0ebfff14 | 405 | static int xics_host_match(struct irq_host *h, struct device_node *node) |
1da177e4 | 406 | { |
0ebfff14 BH |
407 | /* IBM machines have interrupt parents of various funky types for things |
408 | * like vdevices, events, etc... The trick we use here is to match | |
409 | * everything here except the legacy 8259 which is compatible "chrp,iic" | |
410 | */ | |
55b61fec | 411 | return !of_device_is_compatible(node, "chrp,iic"); |
0ebfff14 | 412 | } |
1da177e4 | 413 | |
1af9fa89 ME |
414 | static int xics_host_map(struct irq_host *h, unsigned int virq, |
415 | irq_hw_number_t hw) | |
0ebfff14 | 416 | { |
1af9fa89 | 417 | pr_debug("xics: map virq %d, hwirq 0x%lx\n", virq, hw); |
0ebfff14 | 418 | |
967e012e SD |
419 | /* Insert the interrupt mapping into the radix tree for fast lookup */ |
420 | irq_radix_revmap_insert(xics_host, virq, hw); | |
421 | ||
0ebfff14 | 422 | get_irq_desc(virq)->status |= IRQ_LEVEL; |
1af9fa89 | 423 | set_irq_chip_and_handler(virq, xics_irq_chip, handle_fasteoi_irq); |
0ebfff14 BH |
424 | return 0; |
425 | } | |
426 | ||
427 | static int xics_host_xlate(struct irq_host *h, struct device_node *ct, | |
428 | u32 *intspec, unsigned int intsize, | |
429 | irq_hw_number_t *out_hwirq, unsigned int *out_flags) | |
430 | ||
431 | { | |
432 | /* Current xics implementation translates everything | |
433 | * to level. It is not technically right for MSIs but this | |
434 | * is irrelevant at this point. We might get smarter in the future | |
6c80a21c | 435 | */ |
0ebfff14 BH |
436 | *out_hwirq = intspec[0]; |
437 | *out_flags = IRQ_TYPE_LEVEL_LOW; | |
438 | ||
439 | return 0; | |
440 | } | |
441 | ||
1af9fa89 | 442 | static struct irq_host_ops xics_host_ops = { |
0ebfff14 | 443 | .match = xics_host_match, |
1af9fa89 | 444 | .map = xics_host_map, |
0ebfff14 BH |
445 | .xlate = xics_host_xlate, |
446 | }; | |
447 | ||
448 | static void __init xics_init_host(void) | |
449 | { | |
0ebfff14 | 450 | if (firmware_has_feature(FW_FEATURE_LPAR)) |
1af9fa89 | 451 | xics_irq_chip = &xics_pic_lpar; |
0ebfff14 | 452 | else |
1af9fa89 ME |
453 | xics_irq_chip = &xics_pic_direct; |
454 | ||
455 | xics_host = irq_alloc_host(NULL, IRQ_HOST_MAP_TREE, 0, &xics_host_ops, | |
0ebfff14 BH |
456 | XICS_IRQ_SPURIOUS); |
457 | BUG_ON(xics_host == NULL); | |
458 | irq_set_default_host(xics_host); | |
6c80a21c | 459 | } |
1da177e4 | 460 | |
0641cc91 MM |
461 | |
462 | /* Inter-processor interrupt support */ | |
463 | ||
464 | #ifdef CONFIG_SMP | |
465 | /* | |
466 | * XICS only has a single IPI, so encode the messages per CPU | |
467 | */ | |
468 | struct xics_ipi_struct { | |
469 | unsigned long value; | |
470 | } ____cacheline_aligned; | |
471 | ||
472 | static struct xics_ipi_struct xics_ipi_message[NR_CPUS] __cacheline_aligned; | |
473 | ||
474 | static inline void smp_xics_do_message(int cpu, int msg) | |
475 | { | |
476 | set_bit(msg, &xics_ipi_message[cpu].value); | |
477 | mb(); | |
478 | if (firmware_has_feature(FW_FEATURE_LPAR)) | |
479 | lpar_qirr_info(cpu, IPI_PRIORITY); | |
480 | else | |
481 | direct_qirr_info(cpu, IPI_PRIORITY); | |
482 | } | |
483 | ||
484 | void smp_xics_message_pass(int target, int msg) | |
485 | { | |
486 | unsigned int i; | |
487 | ||
488 | if (target < NR_CPUS) { | |
489 | smp_xics_do_message(target, msg); | |
490 | } else { | |
491 | for_each_online_cpu(i) { | |
492 | if (target == MSG_ALL_BUT_SELF | |
493 | && i == smp_processor_id()) | |
494 | continue; | |
495 | smp_xics_do_message(i, msg); | |
496 | } | |
497 | } | |
498 | } | |
499 | ||
500 | static irqreturn_t xics_ipi_dispatch(int cpu) | |
501 | { | |
502 | WARN_ON(cpu_is_offline(cpu)); | |
503 | ||
199f45c4 | 504 | mb(); /* order mmio clearing qirr */ |
0641cc91 MM |
505 | while (xics_ipi_message[cpu].value) { |
506 | if (test_and_clear_bit(PPC_MSG_CALL_FUNCTION, | |
507 | &xics_ipi_message[cpu].value)) { | |
0641cc91 MM |
508 | smp_message_recv(PPC_MSG_CALL_FUNCTION); |
509 | } | |
510 | if (test_and_clear_bit(PPC_MSG_RESCHEDULE, | |
511 | &xics_ipi_message[cpu].value)) { | |
0641cc91 MM |
512 | smp_message_recv(PPC_MSG_RESCHEDULE); |
513 | } | |
514 | if (test_and_clear_bit(PPC_MSG_CALL_FUNC_SINGLE, | |
515 | &xics_ipi_message[cpu].value)) { | |
0641cc91 MM |
516 | smp_message_recv(PPC_MSG_CALL_FUNC_SINGLE); |
517 | } | |
518 | #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC) | |
519 | if (test_and_clear_bit(PPC_MSG_DEBUGGER_BREAK, | |
520 | &xics_ipi_message[cpu].value)) { | |
0641cc91 MM |
521 | smp_message_recv(PPC_MSG_DEBUGGER_BREAK); |
522 | } | |
523 | #endif | |
524 | } | |
525 | return IRQ_HANDLED; | |
526 | } | |
527 | ||
528 | static irqreturn_t xics_ipi_action_direct(int irq, void *dev_id) | |
529 | { | |
530 | int cpu = smp_processor_id(); | |
531 | ||
532 | direct_qirr_info(cpu, 0xff); | |
533 | ||
534 | return xics_ipi_dispatch(cpu); | |
535 | } | |
536 | ||
537 | static irqreturn_t xics_ipi_action_lpar(int irq, void *dev_id) | |
538 | { | |
539 | int cpu = smp_processor_id(); | |
540 | ||
541 | lpar_qirr_info(cpu, 0xff); | |
542 | ||
543 | return xics_ipi_dispatch(cpu); | |
544 | } | |
545 | ||
546 | static void xics_request_ipi(void) | |
547 | { | |
548 | unsigned int ipi; | |
549 | int rc; | |
550 | ||
551 | ipi = irq_create_mapping(xics_host, XICS_IPI); | |
552 | BUG_ON(ipi == NO_IRQ); | |
553 | ||
554 | /* | |
555 | * IPIs are marked IRQF_DISABLED as they must run with irqs | |
556 | * disabled | |
557 | */ | |
558 | set_irq_handler(ipi, handle_percpu_irq); | |
559 | if (firmware_has_feature(FW_FEATURE_LPAR)) | |
d879f384 MM |
560 | rc = request_irq(ipi, xics_ipi_action_lpar, |
561 | IRQF_DISABLED|IRQF_PERCPU, "IPI", NULL); | |
0641cc91 | 562 | else |
d879f384 MM |
563 | rc = request_irq(ipi, xics_ipi_action_direct, |
564 | IRQF_DISABLED|IRQF_PERCPU, "IPI", NULL); | |
0641cc91 MM |
565 | BUG_ON(rc); |
566 | } | |
567 | ||
568 | int __init smp_xics_probe(void) | |
569 | { | |
570 | xics_request_ipi(); | |
571 | ||
572 | return cpus_weight(cpu_possible_map); | |
573 | } | |
574 | ||
575 | #endif /* CONFIG_SMP */ | |
576 | ||
577 | ||
578 | /* Initialization */ | |
579 | ||
580 | static void xics_update_irq_servers(void) | |
581 | { | |
582 | int i, j; | |
583 | struct device_node *np; | |
584 | u32 ilen; | |
1ef8014d | 585 | const u32 *ireg; |
0641cc91 MM |
586 | u32 hcpuid; |
587 | ||
588 | /* Find the server numbers for the boot cpu. */ | |
589 | np = of_get_cpu_node(boot_cpuid, NULL); | |
590 | BUG_ON(!np); | |
591 | ||
592 | ireg = of_get_property(np, "ibm,ppc-interrupt-gserver#s", &ilen); | |
593 | if (!ireg) { | |
594 | of_node_put(np); | |
595 | return; | |
596 | } | |
597 | ||
598 | i = ilen / sizeof(int); | |
599 | hcpuid = get_hard_smp_processor_id(boot_cpuid); | |
600 | ||
601 | /* Global interrupt distribution server is specified in the last | |
602 | * entry of "ibm,ppc-interrupt-gserver#s" property. Get the last | |
603 | * entry fom this property for current boot cpu id and use it as | |
604 | * default distribution server | |
605 | */ | |
606 | for (j = 0; j < i; j += 2) { | |
607 | if (ireg[j] == hcpuid) { | |
608 | default_server = hcpuid; | |
609 | default_distrib_server = ireg[j+1]; | |
0641cc91 MM |
610 | } |
611 | } | |
612 | ||
613 | of_node_put(np); | |
614 | } | |
615 | ||
0ebfff14 BH |
616 | static void __init xics_map_one_cpu(int hw_id, unsigned long addr, |
617 | unsigned long size) | |
1da177e4 LT |
618 | { |
619 | int i; | |
1da177e4 | 620 | |
0ebfff14 BH |
621 | /* This may look gross but it's good enough for now, we don't quite |
622 | * have a hard -> linux processor id matching. | |
623 | */ | |
624 | for_each_possible_cpu(i) { | |
625 | if (!cpu_present(i)) | |
626 | continue; | |
627 | if (hw_id == get_hard_smp_processor_id(i)) { | |
628 | xics_per_cpu[i] = ioremap(addr, size); | |
629 | return; | |
630 | } | |
631 | } | |
0ebfff14 | 632 | } |
1da177e4 | 633 | |
0ebfff14 BH |
634 | static void __init xics_init_one_node(struct device_node *np, |
635 | unsigned int *indx) | |
636 | { | |
637 | unsigned int ilen; | |
954a46e2 | 638 | const u32 *ireg; |
1da177e4 | 639 | |
0ebfff14 BH |
640 | /* This code does the theorically broken assumption that the interrupt |
641 | * server numbers are the same as the hard CPU numbers. | |
642 | * This happens to be the case so far but we are playing with fire... | |
643 | * should be fixed one of these days. -BenH. | |
644 | */ | |
e2eb6392 | 645 | ireg = of_get_property(np, "ibm,interrupt-server-ranges", NULL); |
1da177e4 | 646 | |
0ebfff14 BH |
647 | /* Do that ever happen ? we'll know soon enough... but even good'old |
648 | * f80 does have that property .. | |
649 | */ | |
650 | WARN_ON(ireg == NULL); | |
1da177e4 LT |
651 | if (ireg) { |
652 | /* | |
653 | * set node starting index for this node | |
654 | */ | |
0ebfff14 | 655 | *indx = *ireg; |
1da177e4 | 656 | } |
e2eb6392 | 657 | ireg = of_get_property(np, "reg", &ilen); |
1da177e4 LT |
658 | if (!ireg) |
659 | panic("xics_init_IRQ: can't find interrupt reg property"); | |
007e8f51 | 660 | |
0ebfff14 BH |
661 | while (ilen >= (4 * sizeof(u32))) { |
662 | unsigned long addr, size; | |
663 | ||
664 | /* XXX Use proper OF parsing code here !!! */ | |
665 | addr = (unsigned long)*ireg++ << 32; | |
666 | ilen -= sizeof(u32); | |
667 | addr |= *ireg++; | |
668 | ilen -= sizeof(u32); | |
669 | size = (unsigned long)*ireg++ << 32; | |
670 | ilen -= sizeof(u32); | |
671 | size |= *ireg++; | |
672 | ilen -= sizeof(u32); | |
673 | xics_map_one_cpu(*indx, addr, size); | |
674 | (*indx)++; | |
675 | } | |
676 | } | |
677 | ||
0ebfff14 BH |
678 | void __init xics_init_IRQ(void) |
679 | { | |
0ebfff14 | 680 | struct device_node *np; |
de0723dc | 681 | u32 indx = 0; |
0ebfff14 | 682 | int found = 0; |
1ef8014d | 683 | const u32 *isize; |
0ebfff14 BH |
684 | |
685 | ppc64_boot_msg(0x20, "XICS Init"); | |
686 | ||
687 | ibm_get_xive = rtas_token("ibm,get-xive"); | |
688 | ibm_set_xive = rtas_token("ibm,set-xive"); | |
689 | ibm_int_on = rtas_token("ibm,int-on"); | |
690 | ibm_int_off = rtas_token("ibm,int-off"); | |
691 | ||
692 | for_each_node_by_type(np, "PowerPC-External-Interrupt-Presentation") { | |
693 | found = 1; | |
a244a957 MM |
694 | if (firmware_has_feature(FW_FEATURE_LPAR)) { |
695 | of_node_put(np); | |
0ebfff14 | 696 | break; |
a244a957 | 697 | } |
0ebfff14 BH |
698 | xics_init_one_node(np, &indx); |
699 | } | |
700 | if (found == 0) | |
701 | return; | |
702 | ||
1ef8014d SD |
703 | /* get the bit size of server numbers */ |
704 | found = 0; | |
705 | ||
706 | for_each_compatible_node(np, NULL, "ibm,ppc-xics") { | |
707 | isize = of_get_property(np, "ibm,interrupt-server#-size", NULL); | |
708 | ||
709 | if (!isize) | |
710 | continue; | |
711 | ||
712 | if (!found) { | |
713 | interrupt_server_size = *isize; | |
714 | found = 1; | |
715 | } else if (*isize != interrupt_server_size) { | |
716 | printk(KERN_WARNING "XICS: " | |
717 | "mismatched ibm,interrupt-server#-size\n"); | |
718 | interrupt_server_size = max(*isize, | |
719 | interrupt_server_size); | |
720 | } | |
721 | } | |
722 | ||
de0723dc | 723 | xics_update_irq_servers(); |
302905a3 | 724 | xics_init_host(); |
1da177e4 | 725 | |
0ebfff14 BH |
726 | if (firmware_has_feature(FW_FEATURE_LPAR)) |
727 | ppc_md.get_irq = xics_get_irq_lpar; | |
728 | else | |
b9e5b4e6 | 729 | ppc_md.get_irq = xics_get_irq_direct; |
1da177e4 | 730 | |
6c80a21c | 731 | xics_setup_cpu(); |
1da177e4 | 732 | |
0ebfff14 | 733 | ppc64_boot_msg(0x21, "XICS Done"); |
1da177e4 | 734 | } |
b9e5b4e6 | 735 | |
0641cc91 | 736 | /* Cpu startup, shutdown, and hotplug */ |
1da177e4 | 737 | |
0641cc91 | 738 | static void xics_set_cpu_priority(unsigned char cppr) |
1da177e4 | 739 | { |
b9e5b4e6 | 740 | if (firmware_has_feature(FW_FEATURE_LPAR)) |
0641cc91 | 741 | lpar_cppr_info(cppr); |
b9e5b4e6 | 742 | else |
0641cc91 MM |
743 | direct_cppr_info(cppr); |
744 | iosync(); | |
1da177e4 | 745 | } |
d13f7208 | 746 | |
b4963255 MM |
747 | /* Have the calling processor join or leave the specified global queue */ |
748 | static void xics_set_cpu_giq(unsigned int gserver, unsigned int join) | |
749 | { | |
edc72ac4 NL |
750 | int index; |
751 | int status; | |
752 | ||
753 | if (!rtas_indicator_present(GLOBAL_INTERRUPT_QUEUE, NULL)) | |
754 | return; | |
755 | ||
756 | index = (1UL << interrupt_server_size) - 1 - gserver; | |
757 | ||
758 | status = rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE, index, join); | |
759 | ||
760 | WARN(status < 0, "set-indicator(%d, %d, %u) returned %d\n", | |
761 | GLOBAL_INTERRUPT_QUEUE, index, join, status); | |
b4963255 | 762 | } |
0641cc91 MM |
763 | |
764 | void xics_setup_cpu(void) | |
d13f7208 | 765 | { |
0641cc91 | 766 | xics_set_cpu_priority(0xff); |
d13f7208 | 767 | |
b4963255 | 768 | xics_set_cpu_giq(default_distrib_server, 1); |
d13f7208 MM |
769 | } |
770 | ||
f10095c3 | 771 | void xics_teardown_cpu(void) |
fce0d574 S |
772 | { |
773 | int cpu = smp_processor_id(); | |
fce0d574 | 774 | |
d7cf0edb | 775 | xics_set_cpu_priority(0); |
81bbbe92 | 776 | |
b4963255 | 777 | /* Clear any pending IPI request */ |
6e99e458 BH |
778 | if (firmware_has_feature(FW_FEATURE_LPAR)) |
779 | lpar_qirr_info(cpu, 0xff); | |
780 | else | |
781 | direct_qirr_info(cpu, 0xff); | |
c3e8506c NF |
782 | } |
783 | ||
784 | void xics_kexec_teardown_cpu(int secondary) | |
785 | { | |
c3e8506c | 786 | xics_teardown_cpu(); |
6e99e458 | 787 | |
81bbbe92 | 788 | /* |
1a57c926 MM |
789 | * we take the ipi irq but and never return so we |
790 | * need to EOI the IPI, but want to leave our priority 0 | |
81bbbe92 | 791 | * |
1a57c926 | 792 | * should we check all the other interrupts too? |
81bbbe92 HM |
793 | * should we be flagging idle loop instead? |
794 | * or creating some task to be scheduled? | |
795 | */ | |
0ebfff14 | 796 | |
1a57c926 MM |
797 | if (firmware_has_feature(FW_FEATURE_LPAR)) |
798 | lpar_xirr_info_set((0x00 << 24) | XICS_IPI); | |
799 | else | |
800 | direct_xirr_info_set((0x00 << 24) | XICS_IPI); | |
81bbbe92 | 801 | |
fce0d574 | 802 | /* |
6d22d85a PM |
803 | * Some machines need to have at least one cpu in the GIQ, |
804 | * so leave the master cpu in the group. | |
fce0d574 | 805 | */ |
81bbbe92 | 806 | if (secondary) |
b4963255 | 807 | xics_set_cpu_giq(default_distrib_server, 0); |
fce0d574 S |
808 | } |
809 | ||
1da177e4 LT |
810 | #ifdef CONFIG_HOTPLUG_CPU |
811 | ||
812 | /* Interrupts are disabled. */ | |
813 | void xics_migrate_irqs_away(void) | |
814 | { | |
d7cf0edb MM |
815 | int cpu = smp_processor_id(), hw_cpu = hard_smp_processor_id(); |
816 | unsigned int irq, virq; | |
1da177e4 | 817 | |
302905a3 MM |
818 | /* If we used to be the default server, move to the new "boot_cpuid" */ |
819 | if (hw_cpu == default_server) | |
820 | xics_update_irq_servers(); | |
821 | ||
1da177e4 | 822 | /* Reject any interrupt that was queued to us... */ |
d7cf0edb | 823 | xics_set_cpu_priority(0); |
1da177e4 | 824 | |
b4963255 MM |
825 | /* Remove ourselves from the global interrupt queue */ |
826 | xics_set_cpu_giq(default_distrib_server, 0); | |
1da177e4 LT |
827 | |
828 | /* Allow IPIs again... */ | |
d7cf0edb | 829 | xics_set_cpu_priority(DEFAULT_PRIORITY); |
1da177e4 LT |
830 | |
831 | for_each_irq(virq) { | |
b9e5b4e6 | 832 | struct irq_desc *desc; |
1da177e4 | 833 | int xics_status[2]; |
b4963255 | 834 | int status; |
1da177e4 LT |
835 | unsigned long flags; |
836 | ||
837 | /* We cant set affinity on ISA interrupts */ | |
0ebfff14 | 838 | if (virq < NUM_ISA_INTERRUPTS) |
1da177e4 | 839 | continue; |
0ebfff14 BH |
840 | if (irq_map[virq].host != xics_host) |
841 | continue; | |
842 | irq = (unsigned int)irq_map[virq].hwirq; | |
1da177e4 | 843 | /* We need to get IPIs still. */ |
0ebfff14 | 844 | if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS) |
1da177e4 | 845 | continue; |
0ebfff14 | 846 | desc = get_irq_desc(virq); |
1da177e4 LT |
847 | |
848 | /* We only need to migrate enabled IRQS */ | |
d1bef4ed | 849 | if (desc == NULL || desc->chip == NULL |
1da177e4 | 850 | || desc->action == NULL |
d1bef4ed | 851 | || desc->chip->set_affinity == NULL) |
1da177e4 LT |
852 | continue; |
853 | ||
854 | spin_lock_irqsave(&desc->lock, flags); | |
855 | ||
856 | status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq); | |
857 | if (status) { | |
2172fe87 MM |
858 | printk(KERN_ERR "%s: ibm,get-xive irq=%u returns %d\n", |
859 | __func__, irq, status); | |
1da177e4 LT |
860 | goto unlock; |
861 | } | |
862 | ||
863 | /* | |
864 | * We only support delivery to all cpus or to one cpu. | |
865 | * The irq has to be migrated only in the single cpu | |
866 | * case. | |
867 | */ | |
d7cf0edb | 868 | if (xics_status[0] != hw_cpu) |
1da177e4 LT |
869 | goto unlock; |
870 | ||
26370322 | 871 | printk(KERN_WARNING "IRQ %u affinity broken off cpu %u\n", |
1da177e4 LT |
872 | virq, cpu); |
873 | ||
874 | /* Reset affinity to all cpus */ | |
e65e49d0 | 875 | cpumask_setall(irq_desc[virq].affinity); |
0de26520 | 876 | desc->chip->set_affinity(virq, cpu_all_mask); |
1da177e4 LT |
877 | unlock: |
878 | spin_unlock_irqrestore(&desc->lock, flags); | |
879 | } | |
880 | } | |
881 | #endif |