Merge branch 'linux-4.6' of git://github.com/skeggsb/linux into drm-fixes
[deliverable/linux.git] / arch / powerpc / sysdev / fsl_msi.h
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1/*
2 * Copyright (C) 2007-2008 Freescale Semiconductor, Inc. All rights reserved.
3 *
4 * Author: Tony Li <tony.li@freescale.com>
5 * Jason Jin <Jason.jin@freescale.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2 of the
10 * License.
11 *
12 */
13#ifndef _POWERPC_SYSDEV_FSL_MSI_H
14#define _POWERPC_SYSDEV_FSL_MSI_H
15
895d603f 16#include <linux/of.h>
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17#include <asm/msi_bitmap.h>
18
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19#define NR_MSI_REG_MSIIR 8 /* MSIIR can index 8 MSI registers */
20#define NR_MSI_REG_MSIIR1 16 /* MSIIR1 can index 16 MSI registers */
21#define NR_MSI_REG_MAX NR_MSI_REG_MSIIR1
34e36c15 22#define IRQS_PER_MSI_REG 32
f31dd944 23#define NR_MSI_IRQS_MAX (NR_MSI_REG_MAX * IRQS_PER_MSI_REG)
34e36c15 24
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25#define FSL_PIC_IP_MASK 0x0000000F
26#define FSL_PIC_IP_MPIC 0x00000001
27#define FSL_PIC_IP_IPIC 0x00000002
28#define FSL_PIC_IP_VMPIC 0x00000003
34e36c15 29
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30#define MSI_HW_ERRATA_ENDIAN 0x00000010
31
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32struct fsl_msi_cascade_data;
33
34e36c15 34struct fsl_msi {
bae1d8f1 35 struct irq_domain *irqhost;
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36
37 unsigned long cascade_irq;
38
2bcd1c0c 39 u32 msiir_offset; /* Offset of MSIIR, relative to start of CCSR */
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40 u32 ibs_shift; /* Shift of interrupt bit select */
41 u32 srs_shift; /* Shift of the shared interrupt register select */
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42 void __iomem *msi_regs;
43 u32 feature;
83495231 44 struct fsl_msi_cascade_data *cascade_array[NR_MSI_REG_MAX];
34e36c15 45
7e7ab367 46 struct msi_bitmap bitmap;
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47
48 struct list_head list; /* support multiple MSI banks */
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49
50 phandle phandle;
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51};
52
53#endif /* _POWERPC_SYSDEV_FSL_MSI_H */
54
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