Commit | Line | Data |
---|---|---|
b809b3e8 | 1 | /* |
5b70a097 | 2 | * MPC83xx/85xx/86xx PCI/PCIE support routing. |
b809b3e8 | 3 | * |
07e4f801 | 4 | * Copyright 2007-2012 Freescale Semiconductor, Inc. |
598804cd | 5 | * Copyright 2008-2009 MontaVista Software, Inc. |
b809b3e8 | 6 | * |
9ac4dd30 ZR |
7 | * Initial author: Xianghua Xiao <x.xiao@freescale.com> |
8 | * Recode: ZHANG WEI <wei.zhang@freescale.com> | |
9 | * Rewrite the routing for Frescale PCI and PCI Express | |
10 | * Roy Zang <tie-fei.zang@freescale.com> | |
598804cd AV |
11 | * MPC83xx PCI-Express support: |
12 | * Tony Li <tony.li@freescale.com> | |
13 | * Anton Vorontsov <avorontsov@ru.mvista.com> | |
b809b3e8 JL |
14 | * |
15 | * This program is free software; you can redistribute it and/or modify it | |
16 | * under the terms of the GNU General Public License as published by the | |
17 | * Free Software Foundation; either version 2 of the License, or (at your | |
18 | * option) any later version. | |
19 | */ | |
9ac4dd30 | 20 | #include <linux/kernel.h> |
b809b3e8 | 21 | #include <linux/pci.h> |
9ac4dd30 ZR |
22 | #include <linux/delay.h> |
23 | #include <linux/string.h> | |
666db563 | 24 | #include <linux/fsl/edac.h> |
9ac4dd30 | 25 | #include <linux/init.h> |
48b16180 | 26 | #include <linux/interrupt.h> |
95f72d1e | 27 | #include <linux/memblock.h> |
54c18193 | 28 | #include <linux/log2.h> |
666db563 | 29 | #include <linux/platform_device.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
48b16180 WD |
31 | #include <linux/suspend.h> |
32 | #include <linux/syscore_ops.h> | |
4e0e3435 | 33 | #include <linux/uaccess.h> |
b809b3e8 | 34 | |
b809b3e8 JL |
35 | #include <asm/io.h> |
36 | #include <asm/prom.h> | |
b809b3e8 | 37 | #include <asm/pci-bridge.h> |
4e0e3435 | 38 | #include <asm/ppc-pci.h> |
9ac4dd30 | 39 | #include <asm/machdep.h> |
4e0e3435 HJ |
40 | #include <asm/disassemble.h> |
41 | #include <asm/ppc-opcode.h> | |
b809b3e8 | 42 | #include <sysdev/fsl_soc.h> |
55c44991 | 43 | #include <sysdev/fsl_pci.h> |
b809b3e8 | 44 | |
b8f44ec2 | 45 | static int fsl_pcie_bus_fixup, is_mpc83xx_pci; |
598804cd | 46 | |
bbd234b1 | 47 | static void quirk_fsl_pcie_early(struct pci_dev *dev) |
598804cd | 48 | { |
59c58c32 | 49 | u8 hdr_type; |
470788d4 | 50 | |
598804cd | 51 | /* if we aren't a PCIe don't bother */ |
f0308261 | 52 | if (!pci_is_pcie(dev)) |
598804cd AV |
53 | return; |
54 | ||
470788d4 | 55 | /* if we aren't in host mode don't bother */ |
59c58c32 ML |
56 | pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type); |
57 | if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) | |
470788d4 KG |
58 | return; |
59 | ||
598804cd AV |
60 | dev->class = PCI_CLASS_BRIDGE_PCI << 8; |
61 | fsl_pcie_bus_fixup = 1; | |
62 | return; | |
63 | } | |
64 | ||
50d8f87d RI |
65 | static int fsl_indirect_read_config(struct pci_bus *, unsigned int, |
66 | int, int, u32 *); | |
67 | ||
68 | static int fsl_pcie_check_link(struct pci_controller *hose) | |
598804cd | 69 | { |
50d8f87d | 70 | u32 val = 0; |
598804cd | 71 | |
34642bbb | 72 | if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) { |
6d5f6a0e KP |
73 | if (hose->ops->read == fsl_indirect_read_config) |
74 | __indirect_read_config(hose, hose->first_busno, 0, | |
75 | PCIE_LTSSM, 4, &val); | |
76 | else | |
50d8f87d | 77 | early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val); |
34642bbb KG |
78 | if (val < PCIE_LTSSM_L0) |
79 | return 1; | |
80 | } else { | |
81 | struct ccsr_pci __iomem *pci = hose->private_data; | |
82 | /* for PCIe IP rev 3.0 or greater use CSR0 for link state */ | |
83 | val = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK) | |
84 | >> PEX_CSR0_LTSSM_SHIFT; | |
85 | if (val != PEX_CSR0_LTSSM_L0) | |
86 | return 1; | |
cc6ea0dd | 87 | } |
cc6ea0dd | 88 | |
598804cd AV |
89 | return 0; |
90 | } | |
91 | ||
50d8f87d RI |
92 | static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int devfn, |
93 | int offset, int len, u32 *val) | |
94 | { | |
95 | struct pci_controller *hose = pci_bus_to_host(bus); | |
96 | ||
97 | if (fsl_pcie_check_link(hose)) | |
98 | hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; | |
99 | else | |
100 | hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK; | |
101 | ||
102 | return indirect_read_config(bus, devfn, offset, len, val); | |
103 | } | |
104 | ||
b37e1613 RI |
105 | #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) |
106 | ||
107 | static struct pci_ops fsl_indirect_pcie_ops = | |
50d8f87d RI |
108 | { |
109 | .read = fsl_indirect_read_config, | |
110 | .write = indirect_write_config, | |
111 | }; | |
112 | ||
96ea3b4a KG |
113 | #define MAX_PHYS_ADDR_BITS 40 |
114 | static u64 pci64_dma_offset = 1ull << MAX_PHYS_ADDR_BITS; | |
115 | ||
97884e00 DA |
116 | #ifdef CONFIG_SWIOTLB |
117 | static void setup_swiotlb_ops(struct pci_controller *hose) | |
118 | { | |
119 | if (ppc_swiotlb_enable) { | |
120 | hose->controller_ops.dma_dev_setup = pci_dma_dev_setup_swiotlb; | |
121 | set_pci_dma_ops(&swiotlb_dma_ops); | |
122 | } | |
123 | } | |
124 | #else | |
125 | static inline void setup_swiotlb_ops(struct pci_controller *hose) {} | |
126 | #endif | |
127 | ||
96ea3b4a KG |
128 | static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask) |
129 | { | |
130 | if (!dev->dma_mask || !dma_supported(dev, dma_mask)) | |
131 | return -EIO; | |
132 | ||
133 | /* | |
134 | * Fixup PCI devices that are able to DMA to above the physical | |
135 | * address width of the SoC such that we can address any internal | |
136 | * SoC address from across PCI if needed | |
137 | */ | |
d317ac17 | 138 | if ((dev_is_pci(dev)) && |
96ea3b4a KG |
139 | dma_mask >= DMA_BIT_MASK(MAX_PHYS_ADDR_BITS)) { |
140 | set_dma_ops(dev, &dma_direct_ops); | |
141 | set_dma_offset(dev, pci64_dma_offset); | |
142 | } | |
143 | ||
144 | *dev->dma_mask = dma_mask; | |
145 | return 0; | |
146 | } | |
147 | ||
a393d897 | 148 | static int setup_one_atmu(struct ccsr_pci __iomem *pci, |
a097a78c TP |
149 | unsigned int index, const struct resource *res, |
150 | resource_size_t offset) | |
151 | { | |
152 | resource_size_t pci_addr = res->start - offset; | |
153 | resource_size_t phys_addr = res->start; | |
28f65c11 | 154 | resource_size_t size = resource_size(res); |
a097a78c TP |
155 | u32 flags = 0x80044000; /* enable & mem R/W */ |
156 | unsigned int i; | |
157 | ||
158 | pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n", | |
159 | (u64)res->start, (u64)size); | |
160 | ||
565f3764 TP |
161 | if (res->flags & IORESOURCE_PREFETCH) |
162 | flags |= 0x10000000; /* enable relaxed ordering */ | |
163 | ||
a097a78c | 164 | for (i = 0; size > 0; i++) { |
6e4c632c | 165 | unsigned int bits = min_t(u32, ilog2(size), |
a097a78c TP |
166 | __ffs(pci_addr | phys_addr)); |
167 | ||
168 | if (index + i >= 5) | |
169 | return -1; | |
170 | ||
171 | out_be32(&pci->pow[index + i].potar, pci_addr >> 12); | |
172 | out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44); | |
173 | out_be32(&pci->pow[index + i].powbar, phys_addr >> 12); | |
174 | out_be32(&pci->pow[index + i].powar, flags | (bits - 1)); | |
175 | ||
176 | pci_addr += (resource_size_t)1U << bits; | |
177 | phys_addr += (resource_size_t)1U << bits; | |
178 | size -= (resource_size_t)1U << bits; | |
179 | } | |
180 | ||
181 | return i; | |
182 | } | |
183 | ||
1930bb5c SW |
184 | static bool is_kdump(void) |
185 | { | |
186 | struct device_node *node; | |
187 | ||
188 | node = of_find_node_by_type(NULL, "memory"); | |
189 | if (!node) { | |
190 | WARN_ON_ONCE(1); | |
191 | return false; | |
192 | } | |
193 | ||
194 | return of_property_read_bool(node, "linux,usable-memory"); | |
195 | } | |
196 | ||
9ac4dd30 | 197 | /* atmu setup for fsl pci/pcie controller */ |
34642bbb | 198 | static void setup_pci_atmu(struct pci_controller *hose) |
b809b3e8 | 199 | { |
34642bbb | 200 | struct ccsr_pci __iomem *pci = hose->private_data; |
f4154e16 | 201 | int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4; |
54c18193 | 202 | u64 mem, sz, paddr_hi = 0; |
3fd47f06 | 203 | u64 offset = 0, paddr_lo = ULLONG_MAX; |
54c18193 KG |
204 | u32 pcicsrbar = 0, pcicsrbar_sz; |
205 | u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL | | |
206 | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; | |
c22618a1 | 207 | const char *name = hose->dn->full_name; |
446bc1ff TT |
208 | const u64 *reg; |
209 | int len; | |
1930bb5c SW |
210 | bool setup_inbound; |
211 | ||
212 | /* | |
213 | * If this is kdump, we don't want to trigger a bunch of PCI | |
214 | * errors by closing the window on in-flight DMA. | |
215 | * | |
216 | * We still run most of the function's logic so that things like | |
217 | * hose->dma_window_size still get set. | |
218 | */ | |
219 | setup_inbound = !is_kdump(); | |
b809b3e8 | 220 | |
720d7aeb HR |
221 | if (of_device_is_compatible(hose->dn, "fsl,bsc9132-pcie")) { |
222 | /* | |
223 | * BSC9132 Rev1.0 has an issue where all the PEX inbound | |
224 | * windows have implemented the default target value as 0xf | |
225 | * for CCSR space.In all Freescale legacy devices the target | |
226 | * of 0xf is reserved for local memory space. 9132 Rev1.0 | |
227 | * now has local mempry space mapped to target 0x0 instead of | |
228 | * 0xf. Hence adding a workaround to remove the target 0xf | |
229 | * defined for memory space from Inbound window attributes. | |
230 | */ | |
231 | piwar &= ~PIWAR_TGI_LOCAL; | |
232 | } | |
233 | ||
9e67886b RZ |
234 | if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { |
235 | if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_2_2) { | |
236 | win_idx = 2; | |
237 | start_idx = 0; | |
238 | end_idx = 3; | |
239 | } | |
240 | } | |
241 | ||
a097a78c | 242 | /* Disable all windows (except powar0 since it's ignored) */ |
9ac4dd30 ZR |
243 | for(i = 1; i < 5; i++) |
244 | out_be32(&pci->pow[i].powar, 0); | |
1930bb5c SW |
245 | |
246 | if (setup_inbound) { | |
247 | for (i = start_idx; i < end_idx; i++) | |
248 | out_be32(&pci->piw[i].piwar, 0); | |
249 | } | |
9ac4dd30 ZR |
250 | |
251 | /* Setup outbound MEM window */ | |
a097a78c TP |
252 | for(i = 0, j = 1; i < 3; i++) { |
253 | if (!(hose->mem_resources[i].flags & IORESOURCE_MEM)) | |
254 | continue; | |
255 | ||
54c18193 KG |
256 | paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start); |
257 | paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end); | |
258 | ||
3fd47f06 BH |
259 | /* We assume all memory resources have the same offset */ |
260 | offset = hose->mem_offset[i]; | |
261 | n = setup_one_atmu(pci, j, &hose->mem_resources[i], offset); | |
a097a78c TP |
262 | |
263 | if (n < 0 || j >= 5) { | |
264 | pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i); | |
265 | hose->mem_resources[i].flags |= IORESOURCE_DISABLED; | |
266 | } else | |
267 | j += n; | |
268 | } | |
9ac4dd30 ZR |
269 | |
270 | /* Setup outbound IO window */ | |
a097a78c TP |
271 | if (hose->io_resource.flags & IORESOURCE_IO) { |
272 | if (j >= 5) { | |
273 | pr_err("Ran out of outbound PCI ATMUs for IO resource\n"); | |
274 | } else { | |
275 | pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, " | |
276 | "phy base 0x%016llx.\n", | |
28f65c11 JP |
277 | (u64)hose->io_resource.start, |
278 | (u64)resource_size(&hose->io_resource), | |
279 | (u64)hose->io_base_phys); | |
a097a78c TP |
280 | out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12)); |
281 | out_be32(&pci->pow[j].potear, 0); | |
282 | out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12)); | |
283 | /* Enable, IO R/W */ | |
284 | out_be32(&pci->pow[j].powar, 0x80088000 | |
2b4a8bd2 | 285 | | (ilog2(hose->io_resource.end |
a097a78c TP |
286 | - hose->io_resource.start + 1) - 1)); |
287 | } | |
9ac4dd30 ZR |
288 | } |
289 | ||
54c18193 | 290 | /* convert to pci address space */ |
3fd47f06 BH |
291 | paddr_hi -= offset; |
292 | paddr_lo -= offset; | |
54c18193 KG |
293 | |
294 | if (paddr_hi == paddr_lo) { | |
295 | pr_err("%s: No outbound window space\n", name); | |
04aa99cd | 296 | return; |
54c18193 KG |
297 | } |
298 | ||
299 | if (paddr_lo == 0) { | |
300 | pr_err("%s: No space for inbound window\n", name); | |
04aa99cd | 301 | return; |
54c18193 KG |
302 | } |
303 | ||
304 | /* setup PCSRBAR/PEXCSRBAR */ | |
305 | early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff); | |
306 | early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz); | |
307 | pcicsrbar_sz = ~pcicsrbar_sz + 1; | |
308 | ||
309 | if (paddr_hi < (0x100000000ull - pcicsrbar_sz) || | |
310 | (paddr_lo > 0x100000000ull)) | |
311 | pcicsrbar = 0x100000000ull - pcicsrbar_sz; | |
312 | else | |
313 | pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz; | |
314 | early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar); | |
315 | ||
316 | paddr_lo = min(paddr_lo, (u64)pcicsrbar); | |
317 | ||
318 | pr_info("%s: PCICSRBAR @ 0x%x\n", name, pcicsrbar); | |
319 | ||
320 | /* Setup inbound mem window */ | |
95f72d1e | 321 | mem = memblock_end_of_DRAM(); |
1930bb5c | 322 | pr_info("%s: end of DRAM %llx\n", __func__, mem); |
446bc1ff TT |
323 | |
324 | /* | |
325 | * The msi-address-64 property, if it exists, indicates the physical | |
326 | * address of the MSIIR register. Normally, this register is located | |
327 | * inside CCSR, so the ATMU that covers all of CCSR is used. But if | |
328 | * this property exists, then we normally need to create a new ATMU | |
329 | * for it. For now, however, we cheat. The only entity that creates | |
330 | * this property is the Freescale hypervisor, and the address is | |
331 | * specified in the partition configuration. Typically, the address | |
332 | * is located in the page immediately after the end of DDR. If so, we | |
333 | * can avoid allocating a new ATMU by extending the DDR ATMU by one | |
334 | * page. | |
335 | */ | |
336 | reg = of_get_property(hose->dn, "msi-address-64", &len); | |
337 | if (reg && (len == sizeof(u64))) { | |
338 | u64 address = be64_to_cpup(reg); | |
339 | ||
340 | if ((address >= mem) && (address < (mem + PAGE_SIZE))) { | |
341 | pr_info("%s: extending DDR ATMU to cover MSIIR", name); | |
342 | mem += PAGE_SIZE; | |
343 | } else { | |
344 | /* TODO: Create a new ATMU for MSIIR */ | |
345 | pr_warn("%s: msi-address-64 address of %llx is " | |
346 | "unsupported\n", name, address); | |
347 | } | |
348 | } | |
349 | ||
54c18193 | 350 | sz = min(mem, paddr_lo); |
2b4a8bd2 | 351 | mem_log = ilog2(sz); |
54c18193 KG |
352 | |
353 | /* PCIe can overmap inbound & outbound since RX & TX are separated */ | |
354 | if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { | |
355 | /* Size window to exact size if power-of-two or one size up */ | |
356 | if ((1ull << mem_log) != mem) { | |
2d49c42a | 357 | mem_log++; |
54c18193 KG |
358 | if ((1ull << mem_log) > mem) |
359 | pr_info("%s: Setting PCI inbound window " | |
360 | "greater than memory size\n", name); | |
54c18193 KG |
361 | } |
362 | ||
f4154e16 | 363 | piwar |= ((mem_log - 1) & PIWAR_SZ_MASK); |
54c18193 | 364 | |
1930bb5c SW |
365 | if (setup_inbound) { |
366 | /* Setup inbound memory window */ | |
367 | out_be32(&pci->piw[win_idx].pitar, 0x00000000); | |
368 | out_be32(&pci->piw[win_idx].piwbar, 0x00000000); | |
369 | out_be32(&pci->piw[win_idx].piwar, piwar); | |
370 | } | |
54c18193 | 371 | |
1930bb5c | 372 | win_idx--; |
54c18193 KG |
373 | hose->dma_window_base_cur = 0x00000000; |
374 | hose->dma_window_size = (resource_size_t)sz; | |
96ea3b4a KG |
375 | |
376 | /* | |
377 | * if we have >4G of memory setup second PCI inbound window to | |
378 | * let devices that are 64-bit address capable to work w/o | |
379 | * SWIOTLB and access the full range of memory | |
380 | */ | |
381 | if (sz != mem) { | |
2b4a8bd2 | 382 | mem_log = ilog2(mem); |
96ea3b4a KG |
383 | |
384 | /* Size window up if we dont fit in exact power-of-2 */ | |
385 | if ((1ull << mem_log) != mem) | |
386 | mem_log++; | |
387 | ||
388 | piwar = (piwar & ~PIWAR_SZ_MASK) | (mem_log - 1); | |
389 | ||
1930bb5c SW |
390 | if (setup_inbound) { |
391 | /* Setup inbound memory window */ | |
392 | out_be32(&pci->piw[win_idx].pitar, 0x00000000); | |
393 | out_be32(&pci->piw[win_idx].piwbear, | |
394 | pci64_dma_offset >> 44); | |
395 | out_be32(&pci->piw[win_idx].piwbar, | |
396 | pci64_dma_offset >> 12); | |
397 | out_be32(&pci->piw[win_idx].piwar, piwar); | |
398 | } | |
96ea3b4a KG |
399 | |
400 | /* | |
401 | * install our own dma_set_mask handler to fixup dma_ops | |
402 | * and dma_offset | |
403 | */ | |
404 | ppc_md.dma_set_mask = fsl_pci_dma_set_mask; | |
405 | ||
406 | pr_info("%s: Setup 64-bit PCI DMA window\n", name); | |
407 | } | |
54c18193 KG |
408 | } else { |
409 | u64 paddr = 0; | |
410 | ||
1930bb5c SW |
411 | if (setup_inbound) { |
412 | /* Setup inbound memory window */ | |
413 | out_be32(&pci->piw[win_idx].pitar, paddr >> 12); | |
414 | out_be32(&pci->piw[win_idx].piwbar, paddr >> 12); | |
415 | out_be32(&pci->piw[win_idx].piwar, | |
416 | (piwar | (mem_log - 1))); | |
417 | } | |
54c18193 | 418 | |
1930bb5c | 419 | win_idx--; |
54c18193 KG |
420 | paddr += 1ull << mem_log; |
421 | sz -= 1ull << mem_log; | |
422 | ||
423 | if (sz) { | |
2b4a8bd2 | 424 | mem_log = ilog2(sz); |
54c18193 KG |
425 | piwar |= (mem_log - 1); |
426 | ||
1930bb5c SW |
427 | if (setup_inbound) { |
428 | out_be32(&pci->piw[win_idx].pitar, | |
429 | paddr >> 12); | |
430 | out_be32(&pci->piw[win_idx].piwbar, | |
431 | paddr >> 12); | |
432 | out_be32(&pci->piw[win_idx].piwar, piwar); | |
433 | } | |
54c18193 | 434 | |
1930bb5c | 435 | win_idx--; |
54c18193 KG |
436 | paddr += 1ull << mem_log; |
437 | } | |
438 | ||
439 | hose->dma_window_base_cur = 0x00000000; | |
440 | hose->dma_window_size = (resource_size_t)paddr; | |
441 | } | |
a097a78c | 442 | |
54c18193 | 443 | if (hose->dma_window_size < mem) { |
c45e9183 KH |
444 | #ifdef CONFIG_SWIOTLB |
445 | ppc_swiotlb_enable = 1; | |
446 | #else | |
54c18193 KG |
447 | pr_err("%s: ERROR: Memory size exceeds PCI ATMU ability to " |
448 | "map - enable CONFIG_SWIOTLB to avoid dma errors.\n", | |
449 | name); | |
450 | #endif | |
451 | /* adjusting outbound windows could reclaim space in mem map */ | |
452 | if (paddr_hi < 0xffffffffull) | |
453 | pr_warning("%s: WARNING: Outbound window cfg leaves " | |
454 | "gaps in memory map. Adjusting the memory map " | |
455 | "could reduce unnecessary bounce buffering.\n", | |
456 | name); | |
457 | ||
458 | pr_info("%s: DMA window size is 0x%llx\n", name, | |
459 | (u64)hose->dma_window_size); | |
460 | } | |
b809b3e8 JL |
461 | } |
462 | ||
c9dadffb | 463 | static void __init setup_pci_cmd(struct pci_controller *hose) |
b809b3e8 | 464 | { |
b809b3e8 | 465 | u16 cmd; |
eb12af43 KG |
466 | int cap_x; |
467 | ||
b809b3e8 JL |
468 | early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd); |
469 | cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | |
9ac4dd30 | 470 | | PCI_COMMAND_IO; |
b809b3e8 | 471 | early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd); |
eb12af43 KG |
472 | |
473 | cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX); | |
474 | if (cap_x) { | |
475 | int pci_x_cmd = cap_x + PCI_X_CMD; | |
476 | cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ | |
477 | | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; | |
478 | early_write_config_word(hose, 0, 0, pci_x_cmd, cmd); | |
479 | } else { | |
480 | early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80); | |
481 | } | |
9ad494f6 KG |
482 | } |
483 | ||
6c0a11c1 KG |
484 | void fsl_pcibios_fixup_bus(struct pci_bus *bus) |
485 | { | |
8206a110 | 486 | struct pci_controller *hose = pci_bus_to_host(bus); |
13635dfd BH |
487 | int i, is_pcie = 0, no_link; |
488 | ||
489 | /* The root complex bridge comes up with bogus resources, | |
490 | * we copy the PHB ones in. | |
491 | * | |
492 | * With the current generic PCI code, the PHB bus no longer | |
493 | * has bus->resource[0..4] set, so things are a bit more | |
494 | * tricky. | |
495 | */ | |
496 | ||
497 | if (fsl_pcie_bus_fixup) | |
498 | is_pcie = early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP); | |
499 | no_link = !!(hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK); | |
500 | ||
501 | if (bus->parent == hose->bus && (is_pcie || no_link)) { | |
502 | for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; ++i) { | |
72b122cc | 503 | struct resource *res = bus->resource[i]; |
13635dfd BH |
504 | struct resource *par; |
505 | ||
506 | if (!res) | |
507 | continue; | |
508 | if (i == 0) | |
509 | par = &hose->io_resource; | |
510 | else if (i < 4) | |
511 | par = &hose->mem_resources[i-1]; | |
512 | else par = NULL; | |
513 | ||
514 | res->start = par ? par->start : 0; | |
515 | res->end = par ? par->end : 0; | |
516 | res->flags = par ? par->flags : 0; | |
6c0a11c1 KG |
517 | } |
518 | } | |
519 | } | |
520 | ||
1e83bf87 | 521 | int fsl_add_bridge(struct platform_device *pdev, int is_primary) |
b809b3e8 JL |
522 | { |
523 | int len; | |
524 | struct pci_controller *hose; | |
525 | struct resource rsrc; | |
8efca493 | 526 | const int *bus_range; |
59c58c32 | 527 | u8 hdr_type, progif; |
52c5affc | 528 | struct device_node *dev; |
34642bbb | 529 | struct ccsr_pci __iomem *pci; |
52c5affc VS |
530 | |
531 | dev = pdev->dev.of_node; | |
b809b3e8 | 532 | |
ef1fd2df PK |
533 | if (!of_device_is_available(dev)) { |
534 | pr_warning("%s: disabled\n", dev->full_name); | |
535 | return -ENODEV; | |
536 | } | |
537 | ||
9ac4dd30 | 538 | pr_debug("Adding PCI host bridge %s\n", dev->full_name); |
b809b3e8 JL |
539 | |
540 | /* Fetch host bridge registers address */ | |
9ac4dd30 ZR |
541 | if (of_address_to_resource(dev, 0, &rsrc)) { |
542 | printk(KERN_WARNING "Can't get pci register base!"); | |
543 | return -ENOMEM; | |
544 | } | |
b809b3e8 JL |
545 | |
546 | /* Get bus range if any */ | |
e2eb6392 | 547 | bus_range = of_get_property(dev, "bus-range", &len); |
b809b3e8 JL |
548 | if (bus_range == NULL || len < 2 * sizeof(int)) |
549 | printk(KERN_WARNING "Can't get bus-range for %s, assume" | |
9ac4dd30 | 550 | " bus 0\n", dev->full_name); |
b809b3e8 | 551 | |
0e47ff1c | 552 | pci_add_flags(PCI_REASSIGN_ALL_BUS); |
dbf8471f | 553 | hose = pcibios_alloc_controller(dev); |
b809b3e8 JL |
554 | if (!hose) |
555 | return -ENOMEM; | |
dbf8471f | 556 | |
52c5affc VS |
557 | /* set platform device as the parent */ |
558 | hose->parent = &pdev->dev; | |
b809b3e8 | 559 | hose->first_busno = bus_range ? bus_range[0] : 0x0; |
bf7c036f | 560 | hose->last_busno = bus_range ? bus_range[1] : 0xff; |
b809b3e8 | 561 | |
34642bbb KG |
562 | pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n", |
563 | (u64)rsrc.start, (u64)resource_size(&rsrc)); | |
564 | ||
565 | pci = hose->private_data = ioremap(rsrc.start, resource_size(&rsrc)); | |
566 | if (!hose->private_data) | |
567 | goto no_bridge; | |
568 | ||
b37e1613 RI |
569 | setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4, |
570 | PPC_INDIRECT_TYPE_BIG_ENDIAN); | |
08871c09 | 571 | |
34642bbb KG |
572 | if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0) |
573 | hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK; | |
574 | ||
59c58c32 | 575 | if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { |
b37e1613 RI |
576 | /* use fsl_indirect_read_config for PCIe */ |
577 | hose->ops = &fsl_indirect_pcie_ops; | |
59c58c32 ML |
578 | /* For PCIE read HEADER_TYPE to identify controler mode */ |
579 | early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &hdr_type); | |
580 | if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) | |
581 | goto no_bridge; | |
582 | ||
583 | } else { | |
584 | /* For PCI read PROG to identify controller mode */ | |
585 | early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif); | |
00406e87 AS |
586 | if ((progif & 1) && |
587 | !of_property_read_bool(dev, "fsl,pci-agent-force-enum")) | |
59c58c32 | 588 | goto no_bridge; |
08871c09 PK |
589 | } |
590 | ||
9ac4dd30 | 591 | setup_pci_cmd(hose); |
b809b3e8 | 592 | |
9ac4dd30 | 593 | /* check PCI express link status */ |
957ecffc | 594 | if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { |
7659c038 | 595 | hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG | |
957ecffc | 596 | PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS; |
34642bbb | 597 | if (fsl_pcie_check_link(hose)) |
957ecffc KG |
598 | hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; |
599 | } | |
b809b3e8 | 600 | |
df3c9019 | 601 | printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. " |
9ac4dd30 ZR |
602 | "Firmware bus number: %d->%d\n", |
603 | (unsigned long long)rsrc.start, hose->first_busno, | |
604 | hose->last_busno); | |
b809b3e8 | 605 | |
9ac4dd30 | 606 | pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", |
b809b3e8 JL |
607 | hose, hose->cfg_addr, hose->cfg_data); |
608 | ||
609 | /* Interpret the "ranges" property */ | |
610 | /* This also maps the I/O region and sets isa_io/mem_base */ | |
9ac4dd30 | 611 | pci_process_bridge_OF_ranges(hose, dev, is_primary); |
b809b3e8 JL |
612 | |
613 | /* Setup PEX window registers */ | |
34642bbb | 614 | setup_pci_atmu(hose); |
b809b3e8 | 615 | |
97884e00 DA |
616 | /* Set up controller operations */ |
617 | setup_swiotlb_ops(hose); | |
618 | ||
b809b3e8 | 619 | return 0; |
59c58c32 ML |
620 | |
621 | no_bridge: | |
34642bbb | 622 | iounmap(hose->private_data); |
59c58c32 ML |
623 | /* unmap cfg_data & cfg_addr separately if not on same page */ |
624 | if (((unsigned long)hose->cfg_data & PAGE_MASK) != | |
625 | ((unsigned long)hose->cfg_addr & PAGE_MASK)) | |
626 | iounmap(hose->cfg_data); | |
627 | iounmap(hose->cfg_addr); | |
628 | pcibios_free_controller(hose); | |
629 | return -ENODEV; | |
b809b3e8 | 630 | } |
5753c082 | 631 | #endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */ |
76fe1ffc | 632 | |
bbd234b1 CL |
633 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, |
634 | quirk_fsl_pcie_early); | |
598804cd | 635 | |
470788d4 | 636 | #if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x) |
598804cd AV |
637 | struct mpc83xx_pcie_priv { |
638 | void __iomem *cfg_type0; | |
639 | void __iomem *cfg_type1; | |
640 | u32 dev_base; | |
641 | }; | |
642 | ||
b8f44ec2 KG |
643 | struct pex_inbound_window { |
644 | u32 ar; | |
645 | u32 tar; | |
646 | u32 barl; | |
647 | u32 barh; | |
648 | }; | |
649 | ||
598804cd AV |
650 | /* |
651 | * With the convention of u-boot, the PCIE outbound window 0 serves | |
652 | * as configuration transactions outbound. | |
653 | */ | |
654 | #define PEX_OUTWIN0_BAR 0xCA4 | |
655 | #define PEX_OUTWIN0_TAL 0xCA8 | |
656 | #define PEX_OUTWIN0_TAH 0xCAC | |
b8f44ec2 KG |
657 | #define PEX_RC_INWIN_BASE 0xE60 |
658 | #define PEX_RCIWARn_EN 0x1 | |
598804cd AV |
659 | |
660 | static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn) | |
661 | { | |
8206a110 | 662 | struct pci_controller *hose = pci_bus_to_host(bus); |
598804cd AV |
663 | |
664 | if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) | |
665 | return PCIBIOS_DEVICE_NOT_FOUND; | |
666 | /* | |
667 | * Workaround for the HW bug: for Type 0 configure transactions the | |
668 | * PCI-E controller does not check the device number bits and just | |
669 | * assumes that the device number bits are 0. | |
670 | */ | |
671 | if (bus->number == hose->first_busno || | |
672 | bus->primary == hose->first_busno) { | |
673 | if (devfn & 0xf8) | |
674 | return PCIBIOS_DEVICE_NOT_FOUND; | |
675 | } | |
676 | ||
677 | if (ppc_md.pci_exclude_device) { | |
678 | if (ppc_md.pci_exclude_device(hose, bus->number, devfn)) | |
679 | return PCIBIOS_DEVICE_NOT_FOUND; | |
680 | } | |
681 | ||
682 | return PCIBIOS_SUCCESSFUL; | |
683 | } | |
684 | ||
685 | static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus, | |
686 | unsigned int devfn, int offset) | |
687 | { | |
8206a110 | 688 | struct pci_controller *hose = pci_bus_to_host(bus); |
598804cd | 689 | struct mpc83xx_pcie_priv *pcie = hose->dn->data; |
f93611fa | 690 | u32 dev_base = bus->number << 24 | devfn << 16; |
598804cd AV |
691 | int ret; |
692 | ||
693 | ret = mpc83xx_pcie_exclude_device(bus, devfn); | |
694 | if (ret) | |
695 | return NULL; | |
696 | ||
697 | offset &= 0xfff; | |
698 | ||
699 | /* Type 0 */ | |
700 | if (bus->number == hose->first_busno) | |
701 | return pcie->cfg_type0 + offset; | |
702 | ||
703 | if (pcie->dev_base == dev_base) | |
704 | goto mapped; | |
705 | ||
706 | out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base); | |
707 | ||
708 | pcie->dev_base = dev_base; | |
709 | mapped: | |
710 | return pcie->cfg_type1 + offset; | |
711 | } | |
712 | ||
598804cd AV |
713 | static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn, |
714 | int offset, int len, u32 val) | |
715 | { | |
f93611fa | 716 | struct pci_controller *hose = pci_bus_to_host(bus); |
598804cd | 717 | |
f93611fa AV |
718 | /* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */ |
719 | if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno) | |
720 | val &= 0xffffff00; | |
721 | ||
933d275f | 722 | return pci_generic_config_write(bus, devfn, offset, len, val); |
598804cd AV |
723 | } |
724 | ||
725 | static struct pci_ops mpc83xx_pcie_ops = { | |
933d275f RH |
726 | .map_bus = mpc83xx_pcie_remap_cfg, |
727 | .read = pci_generic_config_read, | |
598804cd AV |
728 | .write = mpc83xx_pcie_write_config, |
729 | }; | |
730 | ||
731 | static int __init mpc83xx_pcie_setup(struct pci_controller *hose, | |
732 | struct resource *reg) | |
733 | { | |
734 | struct mpc83xx_pcie_priv *pcie; | |
735 | u32 cfg_bar; | |
736 | int ret = -ENOMEM; | |
737 | ||
738 | pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL); | |
739 | if (!pcie) | |
740 | return ret; | |
741 | ||
742 | pcie->cfg_type0 = ioremap(reg->start, resource_size(reg)); | |
743 | if (!pcie->cfg_type0) | |
744 | goto err0; | |
745 | ||
746 | cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR); | |
747 | if (!cfg_bar) { | |
748 | /* PCI-E isn't configured. */ | |
749 | ret = -ENODEV; | |
750 | goto err1; | |
751 | } | |
752 | ||
753 | pcie->cfg_type1 = ioremap(cfg_bar, 0x1000); | |
754 | if (!pcie->cfg_type1) | |
755 | goto err1; | |
756 | ||
757 | WARN_ON(hose->dn->data); | |
758 | hose->dn->data = pcie; | |
759 | hose->ops = &mpc83xx_pcie_ops; | |
34642bbb | 760 | hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK; |
598804cd AV |
761 | |
762 | out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0); | |
763 | out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0); | |
764 | ||
34642bbb | 765 | if (fsl_pcie_check_link(hose)) |
598804cd AV |
766 | hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; |
767 | ||
768 | return 0; | |
769 | err1: | |
770 | iounmap(pcie->cfg_type0); | |
771 | err0: | |
772 | kfree(pcie); | |
773 | return ret; | |
774 | ||
775 | } | |
776 | ||
76fe1ffc JR |
777 | int __init mpc83xx_add_bridge(struct device_node *dev) |
778 | { | |
598804cd | 779 | int ret; |
76fe1ffc JR |
780 | int len; |
781 | struct pci_controller *hose; | |
5b70a097 JR |
782 | struct resource rsrc_reg; |
783 | struct resource rsrc_cfg; | |
76fe1ffc | 784 | const int *bus_range; |
5b70a097 | 785 | int primary; |
76fe1ffc | 786 | |
b8f44ec2 KG |
787 | is_mpc83xx_pci = 1; |
788 | ||
598804cd AV |
789 | if (!of_device_is_available(dev)) { |
790 | pr_warning("%s: disabled by the firmware.\n", | |
791 | dev->full_name); | |
792 | return -ENODEV; | |
793 | } | |
76fe1ffc JR |
794 | pr_debug("Adding PCI host bridge %s\n", dev->full_name); |
795 | ||
796 | /* Fetch host bridge registers address */ | |
5b70a097 JR |
797 | if (of_address_to_resource(dev, 0, &rsrc_reg)) { |
798 | printk(KERN_WARNING "Can't get pci register base!\n"); | |
799 | return -ENOMEM; | |
800 | } | |
801 | ||
802 | memset(&rsrc_cfg, 0, sizeof(rsrc_cfg)); | |
803 | ||
804 | if (of_address_to_resource(dev, 1, &rsrc_cfg)) { | |
805 | printk(KERN_WARNING | |
806 | "No pci config register base in dev tree, " | |
807 | "using default\n"); | |
808 | /* | |
809 | * MPC83xx supports up to two host controllers | |
810 | * one at 0x8500 has config space registers at 0x8300 | |
811 | * one at 0x8600 has config space registers at 0x8380 | |
812 | */ | |
813 | if ((rsrc_reg.start & 0xfffff) == 0x8500) | |
814 | rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300; | |
815 | else if ((rsrc_reg.start & 0xfffff) == 0x8600) | |
816 | rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380; | |
817 | } | |
818 | /* | |
819 | * Controller at offset 0x8500 is primary | |
820 | */ | |
821 | if ((rsrc_reg.start & 0xfffff) == 0x8500) | |
822 | primary = 1; | |
823 | else | |
824 | primary = 0; | |
76fe1ffc JR |
825 | |
826 | /* Get bus range if any */ | |
827 | bus_range = of_get_property(dev, "bus-range", &len); | |
828 | if (bus_range == NULL || len < 2 * sizeof(int)) { | |
829 | printk(KERN_WARNING "Can't get bus-range for %s, assume" | |
830 | " bus 0\n", dev->full_name); | |
831 | } | |
832 | ||
0e47ff1c | 833 | pci_add_flags(PCI_REASSIGN_ALL_BUS); |
76fe1ffc JR |
834 | hose = pcibios_alloc_controller(dev); |
835 | if (!hose) | |
836 | return -ENOMEM; | |
837 | ||
838 | hose->first_busno = bus_range ? bus_range[0] : 0; | |
839 | hose->last_busno = bus_range ? bus_range[1] : 0xff; | |
840 | ||
598804cd AV |
841 | if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) { |
842 | ret = mpc83xx_pcie_setup(hose, &rsrc_reg); | |
843 | if (ret) | |
844 | goto err0; | |
845 | } else { | |
b37e1613 RI |
846 | setup_indirect_pci(hose, rsrc_cfg.start, |
847 | rsrc_cfg.start + 4, 0); | |
598804cd | 848 | } |
76fe1ffc | 849 | |
35225802 | 850 | printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. " |
76fe1ffc | 851 | "Firmware bus number: %d->%d\n", |
5b70a097 | 852 | (unsigned long long)rsrc_reg.start, hose->first_busno, |
76fe1ffc JR |
853 | hose->last_busno); |
854 | ||
855 | pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", | |
856 | hose, hose->cfg_addr, hose->cfg_data); | |
857 | ||
858 | /* Interpret the "ranges" property */ | |
859 | /* This also maps the I/O region and sets isa_io/mem_base */ | |
860 | pci_process_bridge_OF_ranges(hose, dev, primary); | |
861 | ||
862 | return 0; | |
598804cd AV |
863 | err0: |
864 | pcibios_free_controller(hose); | |
865 | return ret; | |
76fe1ffc JR |
866 | } |
867 | #endif /* CONFIG_PPC_83xx */ | |
b8f44ec2 KG |
868 | |
869 | u64 fsl_pci_immrbar_base(struct pci_controller *hose) | |
870 | { | |
871 | #ifdef CONFIG_PPC_83xx | |
872 | if (is_mpc83xx_pci) { | |
873 | struct mpc83xx_pcie_priv *pcie = hose->dn->data; | |
874 | struct pex_inbound_window *in; | |
875 | int i; | |
876 | ||
877 | /* Walk the Root Complex Inbound windows to match IMMR base */ | |
878 | in = pcie->cfg_type0 + PEX_RC_INWIN_BASE; | |
879 | for (i = 0; i < 4; i++) { | |
880 | /* not enabled, skip */ | |
3894817f HS |
881 | if (!(in_le32(&in[i].ar) & PEX_RCIWARn_EN)) |
882 | continue; | |
b8f44ec2 KG |
883 | |
884 | if (get_immrbase() == in_le32(&in[i].tar)) | |
885 | return (u64)in_le32(&in[i].barh) << 32 | | |
886 | in_le32(&in[i].barl); | |
887 | } | |
888 | ||
889 | printk(KERN_WARNING "could not find PCI BAR matching IMMR\n"); | |
890 | } | |
891 | #endif | |
892 | ||
893 | #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) | |
894 | if (!is_mpc83xx_pci) { | |
895 | u32 base; | |
896 | ||
897 | pci_bus_read_config_dword(hose->bus, | |
898 | PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base); | |
a424b97b ML |
899 | |
900 | /* | |
901 | * For PEXCSRBAR, bit 3-0 indicate prefetchable and | |
902 | * address type. So when getting base address, these | |
903 | * bits should be masked | |
904 | */ | |
905 | base &= PCI_BASE_ADDRESS_MEM_MASK; | |
906 | ||
b8f44ec2 KG |
907 | return base; |
908 | } | |
909 | #endif | |
910 | ||
911 | return 0; | |
912 | } | |
07e4f801 | 913 | |
4e0e3435 HJ |
914 | #ifdef CONFIG_E500 |
915 | static int mcheck_handle_load(struct pt_regs *regs, u32 inst) | |
916 | { | |
917 | unsigned int rd, ra, rb, d; | |
918 | ||
919 | rd = get_rt(inst); | |
920 | ra = get_ra(inst); | |
921 | rb = get_rb(inst); | |
922 | d = get_d(inst); | |
923 | ||
924 | switch (get_op(inst)) { | |
925 | case 31: | |
926 | switch (get_xop(inst)) { | |
927 | case OP_31_XOP_LWZX: | |
928 | case OP_31_XOP_LWBRX: | |
929 | regs->gpr[rd] = 0xffffffff; | |
930 | break; | |
931 | ||
932 | case OP_31_XOP_LWZUX: | |
933 | regs->gpr[rd] = 0xffffffff; | |
934 | regs->gpr[ra] += regs->gpr[rb]; | |
935 | break; | |
936 | ||
937 | case OP_31_XOP_LBZX: | |
938 | regs->gpr[rd] = 0xff; | |
939 | break; | |
940 | ||
941 | case OP_31_XOP_LBZUX: | |
942 | regs->gpr[rd] = 0xff; | |
943 | regs->gpr[ra] += regs->gpr[rb]; | |
944 | break; | |
945 | ||
946 | case OP_31_XOP_LHZX: | |
947 | case OP_31_XOP_LHBRX: | |
948 | regs->gpr[rd] = 0xffff; | |
949 | break; | |
950 | ||
951 | case OP_31_XOP_LHZUX: | |
952 | regs->gpr[rd] = 0xffff; | |
953 | regs->gpr[ra] += regs->gpr[rb]; | |
954 | break; | |
955 | ||
956 | case OP_31_XOP_LHAX: | |
957 | regs->gpr[rd] = ~0UL; | |
958 | break; | |
959 | ||
960 | case OP_31_XOP_LHAUX: | |
961 | regs->gpr[rd] = ~0UL; | |
962 | regs->gpr[ra] += regs->gpr[rb]; | |
963 | break; | |
964 | ||
965 | default: | |
966 | return 0; | |
967 | } | |
968 | break; | |
969 | ||
970 | case OP_LWZ: | |
971 | regs->gpr[rd] = 0xffffffff; | |
972 | break; | |
973 | ||
974 | case OP_LWZU: | |
975 | regs->gpr[rd] = 0xffffffff; | |
976 | regs->gpr[ra] += (s16)d; | |
977 | break; | |
978 | ||
979 | case OP_LBZ: | |
980 | regs->gpr[rd] = 0xff; | |
981 | break; | |
982 | ||
983 | case OP_LBZU: | |
984 | regs->gpr[rd] = 0xff; | |
985 | regs->gpr[ra] += (s16)d; | |
986 | break; | |
987 | ||
988 | case OP_LHZ: | |
989 | regs->gpr[rd] = 0xffff; | |
990 | break; | |
991 | ||
992 | case OP_LHZU: | |
993 | regs->gpr[rd] = 0xffff; | |
994 | regs->gpr[ra] += (s16)d; | |
995 | break; | |
996 | ||
997 | case OP_LHA: | |
998 | regs->gpr[rd] = ~0UL; | |
999 | break; | |
1000 | ||
1001 | case OP_LHAU: | |
1002 | regs->gpr[rd] = ~0UL; | |
1003 | regs->gpr[ra] += (s16)d; | |
1004 | break; | |
1005 | ||
1006 | default: | |
1007 | return 0; | |
1008 | } | |
1009 | ||
1010 | return 1; | |
1011 | } | |
1012 | ||
1013 | static int is_in_pci_mem_space(phys_addr_t addr) | |
1014 | { | |
1015 | struct pci_controller *hose; | |
1016 | struct resource *res; | |
1017 | int i; | |
1018 | ||
1019 | list_for_each_entry(hose, &hose_list, list_node) { | |
1020 | if (!(hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG)) | |
1021 | continue; | |
1022 | ||
1023 | for (i = 0; i < 3; i++) { | |
1024 | res = &hose->mem_resources[i]; | |
1025 | if ((res->flags & IORESOURCE_MEM) && | |
1026 | addr >= res->start && addr <= res->end) | |
1027 | return 1; | |
1028 | } | |
1029 | } | |
1030 | return 0; | |
1031 | } | |
1032 | ||
1033 | int fsl_pci_mcheck_exception(struct pt_regs *regs) | |
1034 | { | |
1035 | u32 inst; | |
1036 | int ret; | |
1037 | phys_addr_t addr = 0; | |
1038 | ||
1039 | /* Let KVM/QEMU deal with the exception */ | |
1040 | if (regs->msr & MSR_GS) | |
1041 | return 0; | |
1042 | ||
1043 | #ifdef CONFIG_PHYS_64BIT | |
1044 | addr = mfspr(SPRN_MCARU); | |
1045 | addr <<= 32; | |
1046 | #endif | |
1047 | addr += mfspr(SPRN_MCAR); | |
1048 | ||
1049 | if (is_in_pci_mem_space(addr)) { | |
1050 | if (user_mode(regs)) { | |
1051 | pagefault_disable(); | |
1052 | ret = get_user(regs->nip, &inst); | |
1053 | pagefault_enable(); | |
1054 | } else { | |
0ab32b6f | 1055 | ret = probe_kernel_address((void *)regs->nip, inst); |
4e0e3435 HJ |
1056 | } |
1057 | ||
072daeed | 1058 | if (!ret && mcheck_handle_load(regs, inst)) { |
4e0e3435 HJ |
1059 | regs->nip += 4; |
1060 | return 1; | |
1061 | } | |
1062 | } | |
1063 | ||
1064 | return 0; | |
1065 | } | |
1066 | #endif | |
1067 | ||
07e4f801 SW |
1068 | #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) |
1069 | static const struct of_device_id pci_ids[] = { | |
1070 | { .compatible = "fsl,mpc8540-pci", }, | |
1071 | { .compatible = "fsl,mpc8548-pcie", }, | |
1072 | { .compatible = "fsl,mpc8610-pci", }, | |
1073 | { .compatible = "fsl,mpc8641-pcie", }, | |
d064f30e | 1074 | { .compatible = "fsl,qoriq-pcie", }, |
14bdc913 TT |
1075 | { .compatible = "fsl,qoriq-pcie-v2.1", }, |
1076 | { .compatible = "fsl,qoriq-pcie-v2.2", }, | |
1077 | { .compatible = "fsl,qoriq-pcie-v2.3", }, | |
1078 | { .compatible = "fsl,qoriq-pcie-v2.4", }, | |
cc6ea0dd | 1079 | { .compatible = "fsl,qoriq-pcie-v3.0", }, |
14bdc913 TT |
1080 | |
1081 | /* | |
1082 | * The following entries are for compatibility with older device | |
1083 | * trees. | |
1084 | */ | |
07e4f801 | 1085 | { .compatible = "fsl,p1022-pcie", }, |
07e4f801 | 1086 | { .compatible = "fsl,p4080-pcie", }, |
14bdc913 | 1087 | |
07e4f801 SW |
1088 | {}, |
1089 | }; | |
1090 | ||
1091 | struct device_node *fsl_pci_primary; | |
1092 | ||
905e75c4 | 1093 | void fsl_pci_assign_primary(void) |
07e4f801 | 1094 | { |
905e75c4 | 1095 | struct device_node *np; |
07e4f801 SW |
1096 | |
1097 | /* Callers can specify the primary bus using other means. */ | |
905e75c4 JH |
1098 | if (fsl_pci_primary) |
1099 | return; | |
1100 | ||
1101 | /* If a PCI host bridge contains an ISA node, it's primary. */ | |
1102 | np = of_find_node_by_type(NULL, "isa"); | |
1103 | while ((fsl_pci_primary = of_get_parent(np))) { | |
1104 | of_node_put(np); | |
1105 | np = fsl_pci_primary; | |
1106 | ||
1107 | if (of_match_node(pci_ids, np) && of_device_is_available(np)) | |
1108 | return; | |
07e4f801 SW |
1109 | } |
1110 | ||
905e75c4 JH |
1111 | /* |
1112 | * If there's no PCI host bridge with ISA, arbitrarily | |
1113 | * designate one as primary. This can go away once | |
1114 | * various bugs with primary-less systems are fixed. | |
1115 | */ | |
1116 | for_each_matching_node(np, pci_ids) { | |
1117 | if (of_device_is_available(np)) { | |
1118 | fsl_pci_primary = np; | |
1119 | of_node_put(np); | |
1120 | return; | |
07e4f801 SW |
1121 | } |
1122 | } | |
905e75c4 JH |
1123 | } |
1124 | ||
48b16180 WD |
1125 | #ifdef CONFIG_PM_SLEEP |
1126 | static irqreturn_t fsl_pci_pme_handle(int irq, void *dev_id) | |
905e75c4 | 1127 | { |
48b16180 WD |
1128 | struct pci_controller *hose = dev_id; |
1129 | struct ccsr_pci __iomem *pci = hose->private_data; | |
1130 | u32 dr; | |
905e75c4 | 1131 | |
48b16180 WD |
1132 | dr = in_be32(&pci->pex_pme_mes_dr); |
1133 | if (!dr) | |
1134 | return IRQ_NONE; | |
07e4f801 | 1135 | |
48b16180 | 1136 | out_be32(&pci->pex_pme_mes_dr, dr); |
905e75c4 | 1137 | |
48b16180 | 1138 | return IRQ_HANDLED; |
905e75c4 JH |
1139 | } |
1140 | ||
48b16180 | 1141 | static int fsl_pci_pme_probe(struct pci_controller *hose) |
a393d897 | 1142 | { |
48b16180 WD |
1143 | struct ccsr_pci __iomem *pci; |
1144 | struct pci_dev *dev; | |
1145 | int pme_irq; | |
1146 | int res; | |
1147 | u16 pms; | |
a393d897 | 1148 | |
48b16180 WD |
1149 | /* Get hose's pci_dev */ |
1150 | dev = list_first_entry(&hose->bus->devices, typeof(*dev), bus_list); | |
1151 | ||
1152 | /* PME Disable */ | |
1153 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pms); | |
1154 | pms &= ~PCI_PM_CTRL_PME_ENABLE; | |
1155 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pms); | |
1156 | ||
1157 | pme_irq = irq_of_parse_and_map(hose->dn, 0); | |
1158 | if (!pme_irq) { | |
1159 | dev_err(&dev->dev, "Failed to map PME interrupt.\n"); | |
1160 | ||
1161 | return -ENXIO; | |
1162 | } | |
1163 | ||
1164 | res = devm_request_irq(hose->parent, pme_irq, | |
1165 | fsl_pci_pme_handle, | |
1166 | IRQF_SHARED, | |
1167 | "[PCI] PME", hose); | |
1168 | if (res < 0) { | |
971bd8fa | 1169 | dev_err(&dev->dev, "Unable to request irq %d for PME\n", pme_irq); |
48b16180 | 1170 | irq_dispose_mapping(pme_irq); |
a393d897 | 1171 | |
a393d897 JH |
1172 | return -ENODEV; |
1173 | } | |
1174 | ||
48b16180 WD |
1175 | pci = hose->private_data; |
1176 | ||
1177 | /* Enable PTOD, ENL23D & EXL23D */ | |
dd41d514 | 1178 | clrbits32(&pci->pex_pme_mes_disr, |
48b16180 WD |
1179 | PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D); |
1180 | ||
1181 | out_be32(&pci->pex_pme_mes_ier, 0); | |
1182 | setbits32(&pci->pex_pme_mes_ier, | |
1183 | PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D); | |
1184 | ||
1185 | /* PME Enable */ | |
1186 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pms); | |
1187 | pms |= PCI_PM_CTRL_PME_ENABLE; | |
1188 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pms); | |
a393d897 JH |
1189 | |
1190 | return 0; | |
1191 | } | |
1192 | ||
48b16180 WD |
1193 | static void send_pme_turnoff_message(struct pci_controller *hose) |
1194 | { | |
1195 | struct ccsr_pci __iomem *pci = hose->private_data; | |
1196 | u32 dr; | |
1197 | int i; | |
a393d897 | 1198 | |
48b16180 WD |
1199 | /* Send PME_Turn_Off Message Request */ |
1200 | setbits32(&pci->pex_pmcr, PEX_PMCR_PTOMR); | |
a393d897 | 1201 | |
48b16180 WD |
1202 | /* Wait trun off done */ |
1203 | for (i = 0; i < 150; i++) { | |
1204 | dr = in_be32(&pci->pex_pme_mes_dr); | |
1205 | if (dr) { | |
1206 | out_be32(&pci->pex_pme_mes_dr, dr); | |
1207 | break; | |
1208 | } | |
a393d897 | 1209 | |
48b16180 WD |
1210 | udelay(1000); |
1211 | } | |
1212 | } | |
a393d897 | 1213 | |
48b16180 WD |
1214 | static void fsl_pci_syscore_do_suspend(struct pci_controller *hose) |
1215 | { | |
1216 | send_pme_turnoff_message(hose); | |
1217 | } | |
1218 | ||
1219 | static int fsl_pci_syscore_suspend(void) | |
1220 | { | |
1221 | struct pci_controller *hose, *tmp; | |
1222 | ||
1223 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) | |
1224 | fsl_pci_syscore_do_suspend(hose); | |
1225 | ||
1226 | return 0; | |
1227 | } | |
1228 | ||
1229 | static void fsl_pci_syscore_do_resume(struct pci_controller *hose) | |
1230 | { | |
1231 | struct ccsr_pci __iomem *pci = hose->private_data; | |
1232 | u32 dr; | |
1233 | int i; | |
1234 | ||
1235 | /* Send Exit L2 State Message */ | |
1236 | setbits32(&pci->pex_pmcr, PEX_PMCR_EXL2S); | |
1237 | ||
1238 | /* Wait exit done */ | |
1239 | for (i = 0; i < 150; i++) { | |
1240 | dr = in_be32(&pci->pex_pme_mes_dr); | |
1241 | if (dr) { | |
1242 | out_be32(&pci->pex_pme_mes_dr, dr); | |
1243 | break; | |
1244 | } | |
1245 | ||
1246 | udelay(1000); | |
1247 | } | |
1248 | ||
1249 | setup_pci_atmu(hose); | |
1250 | } | |
1251 | ||
1252 | static void fsl_pci_syscore_resume(void) | |
1253 | { | |
1254 | struct pci_controller *hose, *tmp; | |
1255 | ||
1256 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) | |
1257 | fsl_pci_syscore_do_resume(hose); | |
1258 | } | |
1259 | ||
1260 | static struct syscore_ops pci_syscore_pm_ops = { | |
1261 | .suspend = fsl_pci_syscore_suspend, | |
1262 | .resume = fsl_pci_syscore_resume, | |
1263 | }; | |
a393d897 JH |
1264 | #endif |
1265 | ||
48b16180 WD |
1266 | void fsl_pcibios_fixup_phb(struct pci_controller *phb) |
1267 | { | |
1268 | #ifdef CONFIG_PM_SLEEP | |
1269 | fsl_pci_pme_probe(phb); | |
1270 | #endif | |
1271 | } | |
1272 | ||
666db563 SW |
1273 | static int add_err_dev(struct platform_device *pdev) |
1274 | { | |
1275 | struct platform_device *errdev; | |
1276 | struct mpc85xx_edac_pci_plat_data pd = { | |
1277 | .of_node = pdev->dev.of_node | |
1278 | }; | |
1279 | ||
1280 | errdev = platform_device_register_resndata(&pdev->dev, | |
1281 | "mpc85xx-pci-edac", | |
1282 | PLATFORM_DEVID_AUTO, | |
1283 | pdev->resource, | |
1284 | pdev->num_resources, | |
1285 | &pd, sizeof(pd)); | |
1286 | if (IS_ERR(errdev)) | |
1287 | return PTR_ERR(errdev); | |
1288 | ||
1289 | return 0; | |
1290 | } | |
1291 | ||
48b16180 WD |
1292 | static int fsl_pci_probe(struct platform_device *pdev) |
1293 | { | |
1294 | struct device_node *node; | |
1295 | int ret; | |
1296 | ||
1297 | node = pdev->dev.of_node; | |
1298 | ret = fsl_add_bridge(pdev, fsl_pci_primary == node); | |
666db563 SW |
1299 | if (ret) |
1300 | return ret; | |
48b16180 | 1301 | |
666db563 SW |
1302 | ret = add_err_dev(pdev); |
1303 | if (ret) | |
1304 | dev_err(&pdev->dev, "couldn't register error device: %d\n", | |
1305 | ret); | |
48b16180 WD |
1306 | |
1307 | return 0; | |
1308 | } | |
1309 | ||
905e75c4 JH |
1310 | static struct platform_driver fsl_pci_driver = { |
1311 | .driver = { | |
1312 | .name = "fsl-pci", | |
1313 | .of_match_table = pci_ids, | |
1314 | }, | |
1315 | .probe = fsl_pci_probe, | |
1316 | }; | |
1317 | ||
1318 | static int __init fsl_pci_init(void) | |
1319 | { | |
48b16180 WD |
1320 | #ifdef CONFIG_PM_SLEEP |
1321 | register_syscore_ops(&pci_syscore_pm_ops); | |
1322 | #endif | |
905e75c4 | 1323 | return platform_driver_register(&fsl_pci_driver); |
07e4f801 | 1324 | } |
905e75c4 | 1325 | arch_initcall(fsl_pci_init); |
07e4f801 | 1326 | #endif |