Commit | Line | Data |
---|---|---|
b809b3e8 | 1 | /* |
5b70a097 | 2 | * MPC83xx/85xx/86xx PCI/PCIE support routing. |
b809b3e8 | 3 | * |
07e4f801 | 4 | * Copyright 2007-2012 Freescale Semiconductor, Inc. |
598804cd | 5 | * Copyright 2008-2009 MontaVista Software, Inc. |
b809b3e8 | 6 | * |
9ac4dd30 ZR |
7 | * Initial author: Xianghua Xiao <x.xiao@freescale.com> |
8 | * Recode: ZHANG WEI <wei.zhang@freescale.com> | |
9 | * Rewrite the routing for Frescale PCI and PCI Express | |
10 | * Roy Zang <tie-fei.zang@freescale.com> | |
598804cd AV |
11 | * MPC83xx PCI-Express support: |
12 | * Tony Li <tony.li@freescale.com> | |
13 | * Anton Vorontsov <avorontsov@ru.mvista.com> | |
b809b3e8 JL |
14 | * |
15 | * This program is free software; you can redistribute it and/or modify it | |
16 | * under the terms of the GNU General Public License as published by the | |
17 | * Free Software Foundation; either version 2 of the License, or (at your | |
18 | * option) any later version. | |
19 | */ | |
9ac4dd30 | 20 | #include <linux/kernel.h> |
b809b3e8 | 21 | #include <linux/pci.h> |
9ac4dd30 ZR |
22 | #include <linux/delay.h> |
23 | #include <linux/string.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/bootmem.h> | |
95f72d1e | 26 | #include <linux/memblock.h> |
54c18193 | 27 | #include <linux/log2.h> |
5a0e3ad6 | 28 | #include <linux/slab.h> |
b809b3e8 | 29 | |
b809b3e8 JL |
30 | #include <asm/io.h> |
31 | #include <asm/prom.h> | |
b809b3e8 | 32 | #include <asm/pci-bridge.h> |
9ac4dd30 | 33 | #include <asm/machdep.h> |
b809b3e8 | 34 | #include <sysdev/fsl_soc.h> |
55c44991 | 35 | #include <sysdev/fsl_pci.h> |
b809b3e8 | 36 | |
b8f44ec2 | 37 | static int fsl_pcie_bus_fixup, is_mpc83xx_pci; |
598804cd | 38 | |
dea0ed4a | 39 | static void __devinit quirk_fsl_pcie_header(struct pci_dev *dev) |
598804cd | 40 | { |
470788d4 KG |
41 | u8 progif; |
42 | ||
598804cd AV |
43 | /* if we aren't a PCIe don't bother */ |
44 | if (!pci_find_capability(dev, PCI_CAP_ID_EXP)) | |
45 | return; | |
46 | ||
470788d4 KG |
47 | /* if we aren't in host mode don't bother */ |
48 | pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); | |
49 | if (progif & 0x1) | |
50 | return; | |
51 | ||
598804cd AV |
52 | dev->class = PCI_CLASS_BRIDGE_PCI << 8; |
53 | fsl_pcie_bus_fixup = 1; | |
54 | return; | |
55 | } | |
56 | ||
57 | static int __init fsl_pcie_check_link(struct pci_controller *hose) | |
58 | { | |
59 | u32 val; | |
60 | ||
61 | early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val); | |
62 | if (val < PCIE_LTSSM_L0) | |
63 | return 1; | |
64 | return 0; | |
65 | } | |
66 | ||
5753c082 | 67 | #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) |
96ea3b4a KG |
68 | |
69 | #define MAX_PHYS_ADDR_BITS 40 | |
70 | static u64 pci64_dma_offset = 1ull << MAX_PHYS_ADDR_BITS; | |
71 | ||
72 | static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask) | |
73 | { | |
74 | if (!dev->dma_mask || !dma_supported(dev, dma_mask)) | |
75 | return -EIO; | |
76 | ||
77 | /* | |
78 | * Fixup PCI devices that are able to DMA to above the physical | |
79 | * address width of the SoC such that we can address any internal | |
80 | * SoC address from across PCI if needed | |
81 | */ | |
82 | if ((dev->bus == &pci_bus_type) && | |
83 | dma_mask >= DMA_BIT_MASK(MAX_PHYS_ADDR_BITS)) { | |
84 | set_dma_ops(dev, &dma_direct_ops); | |
85 | set_dma_offset(dev, pci64_dma_offset); | |
86 | } | |
87 | ||
88 | *dev->dma_mask = dma_mask; | |
89 | return 0; | |
90 | } | |
91 | ||
a097a78c TP |
92 | static int __init setup_one_atmu(struct ccsr_pci __iomem *pci, |
93 | unsigned int index, const struct resource *res, | |
94 | resource_size_t offset) | |
95 | { | |
96 | resource_size_t pci_addr = res->start - offset; | |
97 | resource_size_t phys_addr = res->start; | |
28f65c11 | 98 | resource_size_t size = resource_size(res); |
a097a78c TP |
99 | u32 flags = 0x80044000; /* enable & mem R/W */ |
100 | unsigned int i; | |
101 | ||
102 | pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n", | |
103 | (u64)res->start, (u64)size); | |
104 | ||
565f3764 TP |
105 | if (res->flags & IORESOURCE_PREFETCH) |
106 | flags |= 0x10000000; /* enable relaxed ordering */ | |
107 | ||
a097a78c TP |
108 | for (i = 0; size > 0; i++) { |
109 | unsigned int bits = min(__ilog2(size), | |
110 | __ffs(pci_addr | phys_addr)); | |
111 | ||
112 | if (index + i >= 5) | |
113 | return -1; | |
114 | ||
115 | out_be32(&pci->pow[index + i].potar, pci_addr >> 12); | |
116 | out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44); | |
117 | out_be32(&pci->pow[index + i].powbar, phys_addr >> 12); | |
118 | out_be32(&pci->pow[index + i].powar, flags | (bits - 1)); | |
119 | ||
120 | pci_addr += (resource_size_t)1U << bits; | |
121 | phys_addr += (resource_size_t)1U << bits; | |
122 | size -= (resource_size_t)1U << bits; | |
123 | } | |
124 | ||
125 | return i; | |
126 | } | |
127 | ||
9ac4dd30 | 128 | /* atmu setup for fsl pci/pcie controller */ |
c9dadffb AV |
129 | static void __init setup_pci_atmu(struct pci_controller *hose, |
130 | struct resource *rsrc) | |
b809b3e8 | 131 | { |
9ac4dd30 | 132 | struct ccsr_pci __iomem *pci; |
f4154e16 | 133 | int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4; |
54c18193 KG |
134 | u64 mem, sz, paddr_hi = 0; |
135 | u64 paddr_lo = ULLONG_MAX; | |
136 | u32 pcicsrbar = 0, pcicsrbar_sz; | |
137 | u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL | | |
138 | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; | |
139 | char *name = hose->dn->full_name; | |
446bc1ff TT |
140 | const u64 *reg; |
141 | int len; | |
b809b3e8 | 142 | |
72b122cc | 143 | pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n", |
28f65c11 | 144 | (u64)rsrc->start, (u64)resource_size(rsrc)); |
f4154e16 PK |
145 | |
146 | if (of_device_is_compatible(hose->dn, "fsl,qoriq-pcie-v2.2")) { | |
147 | win_idx = 2; | |
148 | start_idx = 0; | |
149 | end_idx = 3; | |
150 | } | |
151 | ||
28f65c11 | 152 | pci = ioremap(rsrc->start, resource_size(rsrc)); |
a097a78c TP |
153 | if (!pci) { |
154 | dev_err(hose->parent, "Unable to map ATMU registers\n"); | |
155 | return; | |
156 | } | |
9ac4dd30 | 157 | |
a097a78c | 158 | /* Disable all windows (except powar0 since it's ignored) */ |
9ac4dd30 ZR |
159 | for(i = 1; i < 5; i++) |
160 | out_be32(&pci->pow[i].powar, 0); | |
f4154e16 | 161 | for (i = start_idx; i < end_idx; i++) |
9ac4dd30 ZR |
162 | out_be32(&pci->piw[i].piwar, 0); |
163 | ||
164 | /* Setup outbound MEM window */ | |
a097a78c TP |
165 | for(i = 0, j = 1; i < 3; i++) { |
166 | if (!(hose->mem_resources[i].flags & IORESOURCE_MEM)) | |
167 | continue; | |
168 | ||
54c18193 KG |
169 | paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start); |
170 | paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end); | |
171 | ||
a097a78c TP |
172 | n = setup_one_atmu(pci, j, &hose->mem_resources[i], |
173 | hose->pci_mem_offset); | |
174 | ||
175 | if (n < 0 || j >= 5) { | |
176 | pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i); | |
177 | hose->mem_resources[i].flags |= IORESOURCE_DISABLED; | |
178 | } else | |
179 | j += n; | |
180 | } | |
9ac4dd30 ZR |
181 | |
182 | /* Setup outbound IO window */ | |
a097a78c TP |
183 | if (hose->io_resource.flags & IORESOURCE_IO) { |
184 | if (j >= 5) { | |
185 | pr_err("Ran out of outbound PCI ATMUs for IO resource\n"); | |
186 | } else { | |
187 | pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, " | |
188 | "phy base 0x%016llx.\n", | |
28f65c11 JP |
189 | (u64)hose->io_resource.start, |
190 | (u64)resource_size(&hose->io_resource), | |
191 | (u64)hose->io_base_phys); | |
a097a78c TP |
192 | out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12)); |
193 | out_be32(&pci->pow[j].potear, 0); | |
194 | out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12)); | |
195 | /* Enable, IO R/W */ | |
196 | out_be32(&pci->pow[j].powar, 0x80088000 | |
197 | | (__ilog2(hose->io_resource.end | |
198 | - hose->io_resource.start + 1) - 1)); | |
199 | } | |
9ac4dd30 ZR |
200 | } |
201 | ||
54c18193 KG |
202 | /* convert to pci address space */ |
203 | paddr_hi -= hose->pci_mem_offset; | |
204 | paddr_lo -= hose->pci_mem_offset; | |
205 | ||
206 | if (paddr_hi == paddr_lo) { | |
207 | pr_err("%s: No outbound window space\n", name); | |
0cf572dc | 208 | goto out; |
54c18193 KG |
209 | } |
210 | ||
211 | if (paddr_lo == 0) { | |
212 | pr_err("%s: No space for inbound window\n", name); | |
0cf572dc | 213 | goto out; |
54c18193 KG |
214 | } |
215 | ||
216 | /* setup PCSRBAR/PEXCSRBAR */ | |
217 | early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff); | |
218 | early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz); | |
219 | pcicsrbar_sz = ~pcicsrbar_sz + 1; | |
220 | ||
221 | if (paddr_hi < (0x100000000ull - pcicsrbar_sz) || | |
222 | (paddr_lo > 0x100000000ull)) | |
223 | pcicsrbar = 0x100000000ull - pcicsrbar_sz; | |
224 | else | |
225 | pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz; | |
226 | early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar); | |
227 | ||
228 | paddr_lo = min(paddr_lo, (u64)pcicsrbar); | |
229 | ||
230 | pr_info("%s: PCICSRBAR @ 0x%x\n", name, pcicsrbar); | |
231 | ||
232 | /* Setup inbound mem window */ | |
95f72d1e | 233 | mem = memblock_end_of_DRAM(); |
446bc1ff TT |
234 | |
235 | /* | |
236 | * The msi-address-64 property, if it exists, indicates the physical | |
237 | * address of the MSIIR register. Normally, this register is located | |
238 | * inside CCSR, so the ATMU that covers all of CCSR is used. But if | |
239 | * this property exists, then we normally need to create a new ATMU | |
240 | * for it. For now, however, we cheat. The only entity that creates | |
241 | * this property is the Freescale hypervisor, and the address is | |
242 | * specified in the partition configuration. Typically, the address | |
243 | * is located in the page immediately after the end of DDR. If so, we | |
244 | * can avoid allocating a new ATMU by extending the DDR ATMU by one | |
245 | * page. | |
246 | */ | |
247 | reg = of_get_property(hose->dn, "msi-address-64", &len); | |
248 | if (reg && (len == sizeof(u64))) { | |
249 | u64 address = be64_to_cpup(reg); | |
250 | ||
251 | if ((address >= mem) && (address < (mem + PAGE_SIZE))) { | |
252 | pr_info("%s: extending DDR ATMU to cover MSIIR", name); | |
253 | mem += PAGE_SIZE; | |
254 | } else { | |
255 | /* TODO: Create a new ATMU for MSIIR */ | |
256 | pr_warn("%s: msi-address-64 address of %llx is " | |
257 | "unsupported\n", name, address); | |
258 | } | |
259 | } | |
260 | ||
54c18193 KG |
261 | sz = min(mem, paddr_lo); |
262 | mem_log = __ilog2_u64(sz); | |
263 | ||
264 | /* PCIe can overmap inbound & outbound since RX & TX are separated */ | |
265 | if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { | |
266 | /* Size window to exact size if power-of-two or one size up */ | |
267 | if ((1ull << mem_log) != mem) { | |
268 | if ((1ull << mem_log) > mem) | |
269 | pr_info("%s: Setting PCI inbound window " | |
270 | "greater than memory size\n", name); | |
271 | mem_log++; | |
272 | } | |
273 | ||
f4154e16 | 274 | piwar |= ((mem_log - 1) & PIWAR_SZ_MASK); |
54c18193 KG |
275 | |
276 | /* Setup inbound memory window */ | |
277 | out_be32(&pci->piw[win_idx].pitar, 0x00000000); | |
278 | out_be32(&pci->piw[win_idx].piwbar, 0x00000000); | |
279 | out_be32(&pci->piw[win_idx].piwar, piwar); | |
280 | win_idx--; | |
281 | ||
282 | hose->dma_window_base_cur = 0x00000000; | |
283 | hose->dma_window_size = (resource_size_t)sz; | |
96ea3b4a KG |
284 | |
285 | /* | |
286 | * if we have >4G of memory setup second PCI inbound window to | |
287 | * let devices that are 64-bit address capable to work w/o | |
288 | * SWIOTLB and access the full range of memory | |
289 | */ | |
290 | if (sz != mem) { | |
291 | mem_log = __ilog2_u64(mem); | |
292 | ||
293 | /* Size window up if we dont fit in exact power-of-2 */ | |
294 | if ((1ull << mem_log) != mem) | |
295 | mem_log++; | |
296 | ||
297 | piwar = (piwar & ~PIWAR_SZ_MASK) | (mem_log - 1); | |
298 | ||
299 | /* Setup inbound memory window */ | |
300 | out_be32(&pci->piw[win_idx].pitar, 0x00000000); | |
301 | out_be32(&pci->piw[win_idx].piwbear, | |
302 | pci64_dma_offset >> 44); | |
303 | out_be32(&pci->piw[win_idx].piwbar, | |
304 | pci64_dma_offset >> 12); | |
305 | out_be32(&pci->piw[win_idx].piwar, piwar); | |
306 | ||
307 | /* | |
308 | * install our own dma_set_mask handler to fixup dma_ops | |
309 | * and dma_offset | |
310 | */ | |
311 | ppc_md.dma_set_mask = fsl_pci_dma_set_mask; | |
312 | ||
313 | pr_info("%s: Setup 64-bit PCI DMA window\n", name); | |
314 | } | |
54c18193 KG |
315 | } else { |
316 | u64 paddr = 0; | |
317 | ||
318 | /* Setup inbound memory window */ | |
319 | out_be32(&pci->piw[win_idx].pitar, paddr >> 12); | |
320 | out_be32(&pci->piw[win_idx].piwbar, paddr >> 12); | |
321 | out_be32(&pci->piw[win_idx].piwar, (piwar | (mem_log - 1))); | |
322 | win_idx--; | |
323 | ||
324 | paddr += 1ull << mem_log; | |
325 | sz -= 1ull << mem_log; | |
326 | ||
327 | if (sz) { | |
328 | mem_log = __ilog2_u64(sz); | |
329 | piwar |= (mem_log - 1); | |
330 | ||
331 | out_be32(&pci->piw[win_idx].pitar, paddr >> 12); | |
332 | out_be32(&pci->piw[win_idx].piwbar, paddr >> 12); | |
333 | out_be32(&pci->piw[win_idx].piwar, piwar); | |
334 | win_idx--; | |
335 | ||
336 | paddr += 1ull << mem_log; | |
337 | } | |
338 | ||
339 | hose->dma_window_base_cur = 0x00000000; | |
340 | hose->dma_window_size = (resource_size_t)paddr; | |
341 | } | |
a097a78c | 342 | |
54c18193 KG |
343 | if (hose->dma_window_size < mem) { |
344 | #ifndef CONFIG_SWIOTLB | |
345 | pr_err("%s: ERROR: Memory size exceeds PCI ATMU ability to " | |
346 | "map - enable CONFIG_SWIOTLB to avoid dma errors.\n", | |
347 | name); | |
348 | #endif | |
349 | /* adjusting outbound windows could reclaim space in mem map */ | |
350 | if (paddr_hi < 0xffffffffull) | |
351 | pr_warning("%s: WARNING: Outbound window cfg leaves " | |
352 | "gaps in memory map. Adjusting the memory map " | |
353 | "could reduce unnecessary bounce buffering.\n", | |
354 | name); | |
355 | ||
356 | pr_info("%s: DMA window size is 0x%llx\n", name, | |
357 | (u64)hose->dma_window_size); | |
358 | } | |
89d93347 | 359 | |
0cf572dc | 360 | out: |
a097a78c | 361 | iounmap(pci); |
b809b3e8 JL |
362 | } |
363 | ||
c9dadffb | 364 | static void __init setup_pci_cmd(struct pci_controller *hose) |
b809b3e8 | 365 | { |
b809b3e8 | 366 | u16 cmd; |
eb12af43 KG |
367 | int cap_x; |
368 | ||
b809b3e8 JL |
369 | early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd); |
370 | cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | |
9ac4dd30 | 371 | | PCI_COMMAND_IO; |
b809b3e8 | 372 | early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd); |
eb12af43 KG |
373 | |
374 | cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX); | |
375 | if (cap_x) { | |
376 | int pci_x_cmd = cap_x + PCI_X_CMD; | |
377 | cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ | |
378 | | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; | |
379 | early_write_config_word(hose, 0, 0, pci_x_cmd, cmd); | |
380 | } else { | |
381 | early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80); | |
382 | } | |
9ad494f6 KG |
383 | } |
384 | ||
6c0a11c1 KG |
385 | void fsl_pcibios_fixup_bus(struct pci_bus *bus) |
386 | { | |
8206a110 | 387 | struct pci_controller *hose = pci_bus_to_host(bus); |
13635dfd BH |
388 | int i, is_pcie = 0, no_link; |
389 | ||
390 | /* The root complex bridge comes up with bogus resources, | |
391 | * we copy the PHB ones in. | |
392 | * | |
393 | * With the current generic PCI code, the PHB bus no longer | |
394 | * has bus->resource[0..4] set, so things are a bit more | |
395 | * tricky. | |
396 | */ | |
397 | ||
398 | if (fsl_pcie_bus_fixup) | |
399 | is_pcie = early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP); | |
400 | no_link = !!(hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK); | |
401 | ||
402 | if (bus->parent == hose->bus && (is_pcie || no_link)) { | |
403 | for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; ++i) { | |
72b122cc | 404 | struct resource *res = bus->resource[i]; |
13635dfd BH |
405 | struct resource *par; |
406 | ||
407 | if (!res) | |
408 | continue; | |
409 | if (i == 0) | |
410 | par = &hose->io_resource; | |
411 | else if (i < 4) | |
412 | par = &hose->mem_resources[i-1]; | |
413 | else par = NULL; | |
414 | ||
415 | res->start = par ? par->start : 0; | |
416 | res->end = par ? par->end : 0; | |
417 | res->flags = par ? par->flags : 0; | |
6c0a11c1 KG |
418 | } |
419 | } | |
420 | } | |
421 | ||
9ac4dd30 | 422 | int __init fsl_add_bridge(struct device_node *dev, int is_primary) |
b809b3e8 JL |
423 | { |
424 | int len; | |
425 | struct pci_controller *hose; | |
426 | struct resource rsrc; | |
8efca493 | 427 | const int *bus_range; |
08871c09 | 428 | u8 progif; |
b809b3e8 | 429 | |
ef1fd2df PK |
430 | if (!of_device_is_available(dev)) { |
431 | pr_warning("%s: disabled\n", dev->full_name); | |
432 | return -ENODEV; | |
433 | } | |
434 | ||
9ac4dd30 | 435 | pr_debug("Adding PCI host bridge %s\n", dev->full_name); |
b809b3e8 JL |
436 | |
437 | /* Fetch host bridge registers address */ | |
9ac4dd30 ZR |
438 | if (of_address_to_resource(dev, 0, &rsrc)) { |
439 | printk(KERN_WARNING "Can't get pci register base!"); | |
440 | return -ENOMEM; | |
441 | } | |
b809b3e8 JL |
442 | |
443 | /* Get bus range if any */ | |
e2eb6392 | 444 | bus_range = of_get_property(dev, "bus-range", &len); |
b809b3e8 JL |
445 | if (bus_range == NULL || len < 2 * sizeof(int)) |
446 | printk(KERN_WARNING "Can't get bus-range for %s, assume" | |
9ac4dd30 | 447 | " bus 0\n", dev->full_name); |
b809b3e8 | 448 | |
0e47ff1c | 449 | pci_add_flags(PCI_REASSIGN_ALL_BUS); |
dbf8471f | 450 | hose = pcibios_alloc_controller(dev); |
b809b3e8 JL |
451 | if (!hose) |
452 | return -ENOMEM; | |
dbf8471f | 453 | |
b809b3e8 | 454 | hose->first_busno = bus_range ? bus_range[0] : 0x0; |
bf7c036f | 455 | hose->last_busno = bus_range ? bus_range[1] : 0xff; |
b809b3e8 | 456 | |
2e56ff20 KG |
457 | setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4, |
458 | PPC_INDIRECT_TYPE_BIG_ENDIAN); | |
08871c09 PK |
459 | |
460 | early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif); | |
461 | if ((progif & 1) == 1) { | |
462 | /* unmap cfg_data & cfg_addr separately if not on same page */ | |
463 | if (((unsigned long)hose->cfg_data & PAGE_MASK) != | |
464 | ((unsigned long)hose->cfg_addr & PAGE_MASK)) | |
465 | iounmap(hose->cfg_data); | |
466 | iounmap(hose->cfg_addr); | |
467 | pcibios_free_controller(hose); | |
c9f11c30 | 468 | return -ENODEV; |
08871c09 PK |
469 | } |
470 | ||
9ac4dd30 | 471 | setup_pci_cmd(hose); |
b809b3e8 | 472 | |
9ac4dd30 | 473 | /* check PCI express link status */ |
957ecffc | 474 | if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { |
7659c038 | 475 | hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG | |
957ecffc | 476 | PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS; |
9ac4dd30 | 477 | if (fsl_pcie_check_link(hose)) |
957ecffc KG |
478 | hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; |
479 | } | |
b809b3e8 | 480 | |
df3c9019 | 481 | printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. " |
9ac4dd30 ZR |
482 | "Firmware bus number: %d->%d\n", |
483 | (unsigned long long)rsrc.start, hose->first_busno, | |
484 | hose->last_busno); | |
b809b3e8 | 485 | |
9ac4dd30 | 486 | pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", |
b809b3e8 JL |
487 | hose, hose->cfg_addr, hose->cfg_data); |
488 | ||
489 | /* Interpret the "ranges" property */ | |
490 | /* This also maps the I/O region and sets isa_io/mem_base */ | |
9ac4dd30 | 491 | pci_process_bridge_OF_ranges(hose, dev, is_primary); |
b809b3e8 JL |
492 | |
493 | /* Setup PEX window registers */ | |
9ac4dd30 | 494 | setup_pci_atmu(hose, &rsrc); |
b809b3e8 JL |
495 | |
496 | return 0; | |
497 | } | |
5753c082 | 498 | #endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */ |
76fe1ffc | 499 | |
470788d4 | 500 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_pcie_header); |
598804cd | 501 | |
470788d4 | 502 | #if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x) |
598804cd AV |
503 | struct mpc83xx_pcie_priv { |
504 | void __iomem *cfg_type0; | |
505 | void __iomem *cfg_type1; | |
506 | u32 dev_base; | |
507 | }; | |
508 | ||
b8f44ec2 KG |
509 | struct pex_inbound_window { |
510 | u32 ar; | |
511 | u32 tar; | |
512 | u32 barl; | |
513 | u32 barh; | |
514 | }; | |
515 | ||
598804cd AV |
516 | /* |
517 | * With the convention of u-boot, the PCIE outbound window 0 serves | |
518 | * as configuration transactions outbound. | |
519 | */ | |
520 | #define PEX_OUTWIN0_BAR 0xCA4 | |
521 | #define PEX_OUTWIN0_TAL 0xCA8 | |
522 | #define PEX_OUTWIN0_TAH 0xCAC | |
b8f44ec2 KG |
523 | #define PEX_RC_INWIN_BASE 0xE60 |
524 | #define PEX_RCIWARn_EN 0x1 | |
598804cd AV |
525 | |
526 | static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn) | |
527 | { | |
8206a110 | 528 | struct pci_controller *hose = pci_bus_to_host(bus); |
598804cd AV |
529 | |
530 | if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) | |
531 | return PCIBIOS_DEVICE_NOT_FOUND; | |
532 | /* | |
533 | * Workaround for the HW bug: for Type 0 configure transactions the | |
534 | * PCI-E controller does not check the device number bits and just | |
535 | * assumes that the device number bits are 0. | |
536 | */ | |
537 | if (bus->number == hose->first_busno || | |
538 | bus->primary == hose->first_busno) { | |
539 | if (devfn & 0xf8) | |
540 | return PCIBIOS_DEVICE_NOT_FOUND; | |
541 | } | |
542 | ||
543 | if (ppc_md.pci_exclude_device) { | |
544 | if (ppc_md.pci_exclude_device(hose, bus->number, devfn)) | |
545 | return PCIBIOS_DEVICE_NOT_FOUND; | |
546 | } | |
547 | ||
548 | return PCIBIOS_SUCCESSFUL; | |
549 | } | |
550 | ||
551 | static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus, | |
552 | unsigned int devfn, int offset) | |
553 | { | |
8206a110 | 554 | struct pci_controller *hose = pci_bus_to_host(bus); |
598804cd | 555 | struct mpc83xx_pcie_priv *pcie = hose->dn->data; |
f93611fa | 556 | u32 dev_base = bus->number << 24 | devfn << 16; |
598804cd AV |
557 | int ret; |
558 | ||
559 | ret = mpc83xx_pcie_exclude_device(bus, devfn); | |
560 | if (ret) | |
561 | return NULL; | |
562 | ||
563 | offset &= 0xfff; | |
564 | ||
565 | /* Type 0 */ | |
566 | if (bus->number == hose->first_busno) | |
567 | return pcie->cfg_type0 + offset; | |
568 | ||
569 | if (pcie->dev_base == dev_base) | |
570 | goto mapped; | |
571 | ||
572 | out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base); | |
573 | ||
574 | pcie->dev_base = dev_base; | |
575 | mapped: | |
576 | return pcie->cfg_type1 + offset; | |
577 | } | |
578 | ||
579 | static int mpc83xx_pcie_read_config(struct pci_bus *bus, unsigned int devfn, | |
580 | int offset, int len, u32 *val) | |
581 | { | |
582 | void __iomem *cfg_addr; | |
583 | ||
584 | cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset); | |
585 | if (!cfg_addr) | |
586 | return PCIBIOS_DEVICE_NOT_FOUND; | |
587 | ||
588 | switch (len) { | |
589 | case 1: | |
590 | *val = in_8(cfg_addr); | |
591 | break; | |
592 | case 2: | |
593 | *val = in_le16(cfg_addr); | |
594 | break; | |
595 | default: | |
596 | *val = in_le32(cfg_addr); | |
597 | break; | |
598 | } | |
599 | ||
600 | return PCIBIOS_SUCCESSFUL; | |
601 | } | |
602 | ||
603 | static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn, | |
604 | int offset, int len, u32 val) | |
605 | { | |
f93611fa | 606 | struct pci_controller *hose = pci_bus_to_host(bus); |
598804cd AV |
607 | void __iomem *cfg_addr; |
608 | ||
609 | cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset); | |
610 | if (!cfg_addr) | |
611 | return PCIBIOS_DEVICE_NOT_FOUND; | |
612 | ||
f93611fa AV |
613 | /* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */ |
614 | if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno) | |
615 | val &= 0xffffff00; | |
616 | ||
598804cd AV |
617 | switch (len) { |
618 | case 1: | |
619 | out_8(cfg_addr, val); | |
620 | break; | |
621 | case 2: | |
622 | out_le16(cfg_addr, val); | |
623 | break; | |
624 | default: | |
625 | out_le32(cfg_addr, val); | |
626 | break; | |
627 | } | |
628 | ||
629 | return PCIBIOS_SUCCESSFUL; | |
630 | } | |
631 | ||
632 | static struct pci_ops mpc83xx_pcie_ops = { | |
633 | .read = mpc83xx_pcie_read_config, | |
634 | .write = mpc83xx_pcie_write_config, | |
635 | }; | |
636 | ||
637 | static int __init mpc83xx_pcie_setup(struct pci_controller *hose, | |
638 | struct resource *reg) | |
639 | { | |
640 | struct mpc83xx_pcie_priv *pcie; | |
641 | u32 cfg_bar; | |
642 | int ret = -ENOMEM; | |
643 | ||
644 | pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL); | |
645 | if (!pcie) | |
646 | return ret; | |
647 | ||
648 | pcie->cfg_type0 = ioremap(reg->start, resource_size(reg)); | |
649 | if (!pcie->cfg_type0) | |
650 | goto err0; | |
651 | ||
652 | cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR); | |
653 | if (!cfg_bar) { | |
654 | /* PCI-E isn't configured. */ | |
655 | ret = -ENODEV; | |
656 | goto err1; | |
657 | } | |
658 | ||
659 | pcie->cfg_type1 = ioremap(cfg_bar, 0x1000); | |
660 | if (!pcie->cfg_type1) | |
661 | goto err1; | |
662 | ||
663 | WARN_ON(hose->dn->data); | |
664 | hose->dn->data = pcie; | |
665 | hose->ops = &mpc83xx_pcie_ops; | |
666 | ||
667 | out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0); | |
668 | out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0); | |
669 | ||
670 | if (fsl_pcie_check_link(hose)) | |
671 | hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; | |
672 | ||
673 | return 0; | |
674 | err1: | |
675 | iounmap(pcie->cfg_type0); | |
676 | err0: | |
677 | kfree(pcie); | |
678 | return ret; | |
679 | ||
680 | } | |
681 | ||
76fe1ffc JR |
682 | int __init mpc83xx_add_bridge(struct device_node *dev) |
683 | { | |
598804cd | 684 | int ret; |
76fe1ffc JR |
685 | int len; |
686 | struct pci_controller *hose; | |
5b70a097 JR |
687 | struct resource rsrc_reg; |
688 | struct resource rsrc_cfg; | |
76fe1ffc | 689 | const int *bus_range; |
5b70a097 | 690 | int primary; |
76fe1ffc | 691 | |
b8f44ec2 KG |
692 | is_mpc83xx_pci = 1; |
693 | ||
598804cd AV |
694 | if (!of_device_is_available(dev)) { |
695 | pr_warning("%s: disabled by the firmware.\n", | |
696 | dev->full_name); | |
697 | return -ENODEV; | |
698 | } | |
76fe1ffc JR |
699 | pr_debug("Adding PCI host bridge %s\n", dev->full_name); |
700 | ||
701 | /* Fetch host bridge registers address */ | |
5b70a097 JR |
702 | if (of_address_to_resource(dev, 0, &rsrc_reg)) { |
703 | printk(KERN_WARNING "Can't get pci register base!\n"); | |
704 | return -ENOMEM; | |
705 | } | |
706 | ||
707 | memset(&rsrc_cfg, 0, sizeof(rsrc_cfg)); | |
708 | ||
709 | if (of_address_to_resource(dev, 1, &rsrc_cfg)) { | |
710 | printk(KERN_WARNING | |
711 | "No pci config register base in dev tree, " | |
712 | "using default\n"); | |
713 | /* | |
714 | * MPC83xx supports up to two host controllers | |
715 | * one at 0x8500 has config space registers at 0x8300 | |
716 | * one at 0x8600 has config space registers at 0x8380 | |
717 | */ | |
718 | if ((rsrc_reg.start & 0xfffff) == 0x8500) | |
719 | rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300; | |
720 | else if ((rsrc_reg.start & 0xfffff) == 0x8600) | |
721 | rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380; | |
722 | } | |
723 | /* | |
724 | * Controller at offset 0x8500 is primary | |
725 | */ | |
726 | if ((rsrc_reg.start & 0xfffff) == 0x8500) | |
727 | primary = 1; | |
728 | else | |
729 | primary = 0; | |
76fe1ffc JR |
730 | |
731 | /* Get bus range if any */ | |
732 | bus_range = of_get_property(dev, "bus-range", &len); | |
733 | if (bus_range == NULL || len < 2 * sizeof(int)) { | |
734 | printk(KERN_WARNING "Can't get bus-range for %s, assume" | |
735 | " bus 0\n", dev->full_name); | |
736 | } | |
737 | ||
0e47ff1c | 738 | pci_add_flags(PCI_REASSIGN_ALL_BUS); |
76fe1ffc JR |
739 | hose = pcibios_alloc_controller(dev); |
740 | if (!hose) | |
741 | return -ENOMEM; | |
742 | ||
743 | hose->first_busno = bus_range ? bus_range[0] : 0; | |
744 | hose->last_busno = bus_range ? bus_range[1] : 0xff; | |
745 | ||
598804cd AV |
746 | if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) { |
747 | ret = mpc83xx_pcie_setup(hose, &rsrc_reg); | |
748 | if (ret) | |
749 | goto err0; | |
750 | } else { | |
751 | setup_indirect_pci(hose, rsrc_cfg.start, | |
752 | rsrc_cfg.start + 4, 0); | |
753 | } | |
76fe1ffc | 754 | |
35225802 | 755 | printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. " |
76fe1ffc | 756 | "Firmware bus number: %d->%d\n", |
5b70a097 | 757 | (unsigned long long)rsrc_reg.start, hose->first_busno, |
76fe1ffc JR |
758 | hose->last_busno); |
759 | ||
760 | pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", | |
761 | hose, hose->cfg_addr, hose->cfg_data); | |
762 | ||
763 | /* Interpret the "ranges" property */ | |
764 | /* This also maps the I/O region and sets isa_io/mem_base */ | |
765 | pci_process_bridge_OF_ranges(hose, dev, primary); | |
766 | ||
767 | return 0; | |
598804cd AV |
768 | err0: |
769 | pcibios_free_controller(hose); | |
770 | return ret; | |
76fe1ffc JR |
771 | } |
772 | #endif /* CONFIG_PPC_83xx */ | |
b8f44ec2 KG |
773 | |
774 | u64 fsl_pci_immrbar_base(struct pci_controller *hose) | |
775 | { | |
776 | #ifdef CONFIG_PPC_83xx | |
777 | if (is_mpc83xx_pci) { | |
778 | struct mpc83xx_pcie_priv *pcie = hose->dn->data; | |
779 | struct pex_inbound_window *in; | |
780 | int i; | |
781 | ||
782 | /* Walk the Root Complex Inbound windows to match IMMR base */ | |
783 | in = pcie->cfg_type0 + PEX_RC_INWIN_BASE; | |
784 | for (i = 0; i < 4; i++) { | |
785 | /* not enabled, skip */ | |
786 | if (!in_le32(&in[i].ar) & PEX_RCIWARn_EN) | |
787 | continue; | |
788 | ||
789 | if (get_immrbase() == in_le32(&in[i].tar)) | |
790 | return (u64)in_le32(&in[i].barh) << 32 | | |
791 | in_le32(&in[i].barl); | |
792 | } | |
793 | ||
794 | printk(KERN_WARNING "could not find PCI BAR matching IMMR\n"); | |
795 | } | |
796 | #endif | |
797 | ||
798 | #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) | |
799 | if (!is_mpc83xx_pci) { | |
800 | u32 base; | |
801 | ||
802 | pci_bus_read_config_dword(hose->bus, | |
803 | PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base); | |
804 | return base; | |
805 | } | |
806 | #endif | |
807 | ||
808 | return 0; | |
809 | } | |
07e4f801 SW |
810 | |
811 | #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) | |
812 | static const struct of_device_id pci_ids[] = { | |
813 | { .compatible = "fsl,mpc8540-pci", }, | |
814 | { .compatible = "fsl,mpc8548-pcie", }, | |
815 | { .compatible = "fsl,mpc8610-pci", }, | |
816 | { .compatible = "fsl,mpc8641-pcie", }, | |
817 | { .compatible = "fsl,p1022-pcie", }, | |
818 | { .compatible = "fsl,p1010-pcie", }, | |
819 | { .compatible = "fsl,p1023-pcie", }, | |
820 | { .compatible = "fsl,p4080-pcie", }, | |
821 | { .compatible = "fsl,qoriq-pcie-v2.3", }, | |
822 | { .compatible = "fsl,qoriq-pcie-v2.2", }, | |
823 | {}, | |
824 | }; | |
825 | ||
826 | struct device_node *fsl_pci_primary; | |
827 | ||
828 | void __devinit fsl_pci_init(void) | |
829 | { | |
c9f11c30 | 830 | int ret; |
07e4f801 SW |
831 | struct device_node *node; |
832 | struct pci_controller *hose; | |
833 | dma_addr_t max = 0xffffffff; | |
834 | ||
835 | /* Callers can specify the primary bus using other means. */ | |
836 | if (!fsl_pci_primary) { | |
837 | /* If a PCI host bridge contains an ISA node, it's primary. */ | |
838 | node = of_find_node_by_type(NULL, "isa"); | |
839 | while ((fsl_pci_primary = of_get_parent(node))) { | |
840 | of_node_put(node); | |
841 | node = fsl_pci_primary; | |
842 | ||
843 | if (of_match_node(pci_ids, node)) | |
844 | break; | |
845 | } | |
846 | } | |
847 | ||
848 | node = NULL; | |
849 | for_each_node_by_type(node, "pci") { | |
850 | if (of_match_node(pci_ids, node)) { | |
851 | /* | |
852 | * If there's no PCI host bridge with ISA, arbitrarily | |
853 | * designate one as primary. This can go away once | |
854 | * various bugs with primary-less systems are fixed. | |
855 | */ | |
856 | if (!fsl_pci_primary) | |
857 | fsl_pci_primary = node; | |
858 | ||
c9f11c30 JH |
859 | ret = fsl_add_bridge(node, fsl_pci_primary == node); |
860 | if (ret == 0) { | |
861 | hose = pci_find_hose_for_OF_device(node); | |
862 | max = min(max, hose->dma_window_base_cur + | |
863 | hose->dma_window_size); | |
864 | } | |
07e4f801 SW |
865 | } |
866 | } | |
867 | ||
868 | #ifdef CONFIG_SWIOTLB | |
869 | /* | |
870 | * if we couldn't map all of DRAM via the dma windows | |
871 | * we need SWIOTLB to handle buffers located outside of | |
872 | * dma capable memory region | |
873 | */ | |
874 | if (memblock_end_of_DRAM() - 1 > max) { | |
875 | ppc_swiotlb_enable = 1; | |
876 | set_pci_dma_ops(&swiotlb_dma_ops); | |
877 | ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb; | |
878 | } | |
879 | #endif | |
880 | } | |
881 | #endif |