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powerpc/mpc85xx: Update clock nodes in device tree
[deliverable/linux.git] / arch / powerpc / sysdev / fsl_pci.c
CommitLineData
b809b3e8 1/*
5b70a097 2 * MPC83xx/85xx/86xx PCI/PCIE support routing.
b809b3e8 3 *
07e4f801 4 * Copyright 2007-2012 Freescale Semiconductor, Inc.
598804cd 5 * Copyright 2008-2009 MontaVista Software, Inc.
b809b3e8 6 *
9ac4dd30
ZR		 7 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
8 * Recode: ZHANG WEI <wei.zhang@freescale.com>
9 * Rewrite the routing for Frescale PCI and PCI Express
10 * Roy Zang <tie-fei.zang@freescale.com>
598804cd
AV		 11 * MPC83xx PCI-Express support:
12 * Tony Li <tony.li@freescale.com>
13 * Anton Vorontsov <avorontsov@ru.mvista.com>
b809b3e8
JL		 14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 */
9ac4dd30 20#include <linux/kernel.h>
b809b3e8 21#include <linux/pci.h>
9ac4dd30
ZR		 22#include <linux/delay.h>
23#include <linux/string.h>
24#include <linux/init.h>
25#include <linux/bootmem.h>
95f72d1e 26#include <linux/memblock.h>
54c18193 27#include <linux/log2.h>
5a0e3ad6 28#include <linux/slab.h>
4e0e3435 29#include <linux/uaccess.h>
b809b3e8 30
b809b3e8
JL		 31#include <asm/io.h>
32#include <asm/prom.h>
b809b3e8 33#include <asm/pci-bridge.h>
4e0e3435 34#include <asm/ppc-pci.h>
9ac4dd30 35#include <asm/machdep.h>
4e0e3435
HJ		 36#include <asm/disassemble.h>
37#include <asm/ppc-opcode.h>
b809b3e8 38#include <sysdev/fsl_soc.h>
55c44991 39#include <sysdev/fsl_pci.h>
b809b3e8 40
b8f44ec2 41static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
598804cd 42
bbd234b1 43static void quirk_fsl_pcie_early(struct pci_dev *dev)
598804cd 44{
59c58c32 45 u8 hdr_type;
470788d4 46
598804cd 47 /* if we aren't a PCIe don't bother */
f0308261 48 if (!pci_is_pcie(dev))
598804cd
AV		 49 return;
50
470788d4 51 /* if we aren't in host mode don't bother */
59c58c32
ML		 52 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type);
53 if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
470788d4
KG		 54 return;
55
598804cd
AV		 56 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
57 fsl_pcie_bus_fixup = 1;
58 return;
59}
60
50d8f87d
RI		 61static int fsl_indirect_read_config(struct pci_bus *, unsigned int,
62 int, int, u32 *);
63
64static int fsl_pcie_check_link(struct pci_controller *hose)
598804cd 65{
50d8f87d 66 u32 val = 0;
598804cd 67
34642bbb 68 if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) {
50d8f87d
RI		 69 if (hose->ops->read == fsl_indirect_read_config) {
70 struct pci_bus bus;
36f68494 71 bus.number = hose->first_busno;
50d8f87d
RI		 72 bus.sysdata = hose;
73 bus.ops = hose->ops;
74 indirect_read_config(&bus, 0, PCIE_LTSSM, 4, &val);
75 } else
76 early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
34642bbb
KG		 77 if (val < PCIE_LTSSM_L0)
78 return 1;
79 } else {
80 struct ccsr_pci __iomem *pci = hose->private_data;
81 /* for PCIe IP rev 3.0 or greater use CSR0 for link state */
82 val = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK)
83 >> PEX_CSR0_LTSSM_SHIFT;
84 if (val != PEX_CSR0_LTSSM_L0)
85 return 1;
cc6ea0dd 86 }
cc6ea0dd 87
598804cd
AV		 88 return 0;
89}
90
50d8f87d
RI		 91static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int devfn,
92 int offset, int len, u32 *val)
93{
94 struct pci_controller *hose = pci_bus_to_host(bus);
95
96 if (fsl_pcie_check_link(hose))
97 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
98 else
99 hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK;
100
101 return indirect_read_config(bus, devfn, offset, len, val);
102}
103
b37e1613
RI		 104#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
105
106static struct pci_ops fsl_indirect_pcie_ops =
50d8f87d
RI		 107{
108 .read = fsl_indirect_read_config,
109 .write = indirect_write_config,
110};
111
96ea3b4a
KG		 112#define MAX_PHYS_ADDR_BITS 40
113static u64 pci64_dma_offset = 1ull << MAX_PHYS_ADDR_BITS;
114
115static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
116{
117 if (!dev->dma_mask || !dma_supported(dev, dma_mask))
118 return -EIO;
119
120 /*
121 * Fixup PCI devices that are able to DMA to above the physical
122 * address width of the SoC such that we can address any internal
123 * SoC address from across PCI if needed
124 */
d317ac17 125 if ((dev_is_pci(dev)) &&
96ea3b4a
KG		 126 dma_mask >= DMA_BIT_MASK(MAX_PHYS_ADDR_BITS)) {
127 set_dma_ops(dev, &dma_direct_ops);
128 set_dma_offset(dev, pci64_dma_offset);
129 }
130
131 *dev->dma_mask = dma_mask;
132 return 0;
133}
134
a393d897 135static int setup_one_atmu(struct ccsr_pci __iomem *pci,
a097a78c
TP		 136 unsigned int index, const struct resource *res,
137 resource_size_t offset)
138{
139 resource_size_t pci_addr = res->start - offset;
140 resource_size_t phys_addr = res->start;
28f65c11 141 resource_size_t size = resource_size(res);
a097a78c
TP		 142 u32 flags = 0x80044000; /* enable & mem R/W */
143 unsigned int i;
144
145 pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n",
146 (u64)res->start, (u64)size);
147
565f3764
TP		 148 if (res->flags & IORESOURCE_PREFETCH)
149 flags |= 0x10000000; /* enable relaxed ordering */
150
a097a78c 151 for (i = 0; size > 0; i++) {
2b4a8bd2 152 unsigned int bits = min(ilog2(size),
a097a78c
TP		 153 __ffs(pci_addr | phys_addr));
154
155 if (index + i >= 5)
156 return -1;
157
158 out_be32(&pci->pow[index + i].potar, pci_addr >> 12);
159 out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44);
160 out_be32(&pci->pow[index + i].powbar, phys_addr >> 12);
161 out_be32(&pci->pow[index + i].powar, flags | (bits - 1));
162
163 pci_addr += (resource_size_t)1U << bits;
164 phys_addr += (resource_size_t)1U << bits;
165 size -= (resource_size_t)1U << bits;
166 }
167
168 return i;
169}
170
9ac4dd30 171/* atmu setup for fsl pci/pcie controller */
34642bbb 172static void setup_pci_atmu(struct pci_controller *hose)
b809b3e8 173{
34642bbb 174 struct ccsr_pci __iomem *pci = hose->private_data;
f4154e16 175 int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4;
54c18193 176 u64 mem, sz, paddr_hi = 0;
3fd47f06 177 u64 offset = 0, paddr_lo = ULLONG_MAX;
54c18193
KG		 178 u32 pcicsrbar = 0, pcicsrbar_sz;
179 u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL |
180 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
c22618a1 181 const char *name = hose->dn->full_name;
446bc1ff
TT		 182 const u64 *reg;
183 int len;
b809b3e8 184
9e67886b
RZ		 185 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
186 if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_2_2) {
187 win_idx = 2;
188 start_idx = 0;
189 end_idx = 3;
190 }
191 }
192
a097a78c 193 /* Disable all windows (except powar0 since it's ignored) */
9ac4dd30
ZR		 194 for(i = 1; i < 5; i++)
195 out_be32(&pci->pow[i].powar, 0);
f4154e16 196 for (i = start_idx; i < end_idx; i++)
9ac4dd30
ZR		 197 out_be32(&pci->piw[i].piwar, 0);
198
199 /* Setup outbound MEM window */
a097a78c
TP		 200 for(i = 0, j = 1; i < 3; i++) {
201 if (!(hose->mem_resources[i].flags & IORESOURCE_MEM))
202 continue;
203
54c18193
KG		 204 paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start);
205 paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end);
206
3fd47f06
BH		 207 /* We assume all memory resources have the same offset */
208 offset = hose->mem_offset[i];
209 n = setup_one_atmu(pci, j, &hose->mem_resources[i], offset);
a097a78c
TP		 210
211 if (n < 0 || j >= 5) {
212 pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i);
213 hose->mem_resources[i].flags |= IORESOURCE_DISABLED;
214 } else
215 j += n;
216 }
9ac4dd30
ZR		 217
218 /* Setup outbound IO window */
a097a78c
TP		 219 if (hose->io_resource.flags & IORESOURCE_IO) {
220 if (j >= 5) {
221 pr_err("Ran out of outbound PCI ATMUs for IO resource\n");
222 } else {
223 pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "
224 "phy base 0x%016llx.\n",
28f65c11
JP		 225 (u64)hose->io_resource.start,
226 (u64)resource_size(&hose->io_resource),
227 (u64)hose->io_base_phys);
a097a78c
TP		 228 out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12));
229 out_be32(&pci->pow[j].potear, 0);
230 out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12));
231 /* Enable, IO R/W */
232 out_be32(&pci->pow[j].powar, 0x80088000
2b4a8bd2 233 | (ilog2(hose->io_resource.end
a097a78c
TP		 234 - hose->io_resource.start + 1) - 1));
235 }
9ac4dd30
ZR		 236 }
237
54c18193 238 /* convert to pci address space */
3fd47f06
BH		 239 paddr_hi -= offset;
240 paddr_lo -= offset;
54c18193
KG		 241
242 if (paddr_hi == paddr_lo) {
243 pr_err("%s: No outbound window space\n", name);
04aa99cd 244 return;
54c18193
KG		 245 }
246
247 if (paddr_lo == 0) {
248 pr_err("%s: No space for inbound window\n", name);
04aa99cd 249 return;
54c18193
KG		 250 }
251
252 /* setup PCSRBAR/PEXCSRBAR */
253 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff);
254 early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
255 pcicsrbar_sz = ~pcicsrbar_sz + 1;
256
257 if (paddr_hi < (0x100000000ull - pcicsrbar_sz) ||
258 (paddr_lo > 0x100000000ull))
259 pcicsrbar = 0x100000000ull - pcicsrbar_sz;
260 else
261 pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz;
262 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar);
263
264 paddr_lo = min(paddr_lo, (u64)pcicsrbar);
265
266 pr_info("%s: PCICSRBAR @ 0x%x\n", name, pcicsrbar);
267
268 /* Setup inbound mem window */
95f72d1e 269 mem = memblock_end_of_DRAM();
446bc1ff
TT		 270
271 /*
272 * The msi-address-64 property, if it exists, indicates the physical
273 * address of the MSIIR register. Normally, this register is located
274 * inside CCSR, so the ATMU that covers all of CCSR is used. But if
275 * this property exists, then we normally need to create a new ATMU
276 * for it. For now, however, we cheat. The only entity that creates
277 * this property is the Freescale hypervisor, and the address is
278 * specified in the partition configuration. Typically, the address
279 * is located in the page immediately after the end of DDR. If so, we
280 * can avoid allocating a new ATMU by extending the DDR ATMU by one
281 * page.
282 */
283 reg = of_get_property(hose->dn, "msi-address-64", &len);
284 if (reg && (len == sizeof(u64))) {
285 u64 address = be64_to_cpup(reg);
286
287 if ((address >= mem) && (address < (mem + PAGE_SIZE))) {
288 pr_info("%s: extending DDR ATMU to cover MSIIR", name);
289 mem += PAGE_SIZE;
290 } else {
291 /* TODO: Create a new ATMU for MSIIR */
292 pr_warn("%s: msi-address-64 address of %llx is "
293 "unsupported\n", name, address);
294 }
295 }
296
54c18193 297 sz = min(mem, paddr_lo);
2b4a8bd2 298 mem_log = ilog2(sz);
54c18193
KG		 299
300 /* PCIe can overmap inbound & outbound since RX & TX are separated */
301 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
302 /* Size window to exact size if power-of-two or one size up */
303 if ((1ull << mem_log) != mem) {
2d49c42a 304 mem_log++;
54c18193
KG		 305 if ((1ull << mem_log) > mem)
306 pr_info("%s: Setting PCI inbound window "
307 "greater than memory size\n", name);
54c18193
KG		 308 }
309
f4154e16 310 piwar |= ((mem_log - 1) & PIWAR_SZ_MASK);
54c18193
KG		 311
312 /* Setup inbound memory window */
313 out_be32(&pci->piw[win_idx].pitar, 0x00000000);
314 out_be32(&pci->piw[win_idx].piwbar, 0x00000000);
315 out_be32(&pci->piw[win_idx].piwar, piwar);
316 win_idx--;
317
318 hose->dma_window_base_cur = 0x00000000;
319 hose->dma_window_size = (resource_size_t)sz;
96ea3b4a
KG		 320
321 /*
322 * if we have >4G of memory setup second PCI inbound window to
323 * let devices that are 64-bit address capable to work w/o
324 * SWIOTLB and access the full range of memory
325 */
326 if (sz != mem) {
2b4a8bd2 327 mem_log = ilog2(mem);
96ea3b4a
KG		 328
329 /* Size window up if we dont fit in exact power-of-2 */
330 if ((1ull << mem_log) != mem)
331 mem_log++;
332
333 piwar = (piwar & ~PIWAR_SZ_MASK) | (mem_log - 1);
334
335 /* Setup inbound memory window */
336 out_be32(&pci->piw[win_idx].pitar, 0x00000000);
337 out_be32(&pci->piw[win_idx].piwbear,
338 pci64_dma_offset >> 44);
339 out_be32(&pci->piw[win_idx].piwbar,
340 pci64_dma_offset >> 12);
341 out_be32(&pci->piw[win_idx].piwar, piwar);
342
343 /*
344 * install our own dma_set_mask handler to fixup dma_ops
345 * and dma_offset
346 */
347 ppc_md.dma_set_mask = fsl_pci_dma_set_mask;
348
349 pr_info("%s: Setup 64-bit PCI DMA window\n", name);
350 }
54c18193
KG		 351 } else {
352 u64 paddr = 0;
353
354 /* Setup inbound memory window */
355 out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
356 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
357 out_be32(&pci->piw[win_idx].piwar, (piwar | (mem_log - 1)));
358 win_idx--;
359
360 paddr += 1ull << mem_log;
361 sz -= 1ull << mem_log;
362
363 if (sz) {
2b4a8bd2 364 mem_log = ilog2(sz);
54c18193
KG		 365 piwar |= (mem_log - 1);
366
367 out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
368 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
369 out_be32(&pci->piw[win_idx].piwar, piwar);
370 win_idx--;
371
372 paddr += 1ull << mem_log;
373 }
374
375 hose->dma_window_base_cur = 0x00000000;
376 hose->dma_window_size = (resource_size_t)paddr;
377 }
a097a78c 378
54c18193 379 if (hose->dma_window_size < mem) {
c45e9183
KH		 380#ifdef CONFIG_SWIOTLB
381 ppc_swiotlb_enable = 1;
382#else
54c18193
KG		 383 pr_err("%s: ERROR: Memory size exceeds PCI ATMU ability to "
384 "map - enable CONFIG_SWIOTLB to avoid dma errors.\n",
385 name);
386#endif
387 /* adjusting outbound windows could reclaim space in mem map */
388 if (paddr_hi < 0xffffffffull)
389 pr_warning("%s: WARNING: Outbound window cfg leaves "
390 "gaps in memory map. Adjusting the memory map "
391 "could reduce unnecessary bounce buffering.\n",
392 name);
393
394 pr_info("%s: DMA window size is 0x%llx\n", name,
395 (u64)hose->dma_window_size);
396 }
b809b3e8
JL		 397}
398
c9dadffb 399static void __init setup_pci_cmd(struct pci_controller *hose)
b809b3e8 400{
b809b3e8 401 u16 cmd;
eb12af43
KG		 402 int cap_x;
403
b809b3e8
JL		 404 early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
405 cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
9ac4dd30 406 | PCI_COMMAND_IO;
b809b3e8 407 early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
eb12af43
KG		 408
409 cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX);
410 if (cap_x) {
411 int pci_x_cmd = cap_x + PCI_X_CMD;
412 cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
413 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
414 early_write_config_word(hose, 0, 0, pci_x_cmd, cmd);
415 } else {
416 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
417 }
9ad494f6
KG		 418}
419
6c0a11c1
KG		 420void fsl_pcibios_fixup_bus(struct pci_bus *bus)
421{
8206a110 422 struct pci_controller *hose = pci_bus_to_host(bus);
13635dfd
BH		 423 int i, is_pcie = 0, no_link;
424
425 /* The root complex bridge comes up with bogus resources,
426 * we copy the PHB ones in.
427 *
428 * With the current generic PCI code, the PHB bus no longer
429 * has bus->resource[0..4] set, so things are a bit more
430 * tricky.
431 */
432
433 if (fsl_pcie_bus_fixup)
434 is_pcie = early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP);
435 no_link = !!(hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK);
436
437 if (bus->parent == hose->bus && (is_pcie || no_link)) {
438 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; ++i) {
72b122cc 439 struct resource *res = bus->resource[i];
13635dfd
BH		 440 struct resource *par;
441
442 if (!res)
443 continue;
444 if (i == 0)
445 par = &hose->io_resource;
446 else if (i < 4)
447 par = &hose->mem_resources[i-1];
448 else par = NULL;
449
450 res->start = par ? par->start : 0;
451 res->end = par ? par->end : 0;
452 res->flags = par ? par->flags : 0;
6c0a11c1
KG		 453 }
454 }
455}
456
1e83bf87 457int fsl_add_bridge(struct platform_device *pdev, int is_primary)
b809b3e8
JL		 458{
459 int len;
460 struct pci_controller *hose;
461 struct resource rsrc;
8efca493 462 const int *bus_range;
59c58c32 463 u8 hdr_type, progif;
52c5affc 464 struct device_node *dev;
34642bbb 465 struct ccsr_pci __iomem *pci;
52c5affc
VS		 466
467 dev = pdev->dev.of_node;
b809b3e8 468
ef1fd2df
PK		 469 if (!of_device_is_available(dev)) {
470 pr_warning("%s: disabled\n", dev->full_name);
471 return -ENODEV;
472 }
473
9ac4dd30 474 pr_debug("Adding PCI host bridge %s\n", dev->full_name);
b809b3e8
JL		 475
476 /* Fetch host bridge registers address */
9ac4dd30
ZR		 477 if (of_address_to_resource(dev, 0, &rsrc)) {
478 printk(KERN_WARNING "Can't get pci register base!");
479 return -ENOMEM;
480 }
b809b3e8
JL		 481
482 /* Get bus range if any */
e2eb6392 483 bus_range = of_get_property(dev, "bus-range", &len);
b809b3e8
JL		 484 if (bus_range == NULL || len < 2 * sizeof(int))
485 printk(KERN_WARNING "Can't get bus-range for %s, assume"
9ac4dd30 486 " bus 0\n", dev->full_name);
b809b3e8 487
0e47ff1c 488 pci_add_flags(PCI_REASSIGN_ALL_BUS);
dbf8471f 489 hose = pcibios_alloc_controller(dev);
b809b3e8
JL		 490 if (!hose)
491 return -ENOMEM;
dbf8471f 492
52c5affc
VS		 493 /* set platform device as the parent */
494 hose->parent = &pdev->dev;
b809b3e8 495 hose->first_busno = bus_range ? bus_range[0] : 0x0;
bf7c036f 496 hose->last_busno = bus_range ? bus_range[1] : 0xff;
b809b3e8 497
34642bbb
KG		 498 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
499 (u64)rsrc.start, (u64)resource_size(&rsrc));
500
501 pci = hose->private_data = ioremap(rsrc.start, resource_size(&rsrc));
502 if (!hose->private_data)
503 goto no_bridge;
504
b37e1613
RI		 505 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
506 PPC_INDIRECT_TYPE_BIG_ENDIAN);
08871c09 507
34642bbb
KG		 508 if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0)
509 hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
510
59c58c32 511 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
b37e1613
RI		 512 /* use fsl_indirect_read_config for PCIe */
513 hose->ops = &fsl_indirect_pcie_ops;
59c58c32
ML		 514 /* For PCIE read HEADER_TYPE to identify controler mode */
515 early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &hdr_type);
516 if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
517 goto no_bridge;
518
519 } else {
520 /* For PCI read PROG to identify controller mode */
521 early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif);
522 if ((progif & 1) == 1)
523 goto no_bridge;
08871c09
PK		 524 }
525
9ac4dd30 526 setup_pci_cmd(hose);
b809b3e8 527
9ac4dd30 528 /* check PCI express link status */
957ecffc 529 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
7659c038 530 hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG |
957ecffc 531 PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
34642bbb 532 if (fsl_pcie_check_link(hose))
957ecffc
KG		 533 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
534 }
b809b3e8 535
df3c9019 536 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
9ac4dd30
ZR		 537 "Firmware bus number: %d->%d\n",
538 (unsigned long long)rsrc.start, hose->first_busno,
539 hose->last_busno);
b809b3e8 540
9ac4dd30 541 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
b809b3e8
JL		 542 hose, hose->cfg_addr, hose->cfg_data);
543
544 /* Interpret the "ranges" property */
545 /* This also maps the I/O region and sets isa_io/mem_base */
9ac4dd30 546 pci_process_bridge_OF_ranges(hose, dev, is_primary);
b809b3e8
JL		 547
548 /* Setup PEX window registers */
34642bbb 549 setup_pci_atmu(hose);
b809b3e8
JL		 550
551 return 0;
59c58c32
ML		 552
553no_bridge:
34642bbb 554 iounmap(hose->private_data);
59c58c32
ML		 555 /* unmap cfg_data & cfg_addr separately if not on same page */
556 if (((unsigned long)hose->cfg_data & PAGE_MASK) !=
557 ((unsigned long)hose->cfg_addr & PAGE_MASK))
558 iounmap(hose->cfg_data);
559 iounmap(hose->cfg_addr);
560 pcibios_free_controller(hose);
561 return -ENODEV;
b809b3e8 562}
5753c082 563#endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
76fe1ffc 564
bbd234b1
CL		 565DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID,
566 quirk_fsl_pcie_early);
598804cd 567
470788d4 568#if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
598804cd
AV		 569struct mpc83xx_pcie_priv {
570 void __iomem *cfg_type0;
571 void __iomem *cfg_type1;
572 u32 dev_base;
573};
574
b8f44ec2
KG		 575struct pex_inbound_window {
576 u32 ar;
577 u32 tar;
578 u32 barl;
579 u32 barh;
580};
581
598804cd
AV		 582/*
583 * With the convention of u-boot, the PCIE outbound window 0 serves
584 * as configuration transactions outbound.
585 */
586#define PEX_OUTWIN0_BAR 0xCA4
587#define PEX_OUTWIN0_TAL 0xCA8
588#define PEX_OUTWIN0_TAH 0xCAC
b8f44ec2
KG		 589#define PEX_RC_INWIN_BASE 0xE60
590#define PEX_RCIWARn_EN 0x1
598804cd
AV		 591
592static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn)
593{
8206a110 594 struct pci_controller *hose = pci_bus_to_host(bus);
598804cd
AV		 595
596 if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)
597 return PCIBIOS_DEVICE_NOT_FOUND;
598 /*
599 * Workaround for the HW bug: for Type 0 configure transactions the
600 * PCI-E controller does not check the device number bits and just
601 * assumes that the device number bits are 0.
602 */
603 if (bus->number == hose->first_busno ||
604 bus->primary == hose->first_busno) {
605 if (devfn & 0xf8)
606 return PCIBIOS_DEVICE_NOT_FOUND;
607 }
608
609 if (ppc_md.pci_exclude_device) {
610 if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
611 return PCIBIOS_DEVICE_NOT_FOUND;
612 }
613
614 return PCIBIOS_SUCCESSFUL;
615}
616
617static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus,
618 unsigned int devfn, int offset)
619{
8206a110 620 struct pci_controller *hose = pci_bus_to_host(bus);
598804cd 621 struct mpc83xx_pcie_priv *pcie = hose->dn->data;
f93611fa 622 u32 dev_base = bus->number << 24 | devfn << 16;
598804cd
AV		 623 int ret;
624
625 ret = mpc83xx_pcie_exclude_device(bus, devfn);
626 if (ret)
627 return NULL;
628
629 offset &= 0xfff;
630
631 /* Type 0 */
632 if (bus->number == hose->first_busno)
633 return pcie->cfg_type0 + offset;
634
635 if (pcie->dev_base == dev_base)
636 goto mapped;
637
638 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base);
639
640 pcie->dev_base = dev_base;
641mapped:
642 return pcie->cfg_type1 + offset;
643}
644
645static int mpc83xx_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
646 int offset, int len, u32 *val)
647{
648 void __iomem *cfg_addr;
649
650 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
651 if (!cfg_addr)
652 return PCIBIOS_DEVICE_NOT_FOUND;
653
654 switch (len) {
655 case 1:
656 *val = in_8(cfg_addr);
657 break;
658 case 2:
659 *val = in_le16(cfg_addr);
660 break;
661 default:
662 *val = in_le32(cfg_addr);
663 break;
664 }
665
666 return PCIBIOS_SUCCESSFUL;
667}
668
669static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
670 int offset, int len, u32 val)
671{
f93611fa 672 struct pci_controller *hose = pci_bus_to_host(bus);
598804cd
AV		 673 void __iomem *cfg_addr;
674
675 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
676 if (!cfg_addr)
677 return PCIBIOS_DEVICE_NOT_FOUND;
678
f93611fa
AV		 679 /* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */
680 if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno)
681 val &= 0xffffff00;
682
598804cd
AV		 683 switch (len) {
684 case 1:
685 out_8(cfg_addr, val);
686 break;
687 case 2:
688 out_le16(cfg_addr, val);
689 break;
690 default:
691 out_le32(cfg_addr, val);
692 break;
693 }
694
695 return PCIBIOS_SUCCESSFUL;
696}
697
698static struct pci_ops mpc83xx_pcie_ops = {
699 .read = mpc83xx_pcie_read_config,
700 .write = mpc83xx_pcie_write_config,
701};
702
703static int __init mpc83xx_pcie_setup(struct pci_controller *hose,
704 struct resource *reg)
705{
706 struct mpc83xx_pcie_priv *pcie;
707 u32 cfg_bar;
708 int ret = -ENOMEM;
709
710 pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL);
711 if (!pcie)
712 return ret;
713
714 pcie->cfg_type0 = ioremap(reg->start, resource_size(reg));
715 if (!pcie->cfg_type0)
716 goto err0;
717
718 cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR);
719 if (!cfg_bar) {
720 /* PCI-E isn't configured. */
721 ret = -ENODEV;
722 goto err1;
723 }
724
725 pcie->cfg_type1 = ioremap(cfg_bar, 0x1000);
726 if (!pcie->cfg_type1)
727 goto err1;
728
729 WARN_ON(hose->dn->data);
730 hose->dn->data = pcie;
731 hose->ops = &mpc83xx_pcie_ops;
34642bbb 732 hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
598804cd
AV		 733
734 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0);
735 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0);
736
34642bbb 737 if (fsl_pcie_check_link(hose))
598804cd
AV		 738 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
739
740 return 0;
741err1:
742 iounmap(pcie->cfg_type0);
743err0:
744 kfree(pcie);
745 return ret;
746
747}
748
76fe1ffc
JR		 749int __init mpc83xx_add_bridge(struct device_node *dev)
750{
598804cd 751 int ret;
76fe1ffc
JR		 752 int len;
753 struct pci_controller *hose;
5b70a097
JR		 754 struct resource rsrc_reg;
755 struct resource rsrc_cfg;
76fe1ffc 756 const int *bus_range;
5b70a097 757 int primary;
76fe1ffc 758
b8f44ec2
KG		 759 is_mpc83xx_pci = 1;
760
598804cd
AV		 761 if (!of_device_is_available(dev)) {
762 pr_warning("%s: disabled by the firmware.\n",
763 dev->full_name);
764 return -ENODEV;
765 }
76fe1ffc
JR		 766 pr_debug("Adding PCI host bridge %s\n", dev->full_name);
767
768 /* Fetch host bridge registers address */
5b70a097
JR		 769 if (of_address_to_resource(dev, 0, &rsrc_reg)) {
770 printk(KERN_WARNING "Can't get pci register base!\n");
771 return -ENOMEM;
772 }
773
774 memset(&rsrc_cfg, 0, sizeof(rsrc_cfg));
775
776 if (of_address_to_resource(dev, 1, &rsrc_cfg)) {
777 printk(KERN_WARNING
778 "No pci config register base in dev tree, "
779 "using default\n");
780 /*
781 * MPC83xx supports up to two host controllers
782 * one at 0x8500 has config space registers at 0x8300
783 * one at 0x8600 has config space registers at 0x8380
784 */
785 if ((rsrc_reg.start & 0xfffff) == 0x8500)
786 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300;
787 else if ((rsrc_reg.start & 0xfffff) == 0x8600)
788 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380;
789 }
790 /*
791 * Controller at offset 0x8500 is primary
792 */
793 if ((rsrc_reg.start & 0xfffff) == 0x8500)
794 primary = 1;
795 else
796 primary = 0;
76fe1ffc
JR		 797
798 /* Get bus range if any */
799 bus_range = of_get_property(dev, "bus-range", &len);
800 if (bus_range == NULL || len < 2 * sizeof(int)) {
801 printk(KERN_WARNING "Can't get bus-range for %s, assume"
802 " bus 0\n", dev->full_name);
803 }
804
0e47ff1c 805 pci_add_flags(PCI_REASSIGN_ALL_BUS);
76fe1ffc
JR		 806 hose = pcibios_alloc_controller(dev);
807 if (!hose)
808 return -ENOMEM;
809
810 hose->first_busno = bus_range ? bus_range[0] : 0;
811 hose->last_busno = bus_range ? bus_range[1] : 0xff;
812
598804cd
AV		 813 if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) {
814 ret = mpc83xx_pcie_setup(hose, &rsrc_reg);
815 if (ret)
816 goto err0;
817 } else {
b37e1613
RI		 818 setup_indirect_pci(hose, rsrc_cfg.start,
819 rsrc_cfg.start + 4, 0);
598804cd 820 }
76fe1ffc 821
35225802 822 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
76fe1ffc 823 "Firmware bus number: %d->%d\n",
5b70a097 824 (unsigned long long)rsrc_reg.start, hose->first_busno,
76fe1ffc
JR		 825 hose->last_busno);
826
827 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
828 hose, hose->cfg_addr, hose->cfg_data);
829
830 /* Interpret the "ranges" property */
831 /* This also maps the I/O region and sets isa_io/mem_base */
832 pci_process_bridge_OF_ranges(hose, dev, primary);
833
834 return 0;
598804cd
AV		 835err0:
836 pcibios_free_controller(hose);
837 return ret;
76fe1ffc
JR		 838}
839#endif /* CONFIG_PPC_83xx */
b8f44ec2
KG		 840
841u64 fsl_pci_immrbar_base(struct pci_controller *hose)
842{
843#ifdef CONFIG_PPC_83xx
844 if (is_mpc83xx_pci) {
845 struct mpc83xx_pcie_priv *pcie = hose->dn->data;
846 struct pex_inbound_window *in;
847 int i;
848
849 /* Walk the Root Complex Inbound windows to match IMMR base */
850 in = pcie->cfg_type0 + PEX_RC_INWIN_BASE;
851 for (i = 0; i < 4; i++) {
852 /* not enabled, skip */
853 if (!in_le32(&in[i].ar) & PEX_RCIWARn_EN)
854 continue;
855
856 if (get_immrbase() == in_le32(&in[i].tar))
857 return (u64)in_le32(&in[i].barh) << 32 |
858 in_le32(&in[i].barl);
859 }
860
861 printk(KERN_WARNING "could not find PCI BAR matching IMMR\n");
862 }
863#endif
864
865#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
866 if (!is_mpc83xx_pci) {
867 u32 base;
868
869 pci_bus_read_config_dword(hose->bus,
870 PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base);
871 return base;
872 }
873#endif
874
875 return 0;
876}
07e4f801 877
4e0e3435
HJ		 878#ifdef CONFIG_E500
879static int mcheck_handle_load(struct pt_regs *regs, u32 inst)
880{
881 unsigned int rd, ra, rb, d;
882
883 rd = get_rt(inst);
884 ra = get_ra(inst);
885 rb = get_rb(inst);
886 d = get_d(inst);
887
888 switch (get_op(inst)) {
889 case 31:
890 switch (get_xop(inst)) {
891 case OP_31_XOP_LWZX:
892 case OP_31_XOP_LWBRX:
893 regs->gpr[rd] = 0xffffffff;
894 break;
895
896 case OP_31_XOP_LWZUX:
897 regs->gpr[rd] = 0xffffffff;
898 regs->gpr[ra] += regs->gpr[rb];
899 break;
900
901 case OP_31_XOP_LBZX:
902 regs->gpr[rd] = 0xff;
903 break;
904
905 case OP_31_XOP_LBZUX:
906 regs->gpr[rd] = 0xff;
907 regs->gpr[ra] += regs->gpr[rb];
908 break;
909
910 case OP_31_XOP_LHZX:
911 case OP_31_XOP_LHBRX:
912 regs->gpr[rd] = 0xffff;
913 break;
914
915 case OP_31_XOP_LHZUX:
916 regs->gpr[rd] = 0xffff;
917 regs->gpr[ra] += regs->gpr[rb];
918 break;
919
920 case OP_31_XOP_LHAX:
921 regs->gpr[rd] = ~0UL;
922 break;
923
924 case OP_31_XOP_LHAUX:
925 regs->gpr[rd] = ~0UL;
926 regs->gpr[ra] += regs->gpr[rb];
927 break;
928
929 default:
930 return 0;
931 }
932 break;
933
934 case OP_LWZ:
935 regs->gpr[rd] = 0xffffffff;
936 break;
937
938 case OP_LWZU:
939 regs->gpr[rd] = 0xffffffff;
940 regs->gpr[ra] += (s16)d;
941 break;
942
943 case OP_LBZ:
944 regs->gpr[rd] = 0xff;
945 break;
946
947 case OP_LBZU:
948 regs->gpr[rd] = 0xff;
949 regs->gpr[ra] += (s16)d;
950 break;
951
952 case OP_LHZ:
953 regs->gpr[rd] = 0xffff;
954 break;
955
956 case OP_LHZU:
957 regs->gpr[rd] = 0xffff;
958 regs->gpr[ra] += (s16)d;
959 break;
960
961 case OP_LHA:
962 regs->gpr[rd] = ~0UL;
963 break;
964
965 case OP_LHAU:
966 regs->gpr[rd] = ~0UL;
967 regs->gpr[ra] += (s16)d;
968 break;
969
970 default:
971 return 0;
972 }
973
974 return 1;
975}
976
977static int is_in_pci_mem_space(phys_addr_t addr)
978{
979 struct pci_controller *hose;
980 struct resource *res;
981 int i;
982
983 list_for_each_entry(hose, &hose_list, list_node) {
984 if (!(hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG))
985 continue;
986
987 for (i = 0; i < 3; i++) {
988 res = &hose->mem_resources[i];
989 if ((res->flags & IORESOURCE_MEM) &&
990 addr >= res->start && addr <= res->end)
991 return 1;
992 }
993 }
994 return 0;
995}
996
997int fsl_pci_mcheck_exception(struct pt_regs *regs)
998{
999 u32 inst;
1000 int ret;
1001 phys_addr_t addr = 0;
1002
1003 /* Let KVM/QEMU deal with the exception */
1004 if (regs->msr & MSR_GS)
1005 return 0;
1006
1007#ifdef CONFIG_PHYS_64BIT
1008 addr = mfspr(SPRN_MCARU);
1009 addr <<= 32;
1010#endif
1011 addr += mfspr(SPRN_MCAR);
1012
1013 if (is_in_pci_mem_space(addr)) {
1014 if (user_mode(regs)) {
1015 pagefault_disable();
1016 ret = get_user(regs->nip, &inst);
1017 pagefault_enable();
1018 } else {
1019 ret = probe_kernel_address(regs->nip, inst);
1020 }
1021
1022 if (mcheck_handle_load(regs, inst)) {
1023 regs->nip += 4;
1024 return 1;
1025 }
1026 }
1027
1028 return 0;
1029}
1030#endif
1031
07e4f801
SW		 1032#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
1033static const struct of_device_id pci_ids[] = {
1034 { .compatible = "fsl,mpc8540-pci", },
1035 { .compatible = "fsl,mpc8548-pcie", },
1036 { .compatible = "fsl,mpc8610-pci", },
1037 { .compatible = "fsl,mpc8641-pcie", },
d064f30e 1038 { .compatible = "fsl,qoriq-pcie", },
14bdc913
TT		 1039 { .compatible = "fsl,qoriq-pcie-v2.1", },
1040 { .compatible = "fsl,qoriq-pcie-v2.2", },
1041 { .compatible = "fsl,qoriq-pcie-v2.3", },
1042 { .compatible = "fsl,qoriq-pcie-v2.4", },
cc6ea0dd 1043 { .compatible = "fsl,qoriq-pcie-v3.0", },
14bdc913
TT		 1044
1045 /*
1046 * The following entries are for compatibility with older device
1047 * trees.
1048 */
07e4f801 1049 { .compatible = "fsl,p1022-pcie", },
07e4f801 1050 { .compatible = "fsl,p4080-pcie", },
14bdc913 1051
07e4f801
SW		 1052 {},
1053};
1054
1055struct device_node *fsl_pci_primary;
1056
905e75c4 1057void fsl_pci_assign_primary(void)
07e4f801 1058{
905e75c4 1059 struct device_node *np;
07e4f801
SW		 1060
1061 /* Callers can specify the primary bus using other means. */
905e75c4
JH		 1062 if (fsl_pci_primary)
1063 return;
1064
1065 /* If a PCI host bridge contains an ISA node, it's primary. */
1066 np = of_find_node_by_type(NULL, "isa");
1067 while ((fsl_pci_primary = of_get_parent(np))) {
1068 of_node_put(np);
1069 np = fsl_pci_primary;
1070
1071 if (of_match_node(pci_ids, np) && of_device_is_available(np))
1072 return;
07e4f801
SW		 1073 }
1074
905e75c4
JH		 1075 /*
1076 * If there's no PCI host bridge with ISA, arbitrarily
1077 * designate one as primary. This can go away once
1078 * various bugs with primary-less systems are fixed.
1079 */
1080 for_each_matching_node(np, pci_ids) {
1081 if (of_device_is_available(np)) {
1082 fsl_pci_primary = np;
1083 of_node_put(np);
1084 return;
07e4f801
SW		 1085 }
1086 }
905e75c4
JH		 1087}
1088
cad5cef6 1089static int fsl_pci_probe(struct platform_device *pdev)
905e75c4
JH		 1090{
1091 int ret;
1092 struct device_node *node;
905e75c4
JH		 1093
1094 node = pdev->dev.of_node;
52c5affc 1095 ret = fsl_add_bridge(pdev, fsl_pci_primary == node);
07e4f801 1096
905e75c4
JH		 1097 mpc85xx_pci_err_probe(pdev);
1098
1099 return 0;
1100}
1101
a393d897
JH		 1102#ifdef CONFIG_PM
1103static int fsl_pci_resume(struct device *dev)
1104{
1105 struct pci_controller *hose;
1106 struct resource pci_rsrc;
1107
1108 hose = pci_find_hose_for_OF_device(dev->of_node);
1109 if (!hose)
1110 return -ENODEV;
1111
1112 if (of_address_to_resource(dev->of_node, 0, &pci_rsrc)) {
1113 dev_err(dev, "Get pci register base failed.");
1114 return -ENODEV;
1115 }
1116
d5bbe659 1117 setup_pci_atmu(hose);
a393d897
JH		 1118
1119 return 0;
1120}
1121
1122static const struct dev_pm_ops pci_pm_ops = {
1123 .resume = fsl_pci_resume,
1124};
1125
1126#define PCI_PM_OPS (&pci_pm_ops)
1127
1128#else
1129
1130#define PCI_PM_OPS NULL
1131
1132#endif
1133
905e75c4
JH		 1134static struct platform_driver fsl_pci_driver = {
1135 .driver = {
1136 .name = "fsl-pci",
a393d897 1137 .pm = PCI_PM_OPS,
905e75c4
JH		 1138 .of_match_table = pci_ids,
1139 },
1140 .probe = fsl_pci_probe,
1141};
1142
1143static int __init fsl_pci_init(void)
1144{
1145 return platform_driver_register(&fsl_pci_driver);
07e4f801 1146}
905e75c4 1147arch_initcall(fsl_pci_init);
07e4f801 1148#endif
Linux kernel - Deliverables
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