Commit | Line | Data |
---|---|---|
b809b3e8 | 1 | /* |
5b70a097 | 2 | * MPC83xx/85xx/86xx PCI/PCIE support routing. |
b809b3e8 | 3 | * |
07e4f801 | 4 | * Copyright 2007-2012 Freescale Semiconductor, Inc. |
598804cd | 5 | * Copyright 2008-2009 MontaVista Software, Inc. |
b809b3e8 | 6 | * |
9ac4dd30 ZR |
7 | * Initial author: Xianghua Xiao <x.xiao@freescale.com> |
8 | * Recode: ZHANG WEI <wei.zhang@freescale.com> | |
9 | * Rewrite the routing for Frescale PCI and PCI Express | |
10 | * Roy Zang <tie-fei.zang@freescale.com> | |
598804cd AV |
11 | * MPC83xx PCI-Express support: |
12 | * Tony Li <tony.li@freescale.com> | |
13 | * Anton Vorontsov <avorontsov@ru.mvista.com> | |
b809b3e8 JL |
14 | * |
15 | * This program is free software; you can redistribute it and/or modify it | |
16 | * under the terms of the GNU General Public License as published by the | |
17 | * Free Software Foundation; either version 2 of the License, or (at your | |
18 | * option) any later version. | |
19 | */ | |
9ac4dd30 | 20 | #include <linux/kernel.h> |
b809b3e8 | 21 | #include <linux/pci.h> |
9ac4dd30 ZR |
22 | #include <linux/delay.h> |
23 | #include <linux/string.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/bootmem.h> | |
95f72d1e | 26 | #include <linux/memblock.h> |
54c18193 | 27 | #include <linux/log2.h> |
5a0e3ad6 | 28 | #include <linux/slab.h> |
b809b3e8 | 29 | |
b809b3e8 JL |
30 | #include <asm/io.h> |
31 | #include <asm/prom.h> | |
b809b3e8 | 32 | #include <asm/pci-bridge.h> |
9ac4dd30 | 33 | #include <asm/machdep.h> |
b809b3e8 | 34 | #include <sysdev/fsl_soc.h> |
55c44991 | 35 | #include <sysdev/fsl_pci.h> |
b809b3e8 | 36 | |
b8f44ec2 | 37 | static int fsl_pcie_bus_fixup, is_mpc83xx_pci; |
598804cd | 38 | |
dea0ed4a | 39 | static void __devinit quirk_fsl_pcie_header(struct pci_dev *dev) |
598804cd | 40 | { |
470788d4 KG |
41 | u8 progif; |
42 | ||
598804cd AV |
43 | /* if we aren't a PCIe don't bother */ |
44 | if (!pci_find_capability(dev, PCI_CAP_ID_EXP)) | |
45 | return; | |
46 | ||
470788d4 KG |
47 | /* if we aren't in host mode don't bother */ |
48 | pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); | |
49 | if (progif & 0x1) | |
50 | return; | |
51 | ||
598804cd AV |
52 | dev->class = PCI_CLASS_BRIDGE_PCI << 8; |
53 | fsl_pcie_bus_fixup = 1; | |
54 | return; | |
55 | } | |
56 | ||
57 | static int __init fsl_pcie_check_link(struct pci_controller *hose) | |
58 | { | |
59 | u32 val; | |
60 | ||
61 | early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val); | |
62 | if (val < PCIE_LTSSM_L0) | |
63 | return 1; | |
64 | return 0; | |
65 | } | |
66 | ||
5753c082 | 67 | #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) |
96ea3b4a KG |
68 | |
69 | #define MAX_PHYS_ADDR_BITS 40 | |
70 | static u64 pci64_dma_offset = 1ull << MAX_PHYS_ADDR_BITS; | |
71 | ||
72 | static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask) | |
73 | { | |
74 | if (!dev->dma_mask || !dma_supported(dev, dma_mask)) | |
75 | return -EIO; | |
76 | ||
77 | /* | |
78 | * Fixup PCI devices that are able to DMA to above the physical | |
79 | * address width of the SoC such that we can address any internal | |
80 | * SoC address from across PCI if needed | |
81 | */ | |
82 | if ((dev->bus == &pci_bus_type) && | |
83 | dma_mask >= DMA_BIT_MASK(MAX_PHYS_ADDR_BITS)) { | |
84 | set_dma_ops(dev, &dma_direct_ops); | |
85 | set_dma_offset(dev, pci64_dma_offset); | |
86 | } | |
87 | ||
88 | *dev->dma_mask = dma_mask; | |
89 | return 0; | |
90 | } | |
91 | ||
a097a78c TP |
92 | static int __init setup_one_atmu(struct ccsr_pci __iomem *pci, |
93 | unsigned int index, const struct resource *res, | |
94 | resource_size_t offset) | |
95 | { | |
96 | resource_size_t pci_addr = res->start - offset; | |
97 | resource_size_t phys_addr = res->start; | |
28f65c11 | 98 | resource_size_t size = resource_size(res); |
a097a78c TP |
99 | u32 flags = 0x80044000; /* enable & mem R/W */ |
100 | unsigned int i; | |
101 | ||
102 | pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n", | |
103 | (u64)res->start, (u64)size); | |
104 | ||
565f3764 TP |
105 | if (res->flags & IORESOURCE_PREFETCH) |
106 | flags |= 0x10000000; /* enable relaxed ordering */ | |
107 | ||
a097a78c TP |
108 | for (i = 0; size > 0; i++) { |
109 | unsigned int bits = min(__ilog2(size), | |
110 | __ffs(pci_addr | phys_addr)); | |
111 | ||
112 | if (index + i >= 5) | |
113 | return -1; | |
114 | ||
115 | out_be32(&pci->pow[index + i].potar, pci_addr >> 12); | |
116 | out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44); | |
117 | out_be32(&pci->pow[index + i].powbar, phys_addr >> 12); | |
118 | out_be32(&pci->pow[index + i].powar, flags | (bits - 1)); | |
119 | ||
120 | pci_addr += (resource_size_t)1U << bits; | |
121 | phys_addr += (resource_size_t)1U << bits; | |
122 | size -= (resource_size_t)1U << bits; | |
123 | } | |
124 | ||
125 | return i; | |
126 | } | |
127 | ||
9ac4dd30 | 128 | /* atmu setup for fsl pci/pcie controller */ |
c9dadffb AV |
129 | static void __init setup_pci_atmu(struct pci_controller *hose, |
130 | struct resource *rsrc) | |
b809b3e8 | 131 | { |
9ac4dd30 | 132 | struct ccsr_pci __iomem *pci; |
f4154e16 | 133 | int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4; |
54c18193 KG |
134 | u64 mem, sz, paddr_hi = 0; |
135 | u64 paddr_lo = ULLONG_MAX; | |
136 | u32 pcicsrbar = 0, pcicsrbar_sz; | |
137 | u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL | | |
138 | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; | |
139 | char *name = hose->dn->full_name; | |
446bc1ff TT |
140 | const u64 *reg; |
141 | int len; | |
b809b3e8 | 142 | |
72b122cc | 143 | pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n", |
28f65c11 | 144 | (u64)rsrc->start, (u64)resource_size(rsrc)); |
f4154e16 | 145 | |
28f65c11 | 146 | pci = ioremap(rsrc->start, resource_size(rsrc)); |
a097a78c TP |
147 | if (!pci) { |
148 | dev_err(hose->parent, "Unable to map ATMU registers\n"); | |
149 | return; | |
150 | } | |
9ac4dd30 | 151 | |
9e67886b RZ |
152 | if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { |
153 | if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_2_2) { | |
154 | win_idx = 2; | |
155 | start_idx = 0; | |
156 | end_idx = 3; | |
157 | } | |
158 | } | |
159 | ||
a097a78c | 160 | /* Disable all windows (except powar0 since it's ignored) */ |
9ac4dd30 ZR |
161 | for(i = 1; i < 5; i++) |
162 | out_be32(&pci->pow[i].powar, 0); | |
f4154e16 | 163 | for (i = start_idx; i < end_idx; i++) |
9ac4dd30 ZR |
164 | out_be32(&pci->piw[i].piwar, 0); |
165 | ||
166 | /* Setup outbound MEM window */ | |
a097a78c TP |
167 | for(i = 0, j = 1; i < 3; i++) { |
168 | if (!(hose->mem_resources[i].flags & IORESOURCE_MEM)) | |
169 | continue; | |
170 | ||
54c18193 KG |
171 | paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start); |
172 | paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end); | |
173 | ||
a097a78c TP |
174 | n = setup_one_atmu(pci, j, &hose->mem_resources[i], |
175 | hose->pci_mem_offset); | |
176 | ||
177 | if (n < 0 || j >= 5) { | |
178 | pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i); | |
179 | hose->mem_resources[i].flags |= IORESOURCE_DISABLED; | |
180 | } else | |
181 | j += n; | |
182 | } | |
9ac4dd30 ZR |
183 | |
184 | /* Setup outbound IO window */ | |
a097a78c TP |
185 | if (hose->io_resource.flags & IORESOURCE_IO) { |
186 | if (j >= 5) { | |
187 | pr_err("Ran out of outbound PCI ATMUs for IO resource\n"); | |
188 | } else { | |
189 | pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, " | |
190 | "phy base 0x%016llx.\n", | |
28f65c11 JP |
191 | (u64)hose->io_resource.start, |
192 | (u64)resource_size(&hose->io_resource), | |
193 | (u64)hose->io_base_phys); | |
a097a78c TP |
194 | out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12)); |
195 | out_be32(&pci->pow[j].potear, 0); | |
196 | out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12)); | |
197 | /* Enable, IO R/W */ | |
198 | out_be32(&pci->pow[j].powar, 0x80088000 | |
199 | | (__ilog2(hose->io_resource.end | |
200 | - hose->io_resource.start + 1) - 1)); | |
201 | } | |
9ac4dd30 ZR |
202 | } |
203 | ||
54c18193 KG |
204 | /* convert to pci address space */ |
205 | paddr_hi -= hose->pci_mem_offset; | |
206 | paddr_lo -= hose->pci_mem_offset; | |
207 | ||
208 | if (paddr_hi == paddr_lo) { | |
209 | pr_err("%s: No outbound window space\n", name); | |
0cf572dc | 210 | goto out; |
54c18193 KG |
211 | } |
212 | ||
213 | if (paddr_lo == 0) { | |
214 | pr_err("%s: No space for inbound window\n", name); | |
0cf572dc | 215 | goto out; |
54c18193 KG |
216 | } |
217 | ||
218 | /* setup PCSRBAR/PEXCSRBAR */ | |
219 | early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff); | |
220 | early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz); | |
221 | pcicsrbar_sz = ~pcicsrbar_sz + 1; | |
222 | ||
223 | if (paddr_hi < (0x100000000ull - pcicsrbar_sz) || | |
224 | (paddr_lo > 0x100000000ull)) | |
225 | pcicsrbar = 0x100000000ull - pcicsrbar_sz; | |
226 | else | |
227 | pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz; | |
228 | early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar); | |
229 | ||
230 | paddr_lo = min(paddr_lo, (u64)pcicsrbar); | |
231 | ||
232 | pr_info("%s: PCICSRBAR @ 0x%x\n", name, pcicsrbar); | |
233 | ||
234 | /* Setup inbound mem window */ | |
95f72d1e | 235 | mem = memblock_end_of_DRAM(); |
446bc1ff TT |
236 | |
237 | /* | |
238 | * The msi-address-64 property, if it exists, indicates the physical | |
239 | * address of the MSIIR register. Normally, this register is located | |
240 | * inside CCSR, so the ATMU that covers all of CCSR is used. But if | |
241 | * this property exists, then we normally need to create a new ATMU | |
242 | * for it. For now, however, we cheat. The only entity that creates | |
243 | * this property is the Freescale hypervisor, and the address is | |
244 | * specified in the partition configuration. Typically, the address | |
245 | * is located in the page immediately after the end of DDR. If so, we | |
246 | * can avoid allocating a new ATMU by extending the DDR ATMU by one | |
247 | * page. | |
248 | */ | |
249 | reg = of_get_property(hose->dn, "msi-address-64", &len); | |
250 | if (reg && (len == sizeof(u64))) { | |
251 | u64 address = be64_to_cpup(reg); | |
252 | ||
253 | if ((address >= mem) && (address < (mem + PAGE_SIZE))) { | |
254 | pr_info("%s: extending DDR ATMU to cover MSIIR", name); | |
255 | mem += PAGE_SIZE; | |
256 | } else { | |
257 | /* TODO: Create a new ATMU for MSIIR */ | |
258 | pr_warn("%s: msi-address-64 address of %llx is " | |
259 | "unsupported\n", name, address); | |
260 | } | |
261 | } | |
262 | ||
54c18193 KG |
263 | sz = min(mem, paddr_lo); |
264 | mem_log = __ilog2_u64(sz); | |
265 | ||
266 | /* PCIe can overmap inbound & outbound since RX & TX are separated */ | |
267 | if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { | |
268 | /* Size window to exact size if power-of-two or one size up */ | |
269 | if ((1ull << mem_log) != mem) { | |
270 | if ((1ull << mem_log) > mem) | |
271 | pr_info("%s: Setting PCI inbound window " | |
272 | "greater than memory size\n", name); | |
273 | mem_log++; | |
274 | } | |
275 | ||
f4154e16 | 276 | piwar |= ((mem_log - 1) & PIWAR_SZ_MASK); |
54c18193 KG |
277 | |
278 | /* Setup inbound memory window */ | |
279 | out_be32(&pci->piw[win_idx].pitar, 0x00000000); | |
280 | out_be32(&pci->piw[win_idx].piwbar, 0x00000000); | |
281 | out_be32(&pci->piw[win_idx].piwar, piwar); | |
282 | win_idx--; | |
283 | ||
284 | hose->dma_window_base_cur = 0x00000000; | |
285 | hose->dma_window_size = (resource_size_t)sz; | |
96ea3b4a KG |
286 | |
287 | /* | |
288 | * if we have >4G of memory setup second PCI inbound window to | |
289 | * let devices that are 64-bit address capable to work w/o | |
290 | * SWIOTLB and access the full range of memory | |
291 | */ | |
292 | if (sz != mem) { | |
293 | mem_log = __ilog2_u64(mem); | |
294 | ||
295 | /* Size window up if we dont fit in exact power-of-2 */ | |
296 | if ((1ull << mem_log) != mem) | |
297 | mem_log++; | |
298 | ||
299 | piwar = (piwar & ~PIWAR_SZ_MASK) | (mem_log - 1); | |
300 | ||
301 | /* Setup inbound memory window */ | |
302 | out_be32(&pci->piw[win_idx].pitar, 0x00000000); | |
303 | out_be32(&pci->piw[win_idx].piwbear, | |
304 | pci64_dma_offset >> 44); | |
305 | out_be32(&pci->piw[win_idx].piwbar, | |
306 | pci64_dma_offset >> 12); | |
307 | out_be32(&pci->piw[win_idx].piwar, piwar); | |
308 | ||
309 | /* | |
310 | * install our own dma_set_mask handler to fixup dma_ops | |
311 | * and dma_offset | |
312 | */ | |
313 | ppc_md.dma_set_mask = fsl_pci_dma_set_mask; | |
314 | ||
315 | pr_info("%s: Setup 64-bit PCI DMA window\n", name); | |
316 | } | |
54c18193 KG |
317 | } else { |
318 | u64 paddr = 0; | |
319 | ||
320 | /* Setup inbound memory window */ | |
321 | out_be32(&pci->piw[win_idx].pitar, paddr >> 12); | |
322 | out_be32(&pci->piw[win_idx].piwbar, paddr >> 12); | |
323 | out_be32(&pci->piw[win_idx].piwar, (piwar | (mem_log - 1))); | |
324 | win_idx--; | |
325 | ||
326 | paddr += 1ull << mem_log; | |
327 | sz -= 1ull << mem_log; | |
328 | ||
329 | if (sz) { | |
330 | mem_log = __ilog2_u64(sz); | |
331 | piwar |= (mem_log - 1); | |
332 | ||
333 | out_be32(&pci->piw[win_idx].pitar, paddr >> 12); | |
334 | out_be32(&pci->piw[win_idx].piwbar, paddr >> 12); | |
335 | out_be32(&pci->piw[win_idx].piwar, piwar); | |
336 | win_idx--; | |
337 | ||
338 | paddr += 1ull << mem_log; | |
339 | } | |
340 | ||
341 | hose->dma_window_base_cur = 0x00000000; | |
342 | hose->dma_window_size = (resource_size_t)paddr; | |
343 | } | |
a097a78c | 344 | |
54c18193 KG |
345 | if (hose->dma_window_size < mem) { |
346 | #ifndef CONFIG_SWIOTLB | |
347 | pr_err("%s: ERROR: Memory size exceeds PCI ATMU ability to " | |
348 | "map - enable CONFIG_SWIOTLB to avoid dma errors.\n", | |
349 | name); | |
350 | #endif | |
351 | /* adjusting outbound windows could reclaim space in mem map */ | |
352 | if (paddr_hi < 0xffffffffull) | |
353 | pr_warning("%s: WARNING: Outbound window cfg leaves " | |
354 | "gaps in memory map. Adjusting the memory map " | |
355 | "could reduce unnecessary bounce buffering.\n", | |
356 | name); | |
357 | ||
358 | pr_info("%s: DMA window size is 0x%llx\n", name, | |
359 | (u64)hose->dma_window_size); | |
360 | } | |
89d93347 | 361 | |
0cf572dc | 362 | out: |
a097a78c | 363 | iounmap(pci); |
b809b3e8 JL |
364 | } |
365 | ||
c9dadffb | 366 | static void __init setup_pci_cmd(struct pci_controller *hose) |
b809b3e8 | 367 | { |
b809b3e8 | 368 | u16 cmd; |
eb12af43 KG |
369 | int cap_x; |
370 | ||
b809b3e8 JL |
371 | early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd); |
372 | cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | |
9ac4dd30 | 373 | | PCI_COMMAND_IO; |
b809b3e8 | 374 | early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd); |
eb12af43 KG |
375 | |
376 | cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX); | |
377 | if (cap_x) { | |
378 | int pci_x_cmd = cap_x + PCI_X_CMD; | |
379 | cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ | |
380 | | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; | |
381 | early_write_config_word(hose, 0, 0, pci_x_cmd, cmd); | |
382 | } else { | |
383 | early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80); | |
384 | } | |
9ad494f6 KG |
385 | } |
386 | ||
6c0a11c1 KG |
387 | void fsl_pcibios_fixup_bus(struct pci_bus *bus) |
388 | { | |
8206a110 | 389 | struct pci_controller *hose = pci_bus_to_host(bus); |
13635dfd BH |
390 | int i, is_pcie = 0, no_link; |
391 | ||
392 | /* The root complex bridge comes up with bogus resources, | |
393 | * we copy the PHB ones in. | |
394 | * | |
395 | * With the current generic PCI code, the PHB bus no longer | |
396 | * has bus->resource[0..4] set, so things are a bit more | |
397 | * tricky. | |
398 | */ | |
399 | ||
400 | if (fsl_pcie_bus_fixup) | |
401 | is_pcie = early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP); | |
402 | no_link = !!(hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK); | |
403 | ||
404 | if (bus->parent == hose->bus && (is_pcie || no_link)) { | |
405 | for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; ++i) { | |
72b122cc | 406 | struct resource *res = bus->resource[i]; |
13635dfd BH |
407 | struct resource *par; |
408 | ||
409 | if (!res) | |
410 | continue; | |
411 | if (i == 0) | |
412 | par = &hose->io_resource; | |
413 | else if (i < 4) | |
414 | par = &hose->mem_resources[i-1]; | |
415 | else par = NULL; | |
416 | ||
417 | res->start = par ? par->start : 0; | |
418 | res->end = par ? par->end : 0; | |
419 | res->flags = par ? par->flags : 0; | |
6c0a11c1 KG |
420 | } |
421 | } | |
422 | } | |
423 | ||
9ac4dd30 | 424 | int __init fsl_add_bridge(struct device_node *dev, int is_primary) |
b809b3e8 JL |
425 | { |
426 | int len; | |
427 | struct pci_controller *hose; | |
428 | struct resource rsrc; | |
8efca493 | 429 | const int *bus_range; |
08871c09 | 430 | u8 progif; |
b809b3e8 | 431 | |
ef1fd2df PK |
432 | if (!of_device_is_available(dev)) { |
433 | pr_warning("%s: disabled\n", dev->full_name); | |
434 | return -ENODEV; | |
435 | } | |
436 | ||
9ac4dd30 | 437 | pr_debug("Adding PCI host bridge %s\n", dev->full_name); |
b809b3e8 JL |
438 | |
439 | /* Fetch host bridge registers address */ | |
9ac4dd30 ZR |
440 | if (of_address_to_resource(dev, 0, &rsrc)) { |
441 | printk(KERN_WARNING "Can't get pci register base!"); | |
442 | return -ENOMEM; | |
443 | } | |
b809b3e8 JL |
444 | |
445 | /* Get bus range if any */ | |
e2eb6392 | 446 | bus_range = of_get_property(dev, "bus-range", &len); |
b809b3e8 JL |
447 | if (bus_range == NULL || len < 2 * sizeof(int)) |
448 | printk(KERN_WARNING "Can't get bus-range for %s, assume" | |
9ac4dd30 | 449 | " bus 0\n", dev->full_name); |
b809b3e8 | 450 | |
0e47ff1c | 451 | pci_add_flags(PCI_REASSIGN_ALL_BUS); |
dbf8471f | 452 | hose = pcibios_alloc_controller(dev); |
b809b3e8 JL |
453 | if (!hose) |
454 | return -ENOMEM; | |
dbf8471f | 455 | |
b809b3e8 | 456 | hose->first_busno = bus_range ? bus_range[0] : 0x0; |
bf7c036f | 457 | hose->last_busno = bus_range ? bus_range[1] : 0xff; |
b809b3e8 | 458 | |
2e56ff20 KG |
459 | setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4, |
460 | PPC_INDIRECT_TYPE_BIG_ENDIAN); | |
08871c09 PK |
461 | |
462 | early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif); | |
463 | if ((progif & 1) == 1) { | |
464 | /* unmap cfg_data & cfg_addr separately if not on same page */ | |
465 | if (((unsigned long)hose->cfg_data & PAGE_MASK) != | |
466 | ((unsigned long)hose->cfg_addr & PAGE_MASK)) | |
467 | iounmap(hose->cfg_data); | |
468 | iounmap(hose->cfg_addr); | |
469 | pcibios_free_controller(hose); | |
c9f11c30 | 470 | return -ENODEV; |
08871c09 PK |
471 | } |
472 | ||
9ac4dd30 | 473 | setup_pci_cmd(hose); |
b809b3e8 | 474 | |
9ac4dd30 | 475 | /* check PCI express link status */ |
957ecffc | 476 | if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { |
7659c038 | 477 | hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG | |
957ecffc | 478 | PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS; |
9ac4dd30 | 479 | if (fsl_pcie_check_link(hose)) |
957ecffc KG |
480 | hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; |
481 | } | |
b809b3e8 | 482 | |
df3c9019 | 483 | printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. " |
9ac4dd30 ZR |
484 | "Firmware bus number: %d->%d\n", |
485 | (unsigned long long)rsrc.start, hose->first_busno, | |
486 | hose->last_busno); | |
b809b3e8 | 487 | |
9ac4dd30 | 488 | pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", |
b809b3e8 JL |
489 | hose, hose->cfg_addr, hose->cfg_data); |
490 | ||
491 | /* Interpret the "ranges" property */ | |
492 | /* This also maps the I/O region and sets isa_io/mem_base */ | |
9ac4dd30 | 493 | pci_process_bridge_OF_ranges(hose, dev, is_primary); |
b809b3e8 JL |
494 | |
495 | /* Setup PEX window registers */ | |
9ac4dd30 | 496 | setup_pci_atmu(hose, &rsrc); |
b809b3e8 JL |
497 | |
498 | return 0; | |
499 | } | |
5753c082 | 500 | #endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */ |
76fe1ffc | 501 | |
470788d4 | 502 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_pcie_header); |
598804cd | 503 | |
470788d4 | 504 | #if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x) |
598804cd AV |
505 | struct mpc83xx_pcie_priv { |
506 | void __iomem *cfg_type0; | |
507 | void __iomem *cfg_type1; | |
508 | u32 dev_base; | |
509 | }; | |
510 | ||
b8f44ec2 KG |
511 | struct pex_inbound_window { |
512 | u32 ar; | |
513 | u32 tar; | |
514 | u32 barl; | |
515 | u32 barh; | |
516 | }; | |
517 | ||
598804cd AV |
518 | /* |
519 | * With the convention of u-boot, the PCIE outbound window 0 serves | |
520 | * as configuration transactions outbound. | |
521 | */ | |
522 | #define PEX_OUTWIN0_BAR 0xCA4 | |
523 | #define PEX_OUTWIN0_TAL 0xCA8 | |
524 | #define PEX_OUTWIN0_TAH 0xCAC | |
b8f44ec2 KG |
525 | #define PEX_RC_INWIN_BASE 0xE60 |
526 | #define PEX_RCIWARn_EN 0x1 | |
598804cd AV |
527 | |
528 | static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn) | |
529 | { | |
8206a110 | 530 | struct pci_controller *hose = pci_bus_to_host(bus); |
598804cd AV |
531 | |
532 | if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) | |
533 | return PCIBIOS_DEVICE_NOT_FOUND; | |
534 | /* | |
535 | * Workaround for the HW bug: for Type 0 configure transactions the | |
536 | * PCI-E controller does not check the device number bits and just | |
537 | * assumes that the device number bits are 0. | |
538 | */ | |
539 | if (bus->number == hose->first_busno || | |
540 | bus->primary == hose->first_busno) { | |
541 | if (devfn & 0xf8) | |
542 | return PCIBIOS_DEVICE_NOT_FOUND; | |
543 | } | |
544 | ||
545 | if (ppc_md.pci_exclude_device) { | |
546 | if (ppc_md.pci_exclude_device(hose, bus->number, devfn)) | |
547 | return PCIBIOS_DEVICE_NOT_FOUND; | |
548 | } | |
549 | ||
550 | return PCIBIOS_SUCCESSFUL; | |
551 | } | |
552 | ||
553 | static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus, | |
554 | unsigned int devfn, int offset) | |
555 | { | |
8206a110 | 556 | struct pci_controller *hose = pci_bus_to_host(bus); |
598804cd | 557 | struct mpc83xx_pcie_priv *pcie = hose->dn->data; |
f93611fa | 558 | u32 dev_base = bus->number << 24 | devfn << 16; |
598804cd AV |
559 | int ret; |
560 | ||
561 | ret = mpc83xx_pcie_exclude_device(bus, devfn); | |
562 | if (ret) | |
563 | return NULL; | |
564 | ||
565 | offset &= 0xfff; | |
566 | ||
567 | /* Type 0 */ | |
568 | if (bus->number == hose->first_busno) | |
569 | return pcie->cfg_type0 + offset; | |
570 | ||
571 | if (pcie->dev_base == dev_base) | |
572 | goto mapped; | |
573 | ||
574 | out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base); | |
575 | ||
576 | pcie->dev_base = dev_base; | |
577 | mapped: | |
578 | return pcie->cfg_type1 + offset; | |
579 | } | |
580 | ||
581 | static int mpc83xx_pcie_read_config(struct pci_bus *bus, unsigned int devfn, | |
582 | int offset, int len, u32 *val) | |
583 | { | |
584 | void __iomem *cfg_addr; | |
585 | ||
586 | cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset); | |
587 | if (!cfg_addr) | |
588 | return PCIBIOS_DEVICE_NOT_FOUND; | |
589 | ||
590 | switch (len) { | |
591 | case 1: | |
592 | *val = in_8(cfg_addr); | |
593 | break; | |
594 | case 2: | |
595 | *val = in_le16(cfg_addr); | |
596 | break; | |
597 | default: | |
598 | *val = in_le32(cfg_addr); | |
599 | break; | |
600 | } | |
601 | ||
602 | return PCIBIOS_SUCCESSFUL; | |
603 | } | |
604 | ||
605 | static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn, | |
606 | int offset, int len, u32 val) | |
607 | { | |
f93611fa | 608 | struct pci_controller *hose = pci_bus_to_host(bus); |
598804cd AV |
609 | void __iomem *cfg_addr; |
610 | ||
611 | cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset); | |
612 | if (!cfg_addr) | |
613 | return PCIBIOS_DEVICE_NOT_FOUND; | |
614 | ||
f93611fa AV |
615 | /* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */ |
616 | if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno) | |
617 | val &= 0xffffff00; | |
618 | ||
598804cd AV |
619 | switch (len) { |
620 | case 1: | |
621 | out_8(cfg_addr, val); | |
622 | break; | |
623 | case 2: | |
624 | out_le16(cfg_addr, val); | |
625 | break; | |
626 | default: | |
627 | out_le32(cfg_addr, val); | |
628 | break; | |
629 | } | |
630 | ||
631 | return PCIBIOS_SUCCESSFUL; | |
632 | } | |
633 | ||
634 | static struct pci_ops mpc83xx_pcie_ops = { | |
635 | .read = mpc83xx_pcie_read_config, | |
636 | .write = mpc83xx_pcie_write_config, | |
637 | }; | |
638 | ||
639 | static int __init mpc83xx_pcie_setup(struct pci_controller *hose, | |
640 | struct resource *reg) | |
641 | { | |
642 | struct mpc83xx_pcie_priv *pcie; | |
643 | u32 cfg_bar; | |
644 | int ret = -ENOMEM; | |
645 | ||
646 | pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL); | |
647 | if (!pcie) | |
648 | return ret; | |
649 | ||
650 | pcie->cfg_type0 = ioremap(reg->start, resource_size(reg)); | |
651 | if (!pcie->cfg_type0) | |
652 | goto err0; | |
653 | ||
654 | cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR); | |
655 | if (!cfg_bar) { | |
656 | /* PCI-E isn't configured. */ | |
657 | ret = -ENODEV; | |
658 | goto err1; | |
659 | } | |
660 | ||
661 | pcie->cfg_type1 = ioremap(cfg_bar, 0x1000); | |
662 | if (!pcie->cfg_type1) | |
663 | goto err1; | |
664 | ||
665 | WARN_ON(hose->dn->data); | |
666 | hose->dn->data = pcie; | |
667 | hose->ops = &mpc83xx_pcie_ops; | |
668 | ||
669 | out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0); | |
670 | out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0); | |
671 | ||
672 | if (fsl_pcie_check_link(hose)) | |
673 | hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; | |
674 | ||
675 | return 0; | |
676 | err1: | |
677 | iounmap(pcie->cfg_type0); | |
678 | err0: | |
679 | kfree(pcie); | |
680 | return ret; | |
681 | ||
682 | } | |
683 | ||
76fe1ffc JR |
684 | int __init mpc83xx_add_bridge(struct device_node *dev) |
685 | { | |
598804cd | 686 | int ret; |
76fe1ffc JR |
687 | int len; |
688 | struct pci_controller *hose; | |
5b70a097 JR |
689 | struct resource rsrc_reg; |
690 | struct resource rsrc_cfg; | |
76fe1ffc | 691 | const int *bus_range; |
5b70a097 | 692 | int primary; |
76fe1ffc | 693 | |
b8f44ec2 KG |
694 | is_mpc83xx_pci = 1; |
695 | ||
598804cd AV |
696 | if (!of_device_is_available(dev)) { |
697 | pr_warning("%s: disabled by the firmware.\n", | |
698 | dev->full_name); | |
699 | return -ENODEV; | |
700 | } | |
76fe1ffc JR |
701 | pr_debug("Adding PCI host bridge %s\n", dev->full_name); |
702 | ||
703 | /* Fetch host bridge registers address */ | |
5b70a097 JR |
704 | if (of_address_to_resource(dev, 0, &rsrc_reg)) { |
705 | printk(KERN_WARNING "Can't get pci register base!\n"); | |
706 | return -ENOMEM; | |
707 | } | |
708 | ||
709 | memset(&rsrc_cfg, 0, sizeof(rsrc_cfg)); | |
710 | ||
711 | if (of_address_to_resource(dev, 1, &rsrc_cfg)) { | |
712 | printk(KERN_WARNING | |
713 | "No pci config register base in dev tree, " | |
714 | "using default\n"); | |
715 | /* | |
716 | * MPC83xx supports up to two host controllers | |
717 | * one at 0x8500 has config space registers at 0x8300 | |
718 | * one at 0x8600 has config space registers at 0x8380 | |
719 | */ | |
720 | if ((rsrc_reg.start & 0xfffff) == 0x8500) | |
721 | rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300; | |
722 | else if ((rsrc_reg.start & 0xfffff) == 0x8600) | |
723 | rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380; | |
724 | } | |
725 | /* | |
726 | * Controller at offset 0x8500 is primary | |
727 | */ | |
728 | if ((rsrc_reg.start & 0xfffff) == 0x8500) | |
729 | primary = 1; | |
730 | else | |
731 | primary = 0; | |
76fe1ffc JR |
732 | |
733 | /* Get bus range if any */ | |
734 | bus_range = of_get_property(dev, "bus-range", &len); | |
735 | if (bus_range == NULL || len < 2 * sizeof(int)) { | |
736 | printk(KERN_WARNING "Can't get bus-range for %s, assume" | |
737 | " bus 0\n", dev->full_name); | |
738 | } | |
739 | ||
0e47ff1c | 740 | pci_add_flags(PCI_REASSIGN_ALL_BUS); |
76fe1ffc JR |
741 | hose = pcibios_alloc_controller(dev); |
742 | if (!hose) | |
743 | return -ENOMEM; | |
744 | ||
745 | hose->first_busno = bus_range ? bus_range[0] : 0; | |
746 | hose->last_busno = bus_range ? bus_range[1] : 0xff; | |
747 | ||
598804cd AV |
748 | if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) { |
749 | ret = mpc83xx_pcie_setup(hose, &rsrc_reg); | |
750 | if (ret) | |
751 | goto err0; | |
752 | } else { | |
753 | setup_indirect_pci(hose, rsrc_cfg.start, | |
754 | rsrc_cfg.start + 4, 0); | |
755 | } | |
76fe1ffc | 756 | |
35225802 | 757 | printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. " |
76fe1ffc | 758 | "Firmware bus number: %d->%d\n", |
5b70a097 | 759 | (unsigned long long)rsrc_reg.start, hose->first_busno, |
76fe1ffc JR |
760 | hose->last_busno); |
761 | ||
762 | pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", | |
763 | hose, hose->cfg_addr, hose->cfg_data); | |
764 | ||
765 | /* Interpret the "ranges" property */ | |
766 | /* This also maps the I/O region and sets isa_io/mem_base */ | |
767 | pci_process_bridge_OF_ranges(hose, dev, primary); | |
768 | ||
769 | return 0; | |
598804cd AV |
770 | err0: |
771 | pcibios_free_controller(hose); | |
772 | return ret; | |
76fe1ffc JR |
773 | } |
774 | #endif /* CONFIG_PPC_83xx */ | |
b8f44ec2 KG |
775 | |
776 | u64 fsl_pci_immrbar_base(struct pci_controller *hose) | |
777 | { | |
778 | #ifdef CONFIG_PPC_83xx | |
779 | if (is_mpc83xx_pci) { | |
780 | struct mpc83xx_pcie_priv *pcie = hose->dn->data; | |
781 | struct pex_inbound_window *in; | |
782 | int i; | |
783 | ||
784 | /* Walk the Root Complex Inbound windows to match IMMR base */ | |
785 | in = pcie->cfg_type0 + PEX_RC_INWIN_BASE; | |
786 | for (i = 0; i < 4; i++) { | |
787 | /* not enabled, skip */ | |
788 | if (!in_le32(&in[i].ar) & PEX_RCIWARn_EN) | |
789 | continue; | |
790 | ||
791 | if (get_immrbase() == in_le32(&in[i].tar)) | |
792 | return (u64)in_le32(&in[i].barh) << 32 | | |
793 | in_le32(&in[i].barl); | |
794 | } | |
795 | ||
796 | printk(KERN_WARNING "could not find PCI BAR matching IMMR\n"); | |
797 | } | |
798 | #endif | |
799 | ||
800 | #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) | |
801 | if (!is_mpc83xx_pci) { | |
802 | u32 base; | |
803 | ||
804 | pci_bus_read_config_dword(hose->bus, | |
805 | PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base); | |
806 | return base; | |
807 | } | |
808 | #endif | |
809 | ||
810 | return 0; | |
811 | } | |
07e4f801 SW |
812 | |
813 | #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) | |
814 | static const struct of_device_id pci_ids[] = { | |
815 | { .compatible = "fsl,mpc8540-pci", }, | |
816 | { .compatible = "fsl,mpc8548-pcie", }, | |
817 | { .compatible = "fsl,mpc8610-pci", }, | |
818 | { .compatible = "fsl,mpc8641-pcie", }, | |
819 | { .compatible = "fsl,p1022-pcie", }, | |
820 | { .compatible = "fsl,p1010-pcie", }, | |
821 | { .compatible = "fsl,p1023-pcie", }, | |
822 | { .compatible = "fsl,p4080-pcie", }, | |
708998c9 | 823 | { .compatible = "fsl,qoriq-pcie-v2.4", }, |
07e4f801 SW |
824 | { .compatible = "fsl,qoriq-pcie-v2.3", }, |
825 | { .compatible = "fsl,qoriq-pcie-v2.2", }, | |
826 | {}, | |
827 | }; | |
828 | ||
829 | struct device_node *fsl_pci_primary; | |
830 | ||
905e75c4 | 831 | void fsl_pci_assign_primary(void) |
07e4f801 | 832 | { |
905e75c4 | 833 | struct device_node *np; |
07e4f801 SW |
834 | |
835 | /* Callers can specify the primary bus using other means. */ | |
905e75c4 JH |
836 | if (fsl_pci_primary) |
837 | return; | |
838 | ||
839 | /* If a PCI host bridge contains an ISA node, it's primary. */ | |
840 | np = of_find_node_by_type(NULL, "isa"); | |
841 | while ((fsl_pci_primary = of_get_parent(np))) { | |
842 | of_node_put(np); | |
843 | np = fsl_pci_primary; | |
844 | ||
845 | if (of_match_node(pci_ids, np) && of_device_is_available(np)) | |
846 | return; | |
07e4f801 SW |
847 | } |
848 | ||
905e75c4 JH |
849 | /* |
850 | * If there's no PCI host bridge with ISA, arbitrarily | |
851 | * designate one as primary. This can go away once | |
852 | * various bugs with primary-less systems are fixed. | |
853 | */ | |
854 | for_each_matching_node(np, pci_ids) { | |
855 | if (of_device_is_available(np)) { | |
856 | fsl_pci_primary = np; | |
857 | of_node_put(np); | |
858 | return; | |
07e4f801 SW |
859 | } |
860 | } | |
905e75c4 JH |
861 | } |
862 | ||
863 | static int __devinit fsl_pci_probe(struct platform_device *pdev) | |
864 | { | |
865 | int ret; | |
866 | struct device_node *node; | |
4d56dec5 | 867 | #ifdef CONFIG_SWIOTLB |
905e75c4 | 868 | struct pci_controller *hose; |
4d56dec5 | 869 | #endif |
905e75c4 JH |
870 | |
871 | node = pdev->dev.of_node; | |
872 | ret = fsl_add_bridge(node, fsl_pci_primary == node); | |
07e4f801 SW |
873 | |
874 | #ifdef CONFIG_SWIOTLB | |
905e75c4 JH |
875 | if (ret == 0) { |
876 | hose = pci_find_hose_for_OF_device(pdev->dev.of_node); | |
877 | ||
878 | /* | |
879 | * if we couldn't map all of DRAM via the dma windows | |
880 | * we need SWIOTLB to handle buffers located outside of | |
881 | * dma capable memory region | |
882 | */ | |
883 | if (memblock_end_of_DRAM() - 1 > hose->dma_window_base_cur + | |
884 | hose->dma_window_size) | |
885 | ppc_swiotlb_enable = 1; | |
886 | } | |
07e4f801 | 887 | #endif |
905e75c4 JH |
888 | |
889 | mpc85xx_pci_err_probe(pdev); | |
890 | ||
891 | return 0; | |
892 | } | |
893 | ||
894 | static struct platform_driver fsl_pci_driver = { | |
895 | .driver = { | |
896 | .name = "fsl-pci", | |
897 | .of_match_table = pci_ids, | |
898 | }, | |
899 | .probe = fsl_pci_probe, | |
900 | }; | |
901 | ||
902 | static int __init fsl_pci_init(void) | |
903 | { | |
904 | return platform_driver_register(&fsl_pci_driver); | |
07e4f801 | 905 | } |
905e75c4 | 906 | arch_initcall(fsl_pci_init); |
07e4f801 | 907 | #endif |