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powerpc: pci config cleanup
[deliverable/linux.git] / arch / powerpc / sysdev / fsl_pci.c
CommitLineData
b809b3e8 1/*
9ac4dd30 2 * MPC85xx/86xx PCI/PCIE support routing.
b809b3e8 3 *
9ac4dd30 4 * Copyright 2007 Freescale Semiconductor, Inc
b809b3e8 5 *
9ac4dd30
ZR		 6 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
7 * Recode: ZHANG WEI <wei.zhang@freescale.com>
8 * Rewrite the routing for Frescale PCI and PCI Express
9 * Roy Zang <tie-fei.zang@freescale.com>
b809b3e8
JL		 10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
9ac4dd30 16#include <linux/kernel.h>
b809b3e8 17#include <linux/pci.h>
9ac4dd30
ZR		 18#include <linux/delay.h>
19#include <linux/string.h>
20#include <linux/init.h>
21#include <linux/bootmem.h>
b809b3e8 22
b809b3e8
JL		 23#include <asm/io.h>
24#include <asm/prom.h>
b809b3e8 25#include <asm/pci-bridge.h>
9ac4dd30 26#include <asm/machdep.h>
b809b3e8 27#include <sysdev/fsl_soc.h>
55c44991 28#include <sysdev/fsl_pci.h>
b809b3e8 29
9ac4dd30
ZR		 30/* atmu setup for fsl pci/pcie controller */
31void __init setup_pci_atmu(struct pci_controller *hose, struct resource *rsrc)
b809b3e8 32{
9ac4dd30
ZR		 33 struct ccsr_pci __iomem *pci;
34 int i;
b809b3e8 35
72b122cc
KG		 36 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
37 (u64)rsrc->start, (u64)rsrc->end - (u64)rsrc->start + 1);
9ac4dd30
ZR		 38 pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1);
39
40 /* Disable all windows (except powar0 since its ignored) */
41 for(i = 1; i < 5; i++)
42 out_be32(&pci->pow[i].powar, 0);
43 for(i = 0; i < 3; i++)
44 out_be32(&pci->piw[i].piwar, 0);
45
46 /* Setup outbound MEM window */
47 for(i = 0; i < 3; i++)
48 if (hose->mem_resources[i].flags & IORESOURCE_MEM){
72b122cc
KG		 49 resource_size_t pci_addr_start =
50 hose->mem_resources[i].start -
51 hose->pci_mem_offset;
52 pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n",
53 (u64)hose->mem_resources[i].start,
54 (u64)hose->mem_resources[i].end
55 - (u64)hose->mem_resources[i].start + 1);
56 out_be32(&pci->pow[i+1].potar, (pci_addr_start >> 12));
9ac4dd30
ZR		 57 out_be32(&pci->pow[i+1].potear, 0);
58 out_be32(&pci->pow[i+1].powbar,
72b122cc 59 (hose->mem_resources[i].start >> 12));
9ac4dd30
ZR		 60 /* Enable, Mem R/W */
61 out_be32(&pci->pow[i+1].powar, 0x80044000
62 | (__ilog2(hose->mem_resources[i].end
63 - hose->mem_resources[i].start + 1) - 1));
64 }
65
66 /* Setup outbound IO window */
67 if (hose->io_resource.flags & IORESOURCE_IO){
72b122cc
KG		 68 pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "
69 "phy base 0x%016llx.\n",
70 (u64)hose->io_resource.start,
71 (u64)hose->io_resource.end - (u64)hose->io_resource.start + 1,
72 (u64)hose->io_base_phys);
73 out_be32(&pci->pow[i+1].potar, (hose->io_resource.start >> 12));
9ac4dd30 74 out_be32(&pci->pow[i+1].potear, 0);
72b122cc 75 out_be32(&pci->pow[i+1].powbar, (hose->io_base_phys >> 12));
9ac4dd30
ZR		 76 /* Enable, IO R/W */
77 out_be32(&pci->pow[i+1].powar, 0x80088000
78 | (__ilog2(hose->io_resource.end
79 - hose->io_resource.start + 1) - 1));
80 }
81
82 /* Setup 2G inbound Memory Window @ 1 */
83 out_be32(&pci->piw[2].pitar, 0x00000000);
84 out_be32(&pci->piw[2].piwbar,0x00000000);
85 out_be32(&pci->piw[2].piwar, PIWAR_2G);
b809b3e8
JL		 86}
87
9ac4dd30 88void __init setup_pci_cmd(struct pci_controller *hose)
b809b3e8 89{
b809b3e8 90 u16 cmd;
eb12af43
KG		 91 int cap_x;
92
b809b3e8
JL		 93 early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
94 cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
9ac4dd30 95 | PCI_COMMAND_IO;
b809b3e8 96 early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
eb12af43
KG		 97
98 cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX);
99 if (cap_x) {
100 int pci_x_cmd = cap_x + PCI_X_CMD;
101 cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
102 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
103 early_write_config_word(hose, 0, 0, pci_x_cmd, cmd);
104 } else {
105 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
106 }
9ad494f6
KG		 107}
108
692d1037 109static void __init setup_pci_pcsrbar(struct pci_controller *hose)
34e36c15 110{
692d1037 111#ifdef CONFIG_PCI_MSI
34e36c15
JJ		 112 phys_addr_t immr_base;
113
114 immr_base = get_immrbase();
115 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, immr_base);
34e36c15 116#endif
692d1037 117}
34e36c15 118
72b122cc 119static int fsl_pcie_bus_fixup;
20243c72 120
72b122cc
KG		 121static void __init quirk_fsl_pcie_header(struct pci_dev *dev)
122{
957ecffc
KG		 123 /* if we aren't a PCIe don't bother */
124 if (!pci_find_capability(dev, PCI_CAP_ID_EXP))
125 return ;
126
72b122cc
KG		 127 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
128 fsl_pcie_bus_fixup = 1;
129 return ;
20243c72
ZW		 130}
131
9ac4dd30
ZR		 132int __init fsl_pcie_check_link(struct pci_controller *hose)
133{
2fce1225
KG		 134 u32 val;
135 early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
9ac4dd30
ZR		 136 if (val < PCIE_LTSSM_L0)
137 return 1;
138 return 0;
139}
20243c72 140
6c0a11c1
KG		 141void fsl_pcibios_fixup_bus(struct pci_bus *bus)
142{
143 struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
144 int i;
145
72b122cc
KG		 146 if ((bus->parent == hose->bus) &&
147 ((fsl_pcie_bus_fixup &&
148 early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) ||
149 (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)))
150 {
151 for (i = 0; i < 4; ++i) {
152 struct resource *res = bus->resource[i];
153 struct resource *par = bus->parent->resource[i];
154 if (res) {
155 res->start = 0;
156 res->end = 0;
157 res->flags = 0;
158 }
159 if (res && par) {
160 res->start = par->start;
161 res->end = par->end;
162 res->flags = par->flags;
163 }
6c0a11c1
KG		 164 }
165 }
166}
167
9ac4dd30 168int __init fsl_add_bridge(struct device_node *dev, int is_primary)
b809b3e8
JL		 169{
170 int len;
171 struct pci_controller *hose;
172 struct resource rsrc;
8efca493 173 const int *bus_range;
b809b3e8 174
9ac4dd30 175 pr_debug("Adding PCI host bridge %s\n", dev->full_name);
b809b3e8
JL		 176
177 /* Fetch host bridge registers address */
9ac4dd30
ZR		 178 if (of_address_to_resource(dev, 0, &rsrc)) {
179 printk(KERN_WARNING "Can't get pci register base!");
180 return -ENOMEM;
181 }
b809b3e8
JL		 182
183 /* Get bus range if any */
e2eb6392 184 bus_range = of_get_property(dev, "bus-range", &len);
b809b3e8
JL		 185 if (bus_range == NULL || len < 2 * sizeof(int))
186 printk(KERN_WARNING "Can't get bus-range for %s, assume"
9ac4dd30 187 " bus 0\n", dev->full_name);
b809b3e8 188
fc3fb71c 189 ppc_pci_flags |= PPC_PCI_REASSIGN_ALL_BUS;
dbf8471f 190 hose = pcibios_alloc_controller(dev);
b809b3e8
JL		 191 if (!hose)
192 return -ENOMEM;
dbf8471f 193
b809b3e8 194 hose->first_busno = bus_range ? bus_range[0] : 0x0;
bf7c036f 195 hose->last_busno = bus_range ? bus_range[1] : 0xff;
b809b3e8 196
2e56ff20
KG		 197 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
198 PPC_INDIRECT_TYPE_BIG_ENDIAN);
9ac4dd30 199 setup_pci_cmd(hose);
b809b3e8 200
9ac4dd30 201 /* check PCI express link status */
957ecffc 202 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
7659c038 203 hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG |
957ecffc 204 PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
9ac4dd30 205 if (fsl_pcie_check_link(hose))
957ecffc
KG		 206 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
207 }
b809b3e8 208
df3c9019 209 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
9ac4dd30
ZR		 210 "Firmware bus number: %d->%d\n",
211 (unsigned long long)rsrc.start, hose->first_busno,
212 hose->last_busno);
b809b3e8 213
9ac4dd30 214 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
b809b3e8
JL		 215 hose, hose->cfg_addr, hose->cfg_data);
216
217 /* Interpret the "ranges" property */
218 /* This also maps the I/O region and sets isa_io/mem_base */
9ac4dd30 219 pci_process_bridge_OF_ranges(hose, dev, is_primary);
b809b3e8
JL		 220
221 /* Setup PEX window registers */
9ac4dd30 222 setup_pci_atmu(hose, &rsrc);
b809b3e8 223
34e36c15 224 /* Setup PEXCSRBAR */
34e36c15 225 setup_pci_pcsrbar(hose);
b809b3e8
JL		 226 return 0;
227}
9ac4dd30 228
72b122cc
KG		 229DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548E, quirk_fsl_pcie_header);
230DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548, quirk_fsl_pcie_header);
231DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543E, quirk_fsl_pcie_header);
232DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543, quirk_fsl_pcie_header);
233DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8547E, quirk_fsl_pcie_header);
234DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545E, quirk_fsl_pcie_header);
235DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545, quirk_fsl_pcie_header);
236DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568E, quirk_fsl_pcie_header);
237DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568, quirk_fsl_pcie_header);
238DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567E, quirk_fsl_pcie_header);
239DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567, quirk_fsl_pcie_header);
240DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533E, quirk_fsl_pcie_header);
241DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533, quirk_fsl_pcie_header);
242DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544E, quirk_fsl_pcie_header);
243DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544, quirk_fsl_pcie_header);
244DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572E, quirk_fsl_pcie_header);
245DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572, quirk_fsl_pcie_header);
2f3804ed
KG		 246DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536E, quirk_fsl_pcie_header);
247DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536, quirk_fsl_pcie_header);
72b122cc
KG		 248DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_header);
249DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641D, quirk_fsl_pcie_header);
250DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8610, quirk_fsl_pcie_header);
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