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powerpc: fix compile error with 85xx/p1022_ds.c
[deliverable/linux.git] / arch / powerpc / sysdev / fsl_pci.c
CommitLineData
b809b3e8 1/*
5b70a097 2 * MPC83xx/85xx/86xx PCI/PCIE support routing.
b809b3e8 3 *
f4154e16 4 * Copyright 2007-2011 Freescale Semiconductor, Inc.
598804cd 5 * Copyright 2008-2009 MontaVista Software, Inc.
b809b3e8 6 *
9ac4dd30
ZR		 7 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
8 * Recode: ZHANG WEI <wei.zhang@freescale.com>
9 * Rewrite the routing for Frescale PCI and PCI Express
10 * Roy Zang <tie-fei.zang@freescale.com>
598804cd
AV		 11 * MPC83xx PCI-Express support:
12 * Tony Li <tony.li@freescale.com>
13 * Anton Vorontsov <avorontsov@ru.mvista.com>
b809b3e8
JL		 14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 */
9ac4dd30 20#include <linux/kernel.h>
b809b3e8 21#include <linux/pci.h>
9ac4dd30
ZR		 22#include <linux/delay.h>
23#include <linux/string.h>
24#include <linux/init.h>
25#include <linux/bootmem.h>
95f72d1e 26#include <linux/memblock.h>
54c18193 27#include <linux/log2.h>
5a0e3ad6 28#include <linux/slab.h>
b809b3e8 29
b809b3e8
JL		 30#include <asm/io.h>
31#include <asm/prom.h>
b809b3e8 32#include <asm/pci-bridge.h>
9ac4dd30 33#include <asm/machdep.h>
b809b3e8 34#include <sysdev/fsl_soc.h>
55c44991 35#include <sysdev/fsl_pci.h>
b809b3e8 36
b8f44ec2 37static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
598804cd
AV		 38
39static void __init quirk_fsl_pcie_header(struct pci_dev *dev)
40{
470788d4
KG		 41 u8 progif;
42
598804cd
AV		 43 /* if we aren't a PCIe don't bother */
44 if (!pci_find_capability(dev, PCI_CAP_ID_EXP))
45 return;
46
470788d4
KG		 47 /* if we aren't in host mode don't bother */
48 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
49 if (progif & 0x1)
50 return;
51
598804cd
AV		 52 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
53 fsl_pcie_bus_fixup = 1;
54 return;
55}
56
57static int __init fsl_pcie_check_link(struct pci_controller *hose)
58{
59 u32 val;
60
61 early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
62 if (val < PCIE_LTSSM_L0)
63 return 1;
64 return 0;
65}
66
5753c082 67#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
96ea3b4a
KG		 68
69#define MAX_PHYS_ADDR_BITS 40
70static u64 pci64_dma_offset = 1ull << MAX_PHYS_ADDR_BITS;
71
72static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
73{
74 if (!dev->dma_mask || !dma_supported(dev, dma_mask))
75 return -EIO;
76
77 /*
78 * Fixup PCI devices that are able to DMA to above the physical
79 * address width of the SoC such that we can address any internal
80 * SoC address from across PCI if needed
81 */
82 if ((dev->bus == &pci_bus_type) &&
83 dma_mask >= DMA_BIT_MASK(MAX_PHYS_ADDR_BITS)) {
84 set_dma_ops(dev, &dma_direct_ops);
85 set_dma_offset(dev, pci64_dma_offset);
86 }
87
88 *dev->dma_mask = dma_mask;
89 return 0;
90}
91
a097a78c
TP		 92static int __init setup_one_atmu(struct ccsr_pci __iomem *pci,
93 unsigned int index, const struct resource *res,
94 resource_size_t offset)
95{
96 resource_size_t pci_addr = res->start - offset;
97 resource_size_t phys_addr = res->start;
28f65c11 98 resource_size_t size = resource_size(res);
a097a78c
TP		 99 u32 flags = 0x80044000; /* enable & mem R/W */
100 unsigned int i;
101
102 pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n",
103 (u64)res->start, (u64)size);
104
565f3764
TP		 105 if (res->flags & IORESOURCE_PREFETCH)
106 flags |= 0x10000000; /* enable relaxed ordering */
107
a097a78c
TP		 108 for (i = 0; size > 0; i++) {
109 unsigned int bits = min(__ilog2(size),
110 __ffs(pci_addr | phys_addr));
111
112 if (index + i >= 5)
113 return -1;
114
115 out_be32(&pci->pow[index + i].potar, pci_addr >> 12);
116 out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44);
117 out_be32(&pci->pow[index + i].powbar, phys_addr >> 12);
118 out_be32(&pci->pow[index + i].powar, flags | (bits - 1));
119
120 pci_addr += (resource_size_t)1U << bits;
121 phys_addr += (resource_size_t)1U << bits;
122 size -= (resource_size_t)1U << bits;
123 }
124
125 return i;
126}
127
9ac4dd30 128/* atmu setup for fsl pci/pcie controller */
c9dadffb
AV		 129static void __init setup_pci_atmu(struct pci_controller *hose,
130 struct resource *rsrc)
b809b3e8 131{
9ac4dd30 132 struct ccsr_pci __iomem *pci;
f4154e16 133 int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4;
54c18193
KG		 134 u64 mem, sz, paddr_hi = 0;
135 u64 paddr_lo = ULLONG_MAX;
136 u32 pcicsrbar = 0, pcicsrbar_sz;
137 u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL |
138 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
139 char *name = hose->dn->full_name;
446bc1ff
TT		 140 const u64 *reg;
141 int len;
b809b3e8 142
72b122cc 143 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
28f65c11 144 (u64)rsrc->start, (u64)resource_size(rsrc));
f4154e16
PK		 145
146 if (of_device_is_compatible(hose->dn, "fsl,qoriq-pcie-v2.2")) {
147 win_idx = 2;
148 start_idx = 0;
149 end_idx = 3;
150 }
151
28f65c11 152 pci = ioremap(rsrc->start, resource_size(rsrc));
a097a78c
TP		 153 if (!pci) {
154 dev_err(hose->parent, "Unable to map ATMU registers\n");
155 return;
156 }
9ac4dd30 157
a097a78c 158 /* Disable all windows (except powar0 since it's ignored) */
9ac4dd30
ZR		 159 for(i = 1; i < 5; i++)
160 out_be32(&pci->pow[i].powar, 0);
f4154e16 161 for (i = start_idx; i < end_idx; i++)
9ac4dd30
ZR		 162 out_be32(&pci->piw[i].piwar, 0);
163
164 /* Setup outbound MEM window */
a097a78c
TP		 165 for(i = 0, j = 1; i < 3; i++) {
166 if (!(hose->mem_resources[i].flags & IORESOURCE_MEM))
167 continue;
168
54c18193
KG		 169 paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start);
170 paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end);
171
a097a78c
TP		 172 n = setup_one_atmu(pci, j, &hose->mem_resources[i],
173 hose->pci_mem_offset);
174
175 if (n < 0 || j >= 5) {
176 pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i);
177 hose->mem_resources[i].flags |= IORESOURCE_DISABLED;
178 } else
179 j += n;
180 }
9ac4dd30
ZR		 181
182 /* Setup outbound IO window */
a097a78c
TP		 183 if (hose->io_resource.flags & IORESOURCE_IO) {
184 if (j >= 5) {
185 pr_err("Ran out of outbound PCI ATMUs for IO resource\n");
186 } else {
187 pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "
188 "phy base 0x%016llx.\n",
28f65c11
JP		 189 (u64)hose->io_resource.start,
190 (u64)resource_size(&hose->io_resource),
191 (u64)hose->io_base_phys);
a097a78c
TP		 192 out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12));
193 out_be32(&pci->pow[j].potear, 0);
194 out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12));
195 /* Enable, IO R/W */
196 out_be32(&pci->pow[j].powar, 0x80088000
197 | (__ilog2(hose->io_resource.end
198 - hose->io_resource.start + 1) - 1));
199 }
9ac4dd30
ZR		 200 }
201
54c18193
KG		 202 /* convert to pci address space */
203 paddr_hi -= hose->pci_mem_offset;
204 paddr_lo -= hose->pci_mem_offset;
205
206 if (paddr_hi == paddr_lo) {
207 pr_err("%s: No outbound window space\n", name);
208 return ;
209 }
210
211 if (paddr_lo == 0) {
212 pr_err("%s: No space for inbound window\n", name);
213 return ;
214 }
215
216 /* setup PCSRBAR/PEXCSRBAR */
217 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff);
218 early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
219 pcicsrbar_sz = ~pcicsrbar_sz + 1;
220
221 if (paddr_hi < (0x100000000ull - pcicsrbar_sz) ||
222 (paddr_lo > 0x100000000ull))
223 pcicsrbar = 0x100000000ull - pcicsrbar_sz;
224 else
225 pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz;
226 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar);
227
228 paddr_lo = min(paddr_lo, (u64)pcicsrbar);
229
230 pr_info("%s: PCICSRBAR @ 0x%x\n", name, pcicsrbar);
231
232 /* Setup inbound mem window */
95f72d1e 233 mem = memblock_end_of_DRAM();
446bc1ff
TT		 234
235 /*
236 * The msi-address-64 property, if it exists, indicates the physical
237 * address of the MSIIR register. Normally, this register is located
238 * inside CCSR, so the ATMU that covers all of CCSR is used. But if
239 * this property exists, then we normally need to create a new ATMU
240 * for it. For now, however, we cheat. The only entity that creates
241 * this property is the Freescale hypervisor, and the address is
242 * specified in the partition configuration. Typically, the address
243 * is located in the page immediately after the end of DDR. If so, we
244 * can avoid allocating a new ATMU by extending the DDR ATMU by one
245 * page.
246 */
247 reg = of_get_property(hose->dn, "msi-address-64", &len);
248 if (reg && (len == sizeof(u64))) {
249 u64 address = be64_to_cpup(reg);
250
251 if ((address >= mem) && (address < (mem + PAGE_SIZE))) {
252 pr_info("%s: extending DDR ATMU to cover MSIIR", name);
253 mem += PAGE_SIZE;
254 } else {
255 /* TODO: Create a new ATMU for MSIIR */
256 pr_warn("%s: msi-address-64 address of %llx is "
257 "unsupported\n", name, address);
258 }
259 }
260
54c18193
KG		 261 sz = min(mem, paddr_lo);
262 mem_log = __ilog2_u64(sz);
263
264 /* PCIe can overmap inbound & outbound since RX & TX are separated */
265 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
266 /* Size window to exact size if power-of-two or one size up */
267 if ((1ull << mem_log) != mem) {
268 if ((1ull << mem_log) > mem)
269 pr_info("%s: Setting PCI inbound window "
270 "greater than memory size\n", name);
271 mem_log++;
272 }
273
f4154e16 274 piwar |= ((mem_log - 1) & PIWAR_SZ_MASK);
54c18193
KG		 275
276 /* Setup inbound memory window */
277 out_be32(&pci->piw[win_idx].pitar, 0x00000000);
278 out_be32(&pci->piw[win_idx].piwbar, 0x00000000);
279 out_be32(&pci->piw[win_idx].piwar, piwar);
280 win_idx--;
281
282 hose->dma_window_base_cur = 0x00000000;
283 hose->dma_window_size = (resource_size_t)sz;
96ea3b4a
KG		 284
285 /*
286 * if we have >4G of memory setup second PCI inbound window to
287 * let devices that are 64-bit address capable to work w/o
288 * SWIOTLB and access the full range of memory
289 */
290 if (sz != mem) {
291 mem_log = __ilog2_u64(mem);
292
293 /* Size window up if we dont fit in exact power-of-2 */
294 if ((1ull << mem_log) != mem)
295 mem_log++;
296
297 piwar = (piwar & ~PIWAR_SZ_MASK) | (mem_log - 1);
298
299 /* Setup inbound memory window */
300 out_be32(&pci->piw[win_idx].pitar, 0x00000000);
301 out_be32(&pci->piw[win_idx].piwbear,
302 pci64_dma_offset >> 44);
303 out_be32(&pci->piw[win_idx].piwbar,
304 pci64_dma_offset >> 12);
305 out_be32(&pci->piw[win_idx].piwar, piwar);
306
307 /*
308 * install our own dma_set_mask handler to fixup dma_ops
309 * and dma_offset
310 */
311 ppc_md.dma_set_mask = fsl_pci_dma_set_mask;
312
313 pr_info("%s: Setup 64-bit PCI DMA window\n", name);
314 }
54c18193
KG		 315 } else {
316 u64 paddr = 0;
317
318 /* Setup inbound memory window */
319 out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
320 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
321 out_be32(&pci->piw[win_idx].piwar, (piwar | (mem_log - 1)));
322 win_idx--;
323
324 paddr += 1ull << mem_log;
325 sz -= 1ull << mem_log;
326
327 if (sz) {
328 mem_log = __ilog2_u64(sz);
329 piwar |= (mem_log - 1);
330
331 out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
332 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
333 out_be32(&pci->piw[win_idx].piwar, piwar);
334 win_idx--;
335
336 paddr += 1ull << mem_log;
337 }
338
339 hose->dma_window_base_cur = 0x00000000;
340 hose->dma_window_size = (resource_size_t)paddr;
341 }
a097a78c 342
54c18193
KG		 343 if (hose->dma_window_size < mem) {
344#ifndef CONFIG_SWIOTLB
345 pr_err("%s: ERROR: Memory size exceeds PCI ATMU ability to "
346 "map - enable CONFIG_SWIOTLB to avoid dma errors.\n",
347 name);
348#endif
349 /* adjusting outbound windows could reclaim space in mem map */
350 if (paddr_hi < 0xffffffffull)
351 pr_warning("%s: WARNING: Outbound window cfg leaves "
352 "gaps in memory map. Adjusting the memory map "
353 "could reduce unnecessary bounce buffering.\n",
354 name);
355
356 pr_info("%s: DMA window size is 0x%llx\n", name,
357 (u64)hose->dma_window_size);
358 }
89d93347 359
a097a78c 360 iounmap(pci);
b809b3e8
JL		 361}
362
c9dadffb 363static void __init setup_pci_cmd(struct pci_controller *hose)
b809b3e8 364{
b809b3e8 365 u16 cmd;
eb12af43
KG		 366 int cap_x;
367
b809b3e8
JL		 368 early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
369 cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
9ac4dd30 370 | PCI_COMMAND_IO;
b809b3e8 371 early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
eb12af43
KG		 372
373 cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX);
374 if (cap_x) {
375 int pci_x_cmd = cap_x + PCI_X_CMD;
376 cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
377 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
378 early_write_config_word(hose, 0, 0, pci_x_cmd, cmd);
379 } else {
380 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
381 }
9ad494f6
KG		 382}
383
6c0a11c1
KG		 384void fsl_pcibios_fixup_bus(struct pci_bus *bus)
385{
8206a110 386 struct pci_controller *hose = pci_bus_to_host(bus);
6c0a11c1
KG		 387 int i;
388
72b122cc
KG		 389 if ((bus->parent == hose->bus) &&
390 ((fsl_pcie_bus_fixup &&
391 early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) ||
392 (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)))
393 {
394 for (i = 0; i < 4; ++i) {
395 struct resource *res = bus->resource[i];
396 struct resource *par = bus->parent->resource[i];
397 if (res) {
398 res->start = 0;
399 res->end = 0;
400 res->flags = 0;
401 }
402 if (res && par) {
403 res->start = par->start;
404 res->end = par->end;
405 res->flags = par->flags;
406 }
6c0a11c1
KG		 407 }
408 }
409}
410
9ac4dd30 411int __init fsl_add_bridge(struct device_node *dev, int is_primary)
b809b3e8
JL		 412{
413 int len;
414 struct pci_controller *hose;
415 struct resource rsrc;
8efca493 416 const int *bus_range;
08871c09 417 u8 progif;
b809b3e8 418
ef1fd2df
PK		 419 if (!of_device_is_available(dev)) {
420 pr_warning("%s: disabled\n", dev->full_name);
421 return -ENODEV;
422 }
423
9ac4dd30 424 pr_debug("Adding PCI host bridge %s\n", dev->full_name);
b809b3e8
JL		 425
426 /* Fetch host bridge registers address */
9ac4dd30
ZR		 427 if (of_address_to_resource(dev, 0, &rsrc)) {
428 printk(KERN_WARNING "Can't get pci register base!");
429 return -ENOMEM;
430 }
b809b3e8
JL		 431
432 /* Get bus range if any */
e2eb6392 433 bus_range = of_get_property(dev, "bus-range", &len);
b809b3e8
JL		 434 if (bus_range == NULL || len < 2 * sizeof(int))
435 printk(KERN_WARNING "Can't get bus-range for %s, assume"
9ac4dd30 436 " bus 0\n", dev->full_name);
b809b3e8 437
0e47ff1c 438 pci_add_flags(PCI_REASSIGN_ALL_BUS);
dbf8471f 439 hose = pcibios_alloc_controller(dev);
b809b3e8
JL		 440 if (!hose)
441 return -ENOMEM;
dbf8471f 442
b809b3e8 443 hose->first_busno = bus_range ? bus_range[0] : 0x0;
bf7c036f 444 hose->last_busno = bus_range ? bus_range[1] : 0xff;
b809b3e8 445
2e56ff20
KG		 446 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
447 PPC_INDIRECT_TYPE_BIG_ENDIAN);
08871c09
PK		 448
449 early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif);
450 if ((progif & 1) == 1) {
451 /* unmap cfg_data & cfg_addr separately if not on same page */
452 if (((unsigned long)hose->cfg_data & PAGE_MASK) !=
453 ((unsigned long)hose->cfg_addr & PAGE_MASK))
454 iounmap(hose->cfg_data);
455 iounmap(hose->cfg_addr);
456 pcibios_free_controller(hose);
457 return 0;
458 }
459
9ac4dd30 460 setup_pci_cmd(hose);
b809b3e8 461
9ac4dd30 462 /* check PCI express link status */
957ecffc 463 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
7659c038 464 hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG |
957ecffc 465 PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
9ac4dd30 466 if (fsl_pcie_check_link(hose))
957ecffc
KG		 467 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
468 }
b809b3e8 469
df3c9019 470 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
9ac4dd30
ZR		 471 "Firmware bus number: %d->%d\n",
472 (unsigned long long)rsrc.start, hose->first_busno,
473 hose->last_busno);
b809b3e8 474
9ac4dd30 475 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
b809b3e8
JL		 476 hose, hose->cfg_addr, hose->cfg_data);
477
478 /* Interpret the "ranges" property */
479 /* This also maps the I/O region and sets isa_io/mem_base */
9ac4dd30 480 pci_process_bridge_OF_ranges(hose, dev, is_primary);
b809b3e8
JL		 481
482 /* Setup PEX window registers */
9ac4dd30 483 setup_pci_atmu(hose, &rsrc);
b809b3e8
JL		 484
485 return 0;
486}
5753c082 487#endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
76fe1ffc 488
470788d4 489DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_pcie_header);
598804cd 490
470788d4 491#if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
598804cd
AV		 492struct mpc83xx_pcie_priv {
493 void __iomem *cfg_type0;
494 void __iomem *cfg_type1;
495 u32 dev_base;
496};
497
b8f44ec2
KG		 498struct pex_inbound_window {
499 u32 ar;
500 u32 tar;
501 u32 barl;
502 u32 barh;
503};
504
598804cd
AV		 505/*
506 * With the convention of u-boot, the PCIE outbound window 0 serves
507 * as configuration transactions outbound.
508 */
509#define PEX_OUTWIN0_BAR 0xCA4
510#define PEX_OUTWIN0_TAL 0xCA8
511#define PEX_OUTWIN0_TAH 0xCAC
b8f44ec2
KG		 512#define PEX_RC_INWIN_BASE 0xE60
513#define PEX_RCIWARn_EN 0x1
598804cd
AV		 514
515static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn)
516{
8206a110 517 struct pci_controller *hose = pci_bus_to_host(bus);
598804cd
AV		 518
519 if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)
520 return PCIBIOS_DEVICE_NOT_FOUND;
521 /*
522 * Workaround for the HW bug: for Type 0 configure transactions the
523 * PCI-E controller does not check the device number bits and just
524 * assumes that the device number bits are 0.
525 */
526 if (bus->number == hose->first_busno ||
527 bus->primary == hose->first_busno) {
528 if (devfn & 0xf8)
529 return PCIBIOS_DEVICE_NOT_FOUND;
530 }
531
532 if (ppc_md.pci_exclude_device) {
533 if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
534 return PCIBIOS_DEVICE_NOT_FOUND;
535 }
536
537 return PCIBIOS_SUCCESSFUL;
538}
539
540static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus,
541 unsigned int devfn, int offset)
542{
8206a110 543 struct pci_controller *hose = pci_bus_to_host(bus);
598804cd 544 struct mpc83xx_pcie_priv *pcie = hose->dn->data;
f93611fa 545 u32 dev_base = bus->number << 24 | devfn << 16;
598804cd
AV		 546 int ret;
547
548 ret = mpc83xx_pcie_exclude_device(bus, devfn);
549 if (ret)
550 return NULL;
551
552 offset &= 0xfff;
553
554 /* Type 0 */
555 if (bus->number == hose->first_busno)
556 return pcie->cfg_type0 + offset;
557
558 if (pcie->dev_base == dev_base)
559 goto mapped;
560
561 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base);
562
563 pcie->dev_base = dev_base;
564mapped:
565 return pcie->cfg_type1 + offset;
566}
567
568static int mpc83xx_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
569 int offset, int len, u32 *val)
570{
571 void __iomem *cfg_addr;
572
573 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
574 if (!cfg_addr)
575 return PCIBIOS_DEVICE_NOT_FOUND;
576
577 switch (len) {
578 case 1:
579 *val = in_8(cfg_addr);
580 break;
581 case 2:
582 *val = in_le16(cfg_addr);
583 break;
584 default:
585 *val = in_le32(cfg_addr);
586 break;
587 }
588
589 return PCIBIOS_SUCCESSFUL;
590}
591
592static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
593 int offset, int len, u32 val)
594{
f93611fa 595 struct pci_controller *hose = pci_bus_to_host(bus);
598804cd
AV		 596 void __iomem *cfg_addr;
597
598 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
599 if (!cfg_addr)
600 return PCIBIOS_DEVICE_NOT_FOUND;
601
f93611fa
AV		 602 /* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */
603 if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno)
604 val &= 0xffffff00;
605
598804cd
AV		 606 switch (len) {
607 case 1:
608 out_8(cfg_addr, val);
609 break;
610 case 2:
611 out_le16(cfg_addr, val);
612 break;
613 default:
614 out_le32(cfg_addr, val);
615 break;
616 }
617
618 return PCIBIOS_SUCCESSFUL;
619}
620
621static struct pci_ops mpc83xx_pcie_ops = {
622 .read = mpc83xx_pcie_read_config,
623 .write = mpc83xx_pcie_write_config,
624};
625
626static int __init mpc83xx_pcie_setup(struct pci_controller *hose,
627 struct resource *reg)
628{
629 struct mpc83xx_pcie_priv *pcie;
630 u32 cfg_bar;
631 int ret = -ENOMEM;
632
633 pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL);
634 if (!pcie)
635 return ret;
636
637 pcie->cfg_type0 = ioremap(reg->start, resource_size(reg));
638 if (!pcie->cfg_type0)
639 goto err0;
640
641 cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR);
642 if (!cfg_bar) {
643 /* PCI-E isn't configured. */
644 ret = -ENODEV;
645 goto err1;
646 }
647
648 pcie->cfg_type1 = ioremap(cfg_bar, 0x1000);
649 if (!pcie->cfg_type1)
650 goto err1;
651
652 WARN_ON(hose->dn->data);
653 hose->dn->data = pcie;
654 hose->ops = &mpc83xx_pcie_ops;
655
656 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0);
657 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0);
658
659 if (fsl_pcie_check_link(hose))
660 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
661
662 return 0;
663err1:
664 iounmap(pcie->cfg_type0);
665err0:
666 kfree(pcie);
667 return ret;
668
669}
670
76fe1ffc
JR		 671int __init mpc83xx_add_bridge(struct device_node *dev)
672{
598804cd 673 int ret;
76fe1ffc
JR		 674 int len;
675 struct pci_controller *hose;
5b70a097
JR		 676 struct resource rsrc_reg;
677 struct resource rsrc_cfg;
76fe1ffc 678 const int *bus_range;
5b70a097 679 int primary;
76fe1ffc 680
b8f44ec2
KG		 681 is_mpc83xx_pci = 1;
682
598804cd
AV		 683 if (!of_device_is_available(dev)) {
684 pr_warning("%s: disabled by the firmware.\n",
685 dev->full_name);
686 return -ENODEV;
687 }
76fe1ffc
JR		 688 pr_debug("Adding PCI host bridge %s\n", dev->full_name);
689
690 /* Fetch host bridge registers address */
5b70a097
JR		 691 if (of_address_to_resource(dev, 0, &rsrc_reg)) {
692 printk(KERN_WARNING "Can't get pci register base!\n");
693 return -ENOMEM;
694 }
695
696 memset(&rsrc_cfg, 0, sizeof(rsrc_cfg));
697
698 if (of_address_to_resource(dev, 1, &rsrc_cfg)) {
699 printk(KERN_WARNING
700 "No pci config register base in dev tree, "
701 "using default\n");
702 /*
703 * MPC83xx supports up to two host controllers
704 * one at 0x8500 has config space registers at 0x8300
705 * one at 0x8600 has config space registers at 0x8380
706 */
707 if ((rsrc_reg.start & 0xfffff) == 0x8500)
708 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300;
709 else if ((rsrc_reg.start & 0xfffff) == 0x8600)
710 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380;
711 }
712 /*
713 * Controller at offset 0x8500 is primary
714 */
715 if ((rsrc_reg.start & 0xfffff) == 0x8500)
716 primary = 1;
717 else
718 primary = 0;
76fe1ffc
JR		 719
720 /* Get bus range if any */
721 bus_range = of_get_property(dev, "bus-range", &len);
722 if (bus_range == NULL || len < 2 * sizeof(int)) {
723 printk(KERN_WARNING "Can't get bus-range for %s, assume"
724 " bus 0\n", dev->full_name);
725 }
726
0e47ff1c 727 pci_add_flags(PCI_REASSIGN_ALL_BUS);
76fe1ffc
JR		 728 hose = pcibios_alloc_controller(dev);
729 if (!hose)
730 return -ENOMEM;
731
732 hose->first_busno = bus_range ? bus_range[0] : 0;
733 hose->last_busno = bus_range ? bus_range[1] : 0xff;
734
598804cd
AV		 735 if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) {
736 ret = mpc83xx_pcie_setup(hose, &rsrc_reg);
737 if (ret)
738 goto err0;
739 } else {
740 setup_indirect_pci(hose, rsrc_cfg.start,
741 rsrc_cfg.start + 4, 0);
742 }
76fe1ffc 743
35225802 744 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
76fe1ffc 745 "Firmware bus number: %d->%d\n",
5b70a097 746 (unsigned long long)rsrc_reg.start, hose->first_busno,
76fe1ffc
JR		 747 hose->last_busno);
748
749 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
750 hose, hose->cfg_addr, hose->cfg_data);
751
752 /* Interpret the "ranges" property */
753 /* This also maps the I/O region and sets isa_io/mem_base */
754 pci_process_bridge_OF_ranges(hose, dev, primary);
755
756 return 0;
598804cd
AV		 757err0:
758 pcibios_free_controller(hose);
759 return ret;
76fe1ffc
JR		 760}
761#endif /* CONFIG_PPC_83xx */
b8f44ec2
KG		 762
763u64 fsl_pci_immrbar_base(struct pci_controller *hose)
764{
765#ifdef CONFIG_PPC_83xx
766 if (is_mpc83xx_pci) {
767 struct mpc83xx_pcie_priv *pcie = hose->dn->data;
768 struct pex_inbound_window *in;
769 int i;
770
771 /* Walk the Root Complex Inbound windows to match IMMR base */
772 in = pcie->cfg_type0 + PEX_RC_INWIN_BASE;
773 for (i = 0; i < 4; i++) {
774 /* not enabled, skip */
775 if (!in_le32(&in[i].ar) & PEX_RCIWARn_EN)
776 continue;
777
778 if (get_immrbase() == in_le32(&in[i].tar))
779 return (u64)in_le32(&in[i].barh) << 32 |
780 in_le32(&in[i].barl);
781 }
782
783 printk(KERN_WARNING "could not find PCI BAR matching IMMR\n");
784 }
785#endif
786
787#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
788 if (!is_mpc83xx_pci) {
789 u32 base;
790
791 pci_bus_read_config_dword(hose->bus,
792 PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base);
793 return base;
794 }
795#endif
796
797 return 0;
798}
Linux kernel - Deliverables
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