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arch/powerpc/sysdev/fsl_rmu.c: introduce missing kfree
[deliverable/linux.git] / arch / powerpc / sysdev / fsl_pci.c
CommitLineData
b809b3e8 1/*
5b70a097 2 * MPC83xx/85xx/86xx PCI/PCIE support routing.
b809b3e8 3 *
f4154e16 4 * Copyright 2007-2011 Freescale Semiconductor, Inc.
598804cd 5 * Copyright 2008-2009 MontaVista Software, Inc.
b809b3e8 6 *
9ac4dd30
ZR		 7 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
8 * Recode: ZHANG WEI <wei.zhang@freescale.com>
9 * Rewrite the routing for Frescale PCI and PCI Express
10 * Roy Zang <tie-fei.zang@freescale.com>
598804cd
AV		 11 * MPC83xx PCI-Express support:
12 * Tony Li <tony.li@freescale.com>
13 * Anton Vorontsov <avorontsov@ru.mvista.com>
b809b3e8
JL		 14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 */
9ac4dd30 20#include <linux/kernel.h>
b809b3e8 21#include <linux/pci.h>
9ac4dd30
ZR		 22#include <linux/delay.h>
23#include <linux/string.h>
24#include <linux/init.h>
25#include <linux/bootmem.h>
95f72d1e 26#include <linux/memblock.h>
54c18193 27#include <linux/log2.h>
5a0e3ad6 28#include <linux/slab.h>
b809b3e8 29
b809b3e8
JL		 30#include <asm/io.h>
31#include <asm/prom.h>
b809b3e8 32#include <asm/pci-bridge.h>
9ac4dd30 33#include <asm/machdep.h>
b809b3e8 34#include <sysdev/fsl_soc.h>
55c44991 35#include <sysdev/fsl_pci.h>
b809b3e8 36
b8f44ec2 37static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
598804cd
AV		 38
39static void __init quirk_fsl_pcie_header(struct pci_dev *dev)
40{
470788d4
KG		 41 u8 progif;
42
598804cd
AV		 43 /* if we aren't a PCIe don't bother */
44 if (!pci_find_capability(dev, PCI_CAP_ID_EXP))
45 return;
46
470788d4
KG		 47 /* if we aren't in host mode don't bother */
48 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
49 if (progif & 0x1)
50 return;
51
598804cd
AV		 52 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
53 fsl_pcie_bus_fixup = 1;
54 return;
55}
56
57static int __init fsl_pcie_check_link(struct pci_controller *hose)
58{
59 u32 val;
60
61 early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
62 if (val < PCIE_LTSSM_L0)
63 return 1;
64 return 0;
65}
66
5753c082 67#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
96ea3b4a
KG		 68
69#define MAX_PHYS_ADDR_BITS 40
70static u64 pci64_dma_offset = 1ull << MAX_PHYS_ADDR_BITS;
71
72static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
73{
74 if (!dev->dma_mask || !dma_supported(dev, dma_mask))
75 return -EIO;
76
77 /*
78 * Fixup PCI devices that are able to DMA to above the physical
79 * address width of the SoC such that we can address any internal
80 * SoC address from across PCI if needed
81 */
82 if ((dev->bus == &pci_bus_type) &&
83 dma_mask >= DMA_BIT_MASK(MAX_PHYS_ADDR_BITS)) {
84 set_dma_ops(dev, &dma_direct_ops);
85 set_dma_offset(dev, pci64_dma_offset);
86 }
87
88 *dev->dma_mask = dma_mask;
89 return 0;
90}
91
a097a78c
TP		 92static int __init setup_one_atmu(struct ccsr_pci __iomem *pci,
93 unsigned int index, const struct resource *res,
94 resource_size_t offset)
95{
96 resource_size_t pci_addr = res->start - offset;
97 resource_size_t phys_addr = res->start;
28f65c11 98 resource_size_t size = resource_size(res);
a097a78c
TP		 99 u32 flags = 0x80044000; /* enable & mem R/W */
100 unsigned int i;
101
102 pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n",
103 (u64)res->start, (u64)size);
104
565f3764
TP		 105 if (res->flags & IORESOURCE_PREFETCH)
106 flags |= 0x10000000; /* enable relaxed ordering */
107
a097a78c
TP		 108 for (i = 0; size > 0; i++) {
109 unsigned int bits = min(__ilog2(size),
110 __ffs(pci_addr | phys_addr));
111
112 if (index + i >= 5)
113 return -1;
114
115 out_be32(&pci->pow[index + i].potar, pci_addr >> 12);
116 out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44);
117 out_be32(&pci->pow[index + i].powbar, phys_addr >> 12);
118 out_be32(&pci->pow[index + i].powar, flags | (bits - 1));
119
120 pci_addr += (resource_size_t)1U << bits;
121 phys_addr += (resource_size_t)1U << bits;
122 size -= (resource_size_t)1U << bits;
123 }
124
125 return i;
126}
127
9ac4dd30 128/* atmu setup for fsl pci/pcie controller */
c9dadffb
AV		 129static void __init setup_pci_atmu(struct pci_controller *hose,
130 struct resource *rsrc)
b809b3e8 131{
9ac4dd30 132 struct ccsr_pci __iomem *pci;
f4154e16 133 int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4;
54c18193
KG		 134 u64 mem, sz, paddr_hi = 0;
135 u64 paddr_lo = ULLONG_MAX;
136 u32 pcicsrbar = 0, pcicsrbar_sz;
137 u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL |
138 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
139 char *name = hose->dn->full_name;
b809b3e8 140
72b122cc 141 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
28f65c11 142 (u64)rsrc->start, (u64)resource_size(rsrc));
f4154e16
PK		 143
144 if (of_device_is_compatible(hose->dn, "fsl,qoriq-pcie-v2.2")) {
145 win_idx = 2;
146 start_idx = 0;
147 end_idx = 3;
148 }
149
28f65c11 150 pci = ioremap(rsrc->start, resource_size(rsrc));
a097a78c
TP		 151 if (!pci) {
152 dev_err(hose->parent, "Unable to map ATMU registers\n");
153 return;
154 }
9ac4dd30 155
a097a78c 156 /* Disable all windows (except powar0 since it's ignored) */
9ac4dd30
ZR		 157 for(i = 1; i < 5; i++)
158 out_be32(&pci->pow[i].powar, 0);
f4154e16 159 for (i = start_idx; i < end_idx; i++)
9ac4dd30
ZR		 160 out_be32(&pci->piw[i].piwar, 0);
161
162 /* Setup outbound MEM window */
a097a78c
TP		 163 for(i = 0, j = 1; i < 3; i++) {
164 if (!(hose->mem_resources[i].flags & IORESOURCE_MEM))
165 continue;
166
54c18193
KG		 167 paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start);
168 paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end);
169
a097a78c
TP		 170 n = setup_one_atmu(pci, j, &hose->mem_resources[i],
171 hose->pci_mem_offset);
172
173 if (n < 0 || j >= 5) {
174 pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i);
175 hose->mem_resources[i].flags |= IORESOURCE_DISABLED;
176 } else
177 j += n;
178 }
9ac4dd30
ZR		 179
180 /* Setup outbound IO window */
a097a78c
TP		 181 if (hose->io_resource.flags & IORESOURCE_IO) {
182 if (j >= 5) {
183 pr_err("Ran out of outbound PCI ATMUs for IO resource\n");
184 } else {
185 pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "
186 "phy base 0x%016llx.\n",
28f65c11
JP		 187 (u64)hose->io_resource.start,
188 (u64)resource_size(&hose->io_resource),
189 (u64)hose->io_base_phys);
a097a78c
TP		 190 out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12));
191 out_be32(&pci->pow[j].potear, 0);
192 out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12));
193 /* Enable, IO R/W */
194 out_be32(&pci->pow[j].powar, 0x80088000
195 | (__ilog2(hose->io_resource.end
196 - hose->io_resource.start + 1) - 1));
197 }
9ac4dd30
ZR		 198 }
199
54c18193
KG		 200 /* convert to pci address space */
201 paddr_hi -= hose->pci_mem_offset;
202 paddr_lo -= hose->pci_mem_offset;
203
204 if (paddr_hi == paddr_lo) {
205 pr_err("%s: No outbound window space\n", name);
206 return ;
207 }
208
209 if (paddr_lo == 0) {
210 pr_err("%s: No space for inbound window\n", name);
211 return ;
212 }
213
214 /* setup PCSRBAR/PEXCSRBAR */
215 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff);
216 early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
217 pcicsrbar_sz = ~pcicsrbar_sz + 1;
218
219 if (paddr_hi < (0x100000000ull - pcicsrbar_sz) ||
220 (paddr_lo > 0x100000000ull))
221 pcicsrbar = 0x100000000ull - pcicsrbar_sz;
222 else
223 pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz;
224 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar);
225
226 paddr_lo = min(paddr_lo, (u64)pcicsrbar);
227
228 pr_info("%s: PCICSRBAR @ 0x%x\n", name, pcicsrbar);
229
230 /* Setup inbound mem window */
95f72d1e 231 mem = memblock_end_of_DRAM();
54c18193
KG		 232 sz = min(mem, paddr_lo);
233 mem_log = __ilog2_u64(sz);
234
235 /* PCIe can overmap inbound & outbound since RX & TX are separated */
236 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
237 /* Size window to exact size if power-of-two or one size up */
238 if ((1ull << mem_log) != mem) {
239 if ((1ull << mem_log) > mem)
240 pr_info("%s: Setting PCI inbound window "
241 "greater than memory size\n", name);
242 mem_log++;
243 }
244
f4154e16 245 piwar |= ((mem_log - 1) & PIWAR_SZ_MASK);
54c18193
KG		 246
247 /* Setup inbound memory window */
248 out_be32(&pci->piw[win_idx].pitar, 0x00000000);
249 out_be32(&pci->piw[win_idx].piwbar, 0x00000000);
250 out_be32(&pci->piw[win_idx].piwar, piwar);
251 win_idx--;
252
253 hose->dma_window_base_cur = 0x00000000;
254 hose->dma_window_size = (resource_size_t)sz;
96ea3b4a
KG		 255
256 /*
257 * if we have >4G of memory setup second PCI inbound window to
258 * let devices that are 64-bit address capable to work w/o
259 * SWIOTLB and access the full range of memory
260 */
261 if (sz != mem) {
262 mem_log = __ilog2_u64(mem);
263
264 /* Size window up if we dont fit in exact power-of-2 */
265 if ((1ull << mem_log) != mem)
266 mem_log++;
267
268 piwar = (piwar & ~PIWAR_SZ_MASK) | (mem_log - 1);
269
270 /* Setup inbound memory window */
271 out_be32(&pci->piw[win_idx].pitar, 0x00000000);
272 out_be32(&pci->piw[win_idx].piwbear,
273 pci64_dma_offset >> 44);
274 out_be32(&pci->piw[win_idx].piwbar,
275 pci64_dma_offset >> 12);
276 out_be32(&pci->piw[win_idx].piwar, piwar);
277
278 /*
279 * install our own dma_set_mask handler to fixup dma_ops
280 * and dma_offset
281 */
282 ppc_md.dma_set_mask = fsl_pci_dma_set_mask;
283
284 pr_info("%s: Setup 64-bit PCI DMA window\n", name);
285 }
54c18193
KG		 286 } else {
287 u64 paddr = 0;
288
289 /* Setup inbound memory window */
290 out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
291 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
292 out_be32(&pci->piw[win_idx].piwar, (piwar | (mem_log - 1)));
293 win_idx--;
294
295 paddr += 1ull << mem_log;
296 sz -= 1ull << mem_log;
297
298 if (sz) {
299 mem_log = __ilog2_u64(sz);
300 piwar |= (mem_log - 1);
301
302 out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
303 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
304 out_be32(&pci->piw[win_idx].piwar, piwar);
305 win_idx--;
306
307 paddr += 1ull << mem_log;
308 }
309
310 hose->dma_window_base_cur = 0x00000000;
311 hose->dma_window_size = (resource_size_t)paddr;
312 }
a097a78c 313
54c18193
KG		 314 if (hose->dma_window_size < mem) {
315#ifndef CONFIG_SWIOTLB
316 pr_err("%s: ERROR: Memory size exceeds PCI ATMU ability to "
317 "map - enable CONFIG_SWIOTLB to avoid dma errors.\n",
318 name);
319#endif
320 /* adjusting outbound windows could reclaim space in mem map */
321 if (paddr_hi < 0xffffffffull)
322 pr_warning("%s: WARNING: Outbound window cfg leaves "
323 "gaps in memory map. Adjusting the memory map "
324 "could reduce unnecessary bounce buffering.\n",
325 name);
326
327 pr_info("%s: DMA window size is 0x%llx\n", name,
328 (u64)hose->dma_window_size);
329 }
89d93347 330
a097a78c 331 iounmap(pci);
b809b3e8
JL		 332}
333
c9dadffb 334static void __init setup_pci_cmd(struct pci_controller *hose)
b809b3e8 335{
b809b3e8 336 u16 cmd;
eb12af43
KG		 337 int cap_x;
338
b809b3e8
JL		 339 early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
340 cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
9ac4dd30 341 | PCI_COMMAND_IO;
b809b3e8 342 early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
eb12af43
KG		 343
344 cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX);
345 if (cap_x) {
346 int pci_x_cmd = cap_x + PCI_X_CMD;
347 cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
348 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
349 early_write_config_word(hose, 0, 0, pci_x_cmd, cmd);
350 } else {
351 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
352 }
9ad494f6
KG		 353}
354
6c0a11c1
KG		 355void fsl_pcibios_fixup_bus(struct pci_bus *bus)
356{
8206a110 357 struct pci_controller *hose = pci_bus_to_host(bus);
6c0a11c1
KG		 358 int i;
359
72b122cc
KG		 360 if ((bus->parent == hose->bus) &&
361 ((fsl_pcie_bus_fixup &&
362 early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) ||
363 (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)))
364 {
365 for (i = 0; i < 4; ++i) {
366 struct resource *res = bus->resource[i];
367 struct resource *par = bus->parent->resource[i];
368 if (res) {
369 res->start = 0;
370 res->end = 0;
371 res->flags = 0;
372 }
373 if (res && par) {
374 res->start = par->start;
375 res->end = par->end;
376 res->flags = par->flags;
377 }
6c0a11c1
KG		 378 }
379 }
380}
381
9ac4dd30 382int __init fsl_add_bridge(struct device_node *dev, int is_primary)
b809b3e8
JL		 383{
384 int len;
385 struct pci_controller *hose;
386 struct resource rsrc;
8efca493 387 const int *bus_range;
08871c09 388 u8 progif;
b809b3e8 389
ef1fd2df
PK		 390 if (!of_device_is_available(dev)) {
391 pr_warning("%s: disabled\n", dev->full_name);
392 return -ENODEV;
393 }
394
9ac4dd30 395 pr_debug("Adding PCI host bridge %s\n", dev->full_name);
b809b3e8
JL		 396
397 /* Fetch host bridge registers address */
9ac4dd30
ZR		 398 if (of_address_to_resource(dev, 0, &rsrc)) {
399 printk(KERN_WARNING "Can't get pci register base!");
400 return -ENOMEM;
401 }
b809b3e8
JL		 402
403 /* Get bus range if any */
e2eb6392 404 bus_range = of_get_property(dev, "bus-range", &len);
b809b3e8
JL		 405 if (bus_range == NULL || len < 2 * sizeof(int))
406 printk(KERN_WARNING "Can't get bus-range for %s, assume"
9ac4dd30 407 " bus 0\n", dev->full_name);
b809b3e8 408
0e47ff1c 409 pci_add_flags(PCI_REASSIGN_ALL_BUS);
dbf8471f 410 hose = pcibios_alloc_controller(dev);
b809b3e8
JL		 411 if (!hose)
412 return -ENOMEM;
dbf8471f 413
b809b3e8 414 hose->first_busno = bus_range ? bus_range[0] : 0x0;
bf7c036f 415 hose->last_busno = bus_range ? bus_range[1] : 0xff;
b809b3e8 416
2e56ff20
KG		 417 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
418 PPC_INDIRECT_TYPE_BIG_ENDIAN);
08871c09
PK		 419
420 early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif);
421 if ((progif & 1) == 1) {
422 /* unmap cfg_data & cfg_addr separately if not on same page */
423 if (((unsigned long)hose->cfg_data & PAGE_MASK) !=
424 ((unsigned long)hose->cfg_addr & PAGE_MASK))
425 iounmap(hose->cfg_data);
426 iounmap(hose->cfg_addr);
427 pcibios_free_controller(hose);
428 return 0;
429 }
430
9ac4dd30 431 setup_pci_cmd(hose);
b809b3e8 432
9ac4dd30 433 /* check PCI express link status */
957ecffc 434 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
7659c038 435 hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG |
957ecffc 436 PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
9ac4dd30 437 if (fsl_pcie_check_link(hose))
957ecffc
KG		 438 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
439 }
b809b3e8 440
df3c9019 441 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
9ac4dd30
ZR		 442 "Firmware bus number: %d->%d\n",
443 (unsigned long long)rsrc.start, hose->first_busno,
444 hose->last_busno);
b809b3e8 445
9ac4dd30 446 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
b809b3e8
JL		 447 hose, hose->cfg_addr, hose->cfg_data);
448
449 /* Interpret the "ranges" property */
450 /* This also maps the I/O region and sets isa_io/mem_base */
9ac4dd30 451 pci_process_bridge_OF_ranges(hose, dev, is_primary);
b809b3e8
JL		 452
453 /* Setup PEX window registers */
9ac4dd30 454 setup_pci_atmu(hose, &rsrc);
b809b3e8
JL		 455
456 return 0;
457}
5753c082 458#endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
76fe1ffc 459
470788d4 460DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_pcie_header);
598804cd 461
470788d4 462#if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
598804cd
AV		 463struct mpc83xx_pcie_priv {
464 void __iomem *cfg_type0;
465 void __iomem *cfg_type1;
466 u32 dev_base;
467};
468
b8f44ec2
KG		 469struct pex_inbound_window {
470 u32 ar;
471 u32 tar;
472 u32 barl;
473 u32 barh;
474};
475
598804cd
AV		 476/*
477 * With the convention of u-boot, the PCIE outbound window 0 serves
478 * as configuration transactions outbound.
479 */
480#define PEX_OUTWIN0_BAR 0xCA4
481#define PEX_OUTWIN0_TAL 0xCA8
482#define PEX_OUTWIN0_TAH 0xCAC
b8f44ec2
KG		 483#define PEX_RC_INWIN_BASE 0xE60
484#define PEX_RCIWARn_EN 0x1
598804cd
AV		 485
486static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn)
487{
8206a110 488 struct pci_controller *hose = pci_bus_to_host(bus);
598804cd
AV		 489
490 if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)
491 return PCIBIOS_DEVICE_NOT_FOUND;
492 /*
493 * Workaround for the HW bug: for Type 0 configure transactions the
494 * PCI-E controller does not check the device number bits and just
495 * assumes that the device number bits are 0.
496 */
497 if (bus->number == hose->first_busno ||
498 bus->primary == hose->first_busno) {
499 if (devfn & 0xf8)
500 return PCIBIOS_DEVICE_NOT_FOUND;
501 }
502
503 if (ppc_md.pci_exclude_device) {
504 if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
505 return PCIBIOS_DEVICE_NOT_FOUND;
506 }
507
508 return PCIBIOS_SUCCESSFUL;
509}
510
511static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus,
512 unsigned int devfn, int offset)
513{
8206a110 514 struct pci_controller *hose = pci_bus_to_host(bus);
598804cd 515 struct mpc83xx_pcie_priv *pcie = hose->dn->data;
f93611fa 516 u32 dev_base = bus->number << 24 | devfn << 16;
598804cd
AV		 517 int ret;
518
519 ret = mpc83xx_pcie_exclude_device(bus, devfn);
520 if (ret)
521 return NULL;
522
523 offset &= 0xfff;
524
525 /* Type 0 */
526 if (bus->number == hose->first_busno)
527 return pcie->cfg_type0 + offset;
528
529 if (pcie->dev_base == dev_base)
530 goto mapped;
531
532 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base);
533
534 pcie->dev_base = dev_base;
535mapped:
536 return pcie->cfg_type1 + offset;
537}
538
539static int mpc83xx_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
540 int offset, int len, u32 *val)
541{
542 void __iomem *cfg_addr;
543
544 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
545 if (!cfg_addr)
546 return PCIBIOS_DEVICE_NOT_FOUND;
547
548 switch (len) {
549 case 1:
550 *val = in_8(cfg_addr);
551 break;
552 case 2:
553 *val = in_le16(cfg_addr);
554 break;
555 default:
556 *val = in_le32(cfg_addr);
557 break;
558 }
559
560 return PCIBIOS_SUCCESSFUL;
561}
562
563static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
564 int offset, int len, u32 val)
565{
f93611fa 566 struct pci_controller *hose = pci_bus_to_host(bus);
598804cd
AV		 567 void __iomem *cfg_addr;
568
569 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
570 if (!cfg_addr)
571 return PCIBIOS_DEVICE_NOT_FOUND;
572
f93611fa
AV		 573 /* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */
574 if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno)
575 val &= 0xffffff00;
576
598804cd
AV		 577 switch (len) {
578 case 1:
579 out_8(cfg_addr, val);
580 break;
581 case 2:
582 out_le16(cfg_addr, val);
583 break;
584 default:
585 out_le32(cfg_addr, val);
586 break;
587 }
588
589 return PCIBIOS_SUCCESSFUL;
590}
591
592static struct pci_ops mpc83xx_pcie_ops = {
593 .read = mpc83xx_pcie_read_config,
594 .write = mpc83xx_pcie_write_config,
595};
596
597static int __init mpc83xx_pcie_setup(struct pci_controller *hose,
598 struct resource *reg)
599{
600 struct mpc83xx_pcie_priv *pcie;
601 u32 cfg_bar;
602 int ret = -ENOMEM;
603
604 pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL);
605 if (!pcie)
606 return ret;
607
608 pcie->cfg_type0 = ioremap(reg->start, resource_size(reg));
609 if (!pcie->cfg_type0)
610 goto err0;
611
612 cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR);
613 if (!cfg_bar) {
614 /* PCI-E isn't configured. */
615 ret = -ENODEV;
616 goto err1;
617 }
618
619 pcie->cfg_type1 = ioremap(cfg_bar, 0x1000);
620 if (!pcie->cfg_type1)
621 goto err1;
622
623 WARN_ON(hose->dn->data);
624 hose->dn->data = pcie;
625 hose->ops = &mpc83xx_pcie_ops;
626
627 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0);
628 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0);
629
630 if (fsl_pcie_check_link(hose))
631 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
632
633 return 0;
634err1:
635 iounmap(pcie->cfg_type0);
636err0:
637 kfree(pcie);
638 return ret;
639
640}
641
76fe1ffc
JR		 642int __init mpc83xx_add_bridge(struct device_node *dev)
643{
598804cd 644 int ret;
76fe1ffc
JR		 645 int len;
646 struct pci_controller *hose;
5b70a097
JR		 647 struct resource rsrc_reg;
648 struct resource rsrc_cfg;
76fe1ffc 649 const int *bus_range;
5b70a097 650 int primary;
76fe1ffc 651
b8f44ec2
KG		 652 is_mpc83xx_pci = 1;
653
598804cd
AV		 654 if (!of_device_is_available(dev)) {
655 pr_warning("%s: disabled by the firmware.\n",
656 dev->full_name);
657 return -ENODEV;
658 }
76fe1ffc
JR		 659 pr_debug("Adding PCI host bridge %s\n", dev->full_name);
660
661 /* Fetch host bridge registers address */
5b70a097
JR		 662 if (of_address_to_resource(dev, 0, &rsrc_reg)) {
663 printk(KERN_WARNING "Can't get pci register base!\n");
664 return -ENOMEM;
665 }
666
667 memset(&rsrc_cfg, 0, sizeof(rsrc_cfg));
668
669 if (of_address_to_resource(dev, 1, &rsrc_cfg)) {
670 printk(KERN_WARNING
671 "No pci config register base in dev tree, "
672 "using default\n");
673 /*
674 * MPC83xx supports up to two host controllers
675 * one at 0x8500 has config space registers at 0x8300
676 * one at 0x8600 has config space registers at 0x8380
677 */
678 if ((rsrc_reg.start & 0xfffff) == 0x8500)
679 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300;
680 else if ((rsrc_reg.start & 0xfffff) == 0x8600)
681 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380;
682 }
683 /*
684 * Controller at offset 0x8500 is primary
685 */
686 if ((rsrc_reg.start & 0xfffff) == 0x8500)
687 primary = 1;
688 else
689 primary = 0;
76fe1ffc
JR		 690
691 /* Get bus range if any */
692 bus_range = of_get_property(dev, "bus-range", &len);
693 if (bus_range == NULL || len < 2 * sizeof(int)) {
694 printk(KERN_WARNING "Can't get bus-range for %s, assume"
695 " bus 0\n", dev->full_name);
696 }
697
0e47ff1c 698 pci_add_flags(PCI_REASSIGN_ALL_BUS);
76fe1ffc
JR		 699 hose = pcibios_alloc_controller(dev);
700 if (!hose)
701 return -ENOMEM;
702
703 hose->first_busno = bus_range ? bus_range[0] : 0;
704 hose->last_busno = bus_range ? bus_range[1] : 0xff;
705
598804cd
AV		 706 if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) {
707 ret = mpc83xx_pcie_setup(hose, &rsrc_reg);
708 if (ret)
709 goto err0;
710 } else {
711 setup_indirect_pci(hose, rsrc_cfg.start,
712 rsrc_cfg.start + 4, 0);
713 }
76fe1ffc 714
35225802 715 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
76fe1ffc 716 "Firmware bus number: %d->%d\n",
5b70a097 717 (unsigned long long)rsrc_reg.start, hose->first_busno,
76fe1ffc
JR		 718 hose->last_busno);
719
720 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
721 hose, hose->cfg_addr, hose->cfg_data);
722
723 /* Interpret the "ranges" property */
724 /* This also maps the I/O region and sets isa_io/mem_base */
725 pci_process_bridge_OF_ranges(hose, dev, primary);
726
727 return 0;
598804cd
AV		 728err0:
729 pcibios_free_controller(hose);
730 return ret;
76fe1ffc
JR		 731}
732#endif /* CONFIG_PPC_83xx */
b8f44ec2
KG		 733
734u64 fsl_pci_immrbar_base(struct pci_controller *hose)
735{
736#ifdef CONFIG_PPC_83xx
737 if (is_mpc83xx_pci) {
738 struct mpc83xx_pcie_priv *pcie = hose->dn->data;
739 struct pex_inbound_window *in;
740 int i;
741
742 /* Walk the Root Complex Inbound windows to match IMMR base */
743 in = pcie->cfg_type0 + PEX_RC_INWIN_BASE;
744 for (i = 0; i < 4; i++) {
745 /* not enabled, skip */
746 if (!in_le32(&in[i].ar) & PEX_RCIWARn_EN)
747 continue;
748
749 if (get_immrbase() == in_le32(&in[i].tar))
750 return (u64)in_le32(&in[i].barh) << 32 |
751 in_le32(&in[i].barl);
752 }
753
754 printk(KERN_WARNING "could not find PCI BAR matching IMMR\n");
755 }
756#endif
757
758#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
759 if (!is_mpc83xx_pci) {
760 u32 base;
761
762 pci_bus_read_config_dword(hose->bus,
763 PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base);
764 return base;
765 }
766#endif
767
768 return 0;
769}
Linux kernel - Deliverables
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