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Merge branch 'drm-nouveau-fixes-3.8' of git://anongit.freedesktop.org/git/nouveau...
[deliverable/linux.git] / arch / powerpc / sysdev / fsl_pci.c
CommitLineData
b809b3e8 1/*
5b70a097 2 * MPC83xx/85xx/86xx PCI/PCIE support routing.
b809b3e8 3 *
07e4f801 4 * Copyright 2007-2012 Freescale Semiconductor, Inc.
598804cd 5 * Copyright 2008-2009 MontaVista Software, Inc.
b809b3e8 6 *
9ac4dd30
ZR		 7 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
8 * Recode: ZHANG WEI <wei.zhang@freescale.com>
9 * Rewrite the routing for Frescale PCI and PCI Express
10 * Roy Zang <tie-fei.zang@freescale.com>
598804cd
AV		 11 * MPC83xx PCI-Express support:
12 * Tony Li <tony.li@freescale.com>
13 * Anton Vorontsov <avorontsov@ru.mvista.com>
b809b3e8
JL		 14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 */
9ac4dd30 20#include <linux/kernel.h>
b809b3e8 21#include <linux/pci.h>
9ac4dd30
ZR		 22#include <linux/delay.h>
23#include <linux/string.h>
24#include <linux/init.h>
25#include <linux/bootmem.h>
95f72d1e 26#include <linux/memblock.h>
54c18193 27#include <linux/log2.h>
5a0e3ad6 28#include <linux/slab.h>
b809b3e8 29
b809b3e8
JL		 30#include <asm/io.h>
31#include <asm/prom.h>
b809b3e8 32#include <asm/pci-bridge.h>
9ac4dd30 33#include <asm/machdep.h>
b809b3e8 34#include <sysdev/fsl_soc.h>
55c44991 35#include <sysdev/fsl_pci.h>
b809b3e8 36
b8f44ec2 37static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
598804cd 38
cad5cef6 39static void quirk_fsl_pcie_header(struct pci_dev *dev)
598804cd 40{
59c58c32 41 u8 hdr_type;
470788d4 42
598804cd
AV		 43 /* if we aren't a PCIe don't bother */
44 if (!pci_find_capability(dev, PCI_CAP_ID_EXP))
45 return;
46
470788d4 47 /* if we aren't in host mode don't bother */
59c58c32
ML		 48 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type);
49 if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
470788d4
KG		 50 return;
51
598804cd
AV		 52 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
53 fsl_pcie_bus_fixup = 1;
54 return;
55}
56
57static int __init fsl_pcie_check_link(struct pci_controller *hose)
58{
59 u32 val;
60
61 early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
62 if (val < PCIE_LTSSM_L0)
63 return 1;
64 return 0;
65}
66
5753c082 67#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
96ea3b4a
KG		 68
69#define MAX_PHYS_ADDR_BITS 40
70static u64 pci64_dma_offset = 1ull << MAX_PHYS_ADDR_BITS;
71
72static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
73{
74 if (!dev->dma_mask || !dma_supported(dev, dma_mask))
75 return -EIO;
76
77 /*
78 * Fixup PCI devices that are able to DMA to above the physical
79 * address width of the SoC such that we can address any internal
80 * SoC address from across PCI if needed
81 */
82 if ((dev->bus == &pci_bus_type) &&
83 dma_mask >= DMA_BIT_MASK(MAX_PHYS_ADDR_BITS)) {
84 set_dma_ops(dev, &dma_direct_ops);
85 set_dma_offset(dev, pci64_dma_offset);
86 }
87
88 *dev->dma_mask = dma_mask;
89 return 0;
90}
91
a393d897 92static int setup_one_atmu(struct ccsr_pci __iomem *pci,
a097a78c
TP		 93 unsigned int index, const struct resource *res,
94 resource_size_t offset)
95{
96 resource_size_t pci_addr = res->start - offset;
97 resource_size_t phys_addr = res->start;
28f65c11 98 resource_size_t size = resource_size(res);
a097a78c
TP		 99 u32 flags = 0x80044000; /* enable & mem R/W */
100 unsigned int i;
101
102 pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n",
103 (u64)res->start, (u64)size);
104
565f3764
TP		 105 if (res->flags & IORESOURCE_PREFETCH)
106 flags |= 0x10000000; /* enable relaxed ordering */
107
a097a78c
TP		 108 for (i = 0; size > 0; i++) {
109 unsigned int bits = min(__ilog2(size),
110 __ffs(pci_addr | phys_addr));
111
112 if (index + i >= 5)
113 return -1;
114
115 out_be32(&pci->pow[index + i].potar, pci_addr >> 12);
116 out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44);
117 out_be32(&pci->pow[index + i].powbar, phys_addr >> 12);
118 out_be32(&pci->pow[index + i].powar, flags | (bits - 1));
119
120 pci_addr += (resource_size_t)1U << bits;
121 phys_addr += (resource_size_t)1U << bits;
122 size -= (resource_size_t)1U << bits;
123 }
124
125 return i;
126}
127
9ac4dd30 128/* atmu setup for fsl pci/pcie controller */
a393d897 129static void setup_pci_atmu(struct pci_controller *hose,
c9dadffb 130 struct resource *rsrc)
b809b3e8 131{
9ac4dd30 132 struct ccsr_pci __iomem *pci;
f4154e16 133 int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4;
54c18193
KG		 134 u64 mem, sz, paddr_hi = 0;
135 u64 paddr_lo = ULLONG_MAX;
136 u32 pcicsrbar = 0, pcicsrbar_sz;
137 u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL |
138 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
c22618a1 139 const char *name = hose->dn->full_name;
446bc1ff
TT		 140 const u64 *reg;
141 int len;
b809b3e8 142
72b122cc 143 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
28f65c11 144 (u64)rsrc->start, (u64)resource_size(rsrc));
f4154e16 145
28f65c11 146 pci = ioremap(rsrc->start, resource_size(rsrc));
a097a78c
TP		 147 if (!pci) {
148 dev_err(hose->parent, "Unable to map ATMU registers\n");
149 return;
150 }
9ac4dd30 151
9e67886b
RZ		 152 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
153 if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_2_2) {
154 win_idx = 2;
155 start_idx = 0;
156 end_idx = 3;
157 }
158 }
159
a097a78c 160 /* Disable all windows (except powar0 since it's ignored) */
9ac4dd30
ZR		 161 for(i = 1; i < 5; i++)
162 out_be32(&pci->pow[i].powar, 0);
f4154e16 163 for (i = start_idx; i < end_idx; i++)
9ac4dd30
ZR		 164 out_be32(&pci->piw[i].piwar, 0);
165
166 /* Setup outbound MEM window */
a097a78c
TP		 167 for(i = 0, j = 1; i < 3; i++) {
168 if (!(hose->mem_resources[i].flags & IORESOURCE_MEM))
169 continue;
170
54c18193
KG		 171 paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start);
172 paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end);
173
a097a78c
TP		 174 n = setup_one_atmu(pci, j, &hose->mem_resources[i],
175 hose->pci_mem_offset);
176
177 if (n < 0 || j >= 5) {
178 pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i);
179 hose->mem_resources[i].flags |= IORESOURCE_DISABLED;
180 } else
181 j += n;
182 }
9ac4dd30
ZR		 183
184 /* Setup outbound IO window */
a097a78c
TP		 185 if (hose->io_resource.flags & IORESOURCE_IO) {
186 if (j >= 5) {
187 pr_err("Ran out of outbound PCI ATMUs for IO resource\n");
188 } else {
189 pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "
190 "phy base 0x%016llx.\n",
28f65c11
JP		 191 (u64)hose->io_resource.start,
192 (u64)resource_size(&hose->io_resource),
193 (u64)hose->io_base_phys);
a097a78c
TP		 194 out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12));
195 out_be32(&pci->pow[j].potear, 0);
196 out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12));
197 /* Enable, IO R/W */
198 out_be32(&pci->pow[j].powar, 0x80088000
199 | (__ilog2(hose->io_resource.end
200 - hose->io_resource.start + 1) - 1));
201 }
9ac4dd30
ZR		 202 }
203
54c18193
KG		 204 /* convert to pci address space */
205 paddr_hi -= hose->pci_mem_offset;
206 paddr_lo -= hose->pci_mem_offset;
207
208 if (paddr_hi == paddr_lo) {
209 pr_err("%s: No outbound window space\n", name);
0cf572dc 210 goto out;
54c18193
KG		 211 }
212
213 if (paddr_lo == 0) {
214 pr_err("%s: No space for inbound window\n", name);
0cf572dc 215 goto out;
54c18193
KG		 216 }
217
218 /* setup PCSRBAR/PEXCSRBAR */
219 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff);
220 early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
221 pcicsrbar_sz = ~pcicsrbar_sz + 1;
222
223 if (paddr_hi < (0x100000000ull - pcicsrbar_sz) ||
224 (paddr_lo > 0x100000000ull))
225 pcicsrbar = 0x100000000ull - pcicsrbar_sz;
226 else
227 pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz;
228 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar);
229
230 paddr_lo = min(paddr_lo, (u64)pcicsrbar);
231
232 pr_info("%s: PCICSRBAR @ 0x%x\n", name, pcicsrbar);
233
234 /* Setup inbound mem window */
95f72d1e 235 mem = memblock_end_of_DRAM();
446bc1ff
TT		 236
237 /*
238 * The msi-address-64 property, if it exists, indicates the physical
239 * address of the MSIIR register. Normally, this register is located
240 * inside CCSR, so the ATMU that covers all of CCSR is used. But if
241 * this property exists, then we normally need to create a new ATMU
242 * for it. For now, however, we cheat. The only entity that creates
243 * this property is the Freescale hypervisor, and the address is
244 * specified in the partition configuration. Typically, the address
245 * is located in the page immediately after the end of DDR. If so, we
246 * can avoid allocating a new ATMU by extending the DDR ATMU by one
247 * page.
248 */
249 reg = of_get_property(hose->dn, "msi-address-64", &len);
250 if (reg && (len == sizeof(u64))) {
251 u64 address = be64_to_cpup(reg);
252
253 if ((address >= mem) && (address < (mem + PAGE_SIZE))) {
254 pr_info("%s: extending DDR ATMU to cover MSIIR", name);
255 mem += PAGE_SIZE;
256 } else {
257 /* TODO: Create a new ATMU for MSIIR */
258 pr_warn("%s: msi-address-64 address of %llx is "
259 "unsupported\n", name, address);
260 }
261 }
262
54c18193
KG		 263 sz = min(mem, paddr_lo);
264 mem_log = __ilog2_u64(sz);
265
266 /* PCIe can overmap inbound & outbound since RX & TX are separated */
267 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
268 /* Size window to exact size if power-of-two or one size up */
269 if ((1ull << mem_log) != mem) {
270 if ((1ull << mem_log) > mem)
271 pr_info("%s: Setting PCI inbound window "
272 "greater than memory size\n", name);
273 mem_log++;
274 }
275
f4154e16 276 piwar |= ((mem_log - 1) & PIWAR_SZ_MASK);
54c18193
KG		 277
278 /* Setup inbound memory window */
279 out_be32(&pci->piw[win_idx].pitar, 0x00000000);
280 out_be32(&pci->piw[win_idx].piwbar, 0x00000000);
281 out_be32(&pci->piw[win_idx].piwar, piwar);
282 win_idx--;
283
284 hose->dma_window_base_cur = 0x00000000;
285 hose->dma_window_size = (resource_size_t)sz;
96ea3b4a
KG		 286
287 /*
288 * if we have >4G of memory setup second PCI inbound window to
289 * let devices that are 64-bit address capable to work w/o
290 * SWIOTLB and access the full range of memory
291 */
292 if (sz != mem) {
293 mem_log = __ilog2_u64(mem);
294
295 /* Size window up if we dont fit in exact power-of-2 */
296 if ((1ull << mem_log) != mem)
297 mem_log++;
298
299 piwar = (piwar & ~PIWAR_SZ_MASK) | (mem_log - 1);
300
301 /* Setup inbound memory window */
302 out_be32(&pci->piw[win_idx].pitar, 0x00000000);
303 out_be32(&pci->piw[win_idx].piwbear,
304 pci64_dma_offset >> 44);
305 out_be32(&pci->piw[win_idx].piwbar,
306 pci64_dma_offset >> 12);
307 out_be32(&pci->piw[win_idx].piwar, piwar);
308
309 /*
310 * install our own dma_set_mask handler to fixup dma_ops
311 * and dma_offset
312 */
313 ppc_md.dma_set_mask = fsl_pci_dma_set_mask;
314
315 pr_info("%s: Setup 64-bit PCI DMA window\n", name);
316 }
54c18193
KG		 317 } else {
318 u64 paddr = 0;
319
320 /* Setup inbound memory window */
321 out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
322 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
323 out_be32(&pci->piw[win_idx].piwar, (piwar | (mem_log - 1)));
324 win_idx--;
325
326 paddr += 1ull << mem_log;
327 sz -= 1ull << mem_log;
328
329 if (sz) {
330 mem_log = __ilog2_u64(sz);
331 piwar |= (mem_log - 1);
332
333 out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
334 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
335 out_be32(&pci->piw[win_idx].piwar, piwar);
336 win_idx--;
337
338 paddr += 1ull << mem_log;
339 }
340
341 hose->dma_window_base_cur = 0x00000000;
342 hose->dma_window_size = (resource_size_t)paddr;
343 }
a097a78c 344
54c18193
KG		 345 if (hose->dma_window_size < mem) {
346#ifndef CONFIG_SWIOTLB
347 pr_err("%s: ERROR: Memory size exceeds PCI ATMU ability to "
348 "map - enable CONFIG_SWIOTLB to avoid dma errors.\n",
349 name);
350#endif
351 /* adjusting outbound windows could reclaim space in mem map */
352 if (paddr_hi < 0xffffffffull)
353 pr_warning("%s: WARNING: Outbound window cfg leaves "
354 "gaps in memory map. Adjusting the memory map "
355 "could reduce unnecessary bounce buffering.\n",
356 name);
357
358 pr_info("%s: DMA window size is 0x%llx\n", name,
359 (u64)hose->dma_window_size);
360 }
89d93347 361
0cf572dc 362out:
a097a78c 363 iounmap(pci);
b809b3e8
JL		 364}
365
c9dadffb 366static void __init setup_pci_cmd(struct pci_controller *hose)
b809b3e8 367{
b809b3e8 368 u16 cmd;
eb12af43
KG		 369 int cap_x;
370
b809b3e8
JL		 371 early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
372 cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
9ac4dd30 373 | PCI_COMMAND_IO;
b809b3e8 374 early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
eb12af43
KG		 375
376 cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX);
377 if (cap_x) {
378 int pci_x_cmd = cap_x + PCI_X_CMD;
379 cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
380 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
381 early_write_config_word(hose, 0, 0, pci_x_cmd, cmd);
382 } else {
383 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
384 }
9ad494f6
KG		 385}
386
6c0a11c1
KG		 387void fsl_pcibios_fixup_bus(struct pci_bus *bus)
388{
8206a110 389 struct pci_controller *hose = pci_bus_to_host(bus);
13635dfd
BH		 390 int i, is_pcie = 0, no_link;
391
392 /* The root complex bridge comes up with bogus resources,
393 * we copy the PHB ones in.
394 *
395 * With the current generic PCI code, the PHB bus no longer
396 * has bus->resource[0..4] set, so things are a bit more
397 * tricky.
398 */
399
400 if (fsl_pcie_bus_fixup)
401 is_pcie = early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP);
402 no_link = !!(hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK);
403
404 if (bus->parent == hose->bus && (is_pcie || no_link)) {
405 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; ++i) {
72b122cc 406 struct resource *res = bus->resource[i];
13635dfd
BH		 407 struct resource *par;
408
409 if (!res)
410 continue;
411 if (i == 0)
412 par = &hose->io_resource;
413 else if (i < 4)
414 par = &hose->mem_resources[i-1];
415 else par = NULL;
416
417 res->start = par ? par->start : 0;
418 res->end = par ? par->end : 0;
419 res->flags = par ? par->flags : 0;
6c0a11c1
KG		 420 }
421 }
422}
423
9ac4dd30 424int __init fsl_add_bridge(struct device_node *dev, int is_primary)
b809b3e8
JL		 425{
426 int len;
427 struct pci_controller *hose;
428 struct resource rsrc;
8efca493 429 const int *bus_range;
59c58c32 430 u8 hdr_type, progif;
b809b3e8 431
ef1fd2df
PK		 432 if (!of_device_is_available(dev)) {
433 pr_warning("%s: disabled\n", dev->full_name);
434 return -ENODEV;
435 }
436
9ac4dd30 437 pr_debug("Adding PCI host bridge %s\n", dev->full_name);
b809b3e8
JL		 438
439 /* Fetch host bridge registers address */
9ac4dd30
ZR		 440 if (of_address_to_resource(dev, 0, &rsrc)) {
441 printk(KERN_WARNING "Can't get pci register base!");
442 return -ENOMEM;
443 }
b809b3e8
JL		 444
445 /* Get bus range if any */
e2eb6392 446 bus_range = of_get_property(dev, "bus-range", &len);
b809b3e8
JL		 447 if (bus_range == NULL || len < 2 * sizeof(int))
448 printk(KERN_WARNING "Can't get bus-range for %s, assume"
9ac4dd30 449 " bus 0\n", dev->full_name);
b809b3e8 450
0e47ff1c 451 pci_add_flags(PCI_REASSIGN_ALL_BUS);
dbf8471f 452 hose = pcibios_alloc_controller(dev);
b809b3e8
JL		 453 if (!hose)
454 return -ENOMEM;
dbf8471f 455
b809b3e8 456 hose->first_busno = bus_range ? bus_range[0] : 0x0;
bf7c036f 457 hose->last_busno = bus_range ? bus_range[1] : 0xff;
b809b3e8 458
2e56ff20
KG		 459 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
460 PPC_INDIRECT_TYPE_BIG_ENDIAN);
08871c09 461
59c58c32
ML		 462 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
463 /* For PCIE read HEADER_TYPE to identify controler mode */
464 early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &hdr_type);
465 if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
466 goto no_bridge;
467
468 } else {
469 /* For PCI read PROG to identify controller mode */
470 early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif);
471 if ((progif & 1) == 1)
472 goto no_bridge;
08871c09
PK		 473 }
474
9ac4dd30 475 setup_pci_cmd(hose);
b809b3e8 476
9ac4dd30 477 /* check PCI express link status */
957ecffc 478 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
7659c038 479 hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG |
957ecffc 480 PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
9ac4dd30 481 if (fsl_pcie_check_link(hose))
957ecffc
KG		 482 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
483 }
b809b3e8 484
df3c9019 485 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
9ac4dd30
ZR		 486 "Firmware bus number: %d->%d\n",
487 (unsigned long long)rsrc.start, hose->first_busno,
488 hose->last_busno);
b809b3e8 489
9ac4dd30 490 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
b809b3e8
JL		 491 hose, hose->cfg_addr, hose->cfg_data);
492
493 /* Interpret the "ranges" property */
494 /* This also maps the I/O region and sets isa_io/mem_base */
9ac4dd30 495 pci_process_bridge_OF_ranges(hose, dev, is_primary);
b809b3e8
JL		 496
497 /* Setup PEX window registers */
9ac4dd30 498 setup_pci_atmu(hose, &rsrc);
b809b3e8
JL		 499
500 return 0;
59c58c32
ML		 501
502no_bridge:
503 /* unmap cfg_data & cfg_addr separately if not on same page */
504 if (((unsigned long)hose->cfg_data & PAGE_MASK) !=
505 ((unsigned long)hose->cfg_addr & PAGE_MASK))
506 iounmap(hose->cfg_data);
507 iounmap(hose->cfg_addr);
508 pcibios_free_controller(hose);
509 return -ENODEV;
b809b3e8 510}
5753c082 511#endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
76fe1ffc 512
470788d4 513DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_pcie_header);
598804cd 514
470788d4 515#if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
598804cd
AV		 516struct mpc83xx_pcie_priv {
517 void __iomem *cfg_type0;
518 void __iomem *cfg_type1;
519 u32 dev_base;
520};
521
b8f44ec2
KG		 522struct pex_inbound_window {
523 u32 ar;
524 u32 tar;
525 u32 barl;
526 u32 barh;
527};
528
598804cd
AV		 529/*
530 * With the convention of u-boot, the PCIE outbound window 0 serves
531 * as configuration transactions outbound.
532 */
533#define PEX_OUTWIN0_BAR 0xCA4
534#define PEX_OUTWIN0_TAL 0xCA8
535#define PEX_OUTWIN0_TAH 0xCAC
b8f44ec2
KG		 536#define PEX_RC_INWIN_BASE 0xE60
537#define PEX_RCIWARn_EN 0x1
598804cd
AV		 538
539static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn)
540{
8206a110 541 struct pci_controller *hose = pci_bus_to_host(bus);
598804cd
AV		 542
543 if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)
544 return PCIBIOS_DEVICE_NOT_FOUND;
545 /*
546 * Workaround for the HW bug: for Type 0 configure transactions the
547 * PCI-E controller does not check the device number bits and just
548 * assumes that the device number bits are 0.
549 */
550 if (bus->number == hose->first_busno ||
551 bus->primary == hose->first_busno) {
552 if (devfn & 0xf8)
553 return PCIBIOS_DEVICE_NOT_FOUND;
554 }
555
556 if (ppc_md.pci_exclude_device) {
557 if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
558 return PCIBIOS_DEVICE_NOT_FOUND;
559 }
560
561 return PCIBIOS_SUCCESSFUL;
562}
563
564static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus,
565 unsigned int devfn, int offset)
566{
8206a110 567 struct pci_controller *hose = pci_bus_to_host(bus);
598804cd 568 struct mpc83xx_pcie_priv *pcie = hose->dn->data;
f93611fa 569 u32 dev_base = bus->number << 24 | devfn << 16;
598804cd
AV		 570 int ret;
571
572 ret = mpc83xx_pcie_exclude_device(bus, devfn);
573 if (ret)
574 return NULL;
575
576 offset &= 0xfff;
577
578 /* Type 0 */
579 if (bus->number == hose->first_busno)
580 return pcie->cfg_type0 + offset;
581
582 if (pcie->dev_base == dev_base)
583 goto mapped;
584
585 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base);
586
587 pcie->dev_base = dev_base;
588mapped:
589 return pcie->cfg_type1 + offset;
590}
591
592static int mpc83xx_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
593 int offset, int len, u32 *val)
594{
595 void __iomem *cfg_addr;
596
597 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
598 if (!cfg_addr)
599 return PCIBIOS_DEVICE_NOT_FOUND;
600
601 switch (len) {
602 case 1:
603 *val = in_8(cfg_addr);
604 break;
605 case 2:
606 *val = in_le16(cfg_addr);
607 break;
608 default:
609 *val = in_le32(cfg_addr);
610 break;
611 }
612
613 return PCIBIOS_SUCCESSFUL;
614}
615
616static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
617 int offset, int len, u32 val)
618{
f93611fa 619 struct pci_controller *hose = pci_bus_to_host(bus);
598804cd
AV		 620 void __iomem *cfg_addr;
621
622 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
623 if (!cfg_addr)
624 return PCIBIOS_DEVICE_NOT_FOUND;
625
f93611fa
AV		 626 /* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */
627 if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno)
628 val &= 0xffffff00;
629
598804cd
AV		 630 switch (len) {
631 case 1:
632 out_8(cfg_addr, val);
633 break;
634 case 2:
635 out_le16(cfg_addr, val);
636 break;
637 default:
638 out_le32(cfg_addr, val);
639 break;
640 }
641
642 return PCIBIOS_SUCCESSFUL;
643}
644
645static struct pci_ops mpc83xx_pcie_ops = {
646 .read = mpc83xx_pcie_read_config,
647 .write = mpc83xx_pcie_write_config,
648};
649
650static int __init mpc83xx_pcie_setup(struct pci_controller *hose,
651 struct resource *reg)
652{
653 struct mpc83xx_pcie_priv *pcie;
654 u32 cfg_bar;
655 int ret = -ENOMEM;
656
657 pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL);
658 if (!pcie)
659 return ret;
660
661 pcie->cfg_type0 = ioremap(reg->start, resource_size(reg));
662 if (!pcie->cfg_type0)
663 goto err0;
664
665 cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR);
666 if (!cfg_bar) {
667 /* PCI-E isn't configured. */
668 ret = -ENODEV;
669 goto err1;
670 }
671
672 pcie->cfg_type1 = ioremap(cfg_bar, 0x1000);
673 if (!pcie->cfg_type1)
674 goto err1;
675
676 WARN_ON(hose->dn->data);
677 hose->dn->data = pcie;
678 hose->ops = &mpc83xx_pcie_ops;
679
680 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0);
681 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0);
682
683 if (fsl_pcie_check_link(hose))
684 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
685
686 return 0;
687err1:
688 iounmap(pcie->cfg_type0);
689err0:
690 kfree(pcie);
691 return ret;
692
693}
694
76fe1ffc
JR		 695int __init mpc83xx_add_bridge(struct device_node *dev)
696{
598804cd 697 int ret;
76fe1ffc
JR		 698 int len;
699 struct pci_controller *hose;
5b70a097
JR		 700 struct resource rsrc_reg;
701 struct resource rsrc_cfg;
76fe1ffc 702 const int *bus_range;
5b70a097 703 int primary;
76fe1ffc 704
b8f44ec2
KG		 705 is_mpc83xx_pci = 1;
706
598804cd
AV		 707 if (!of_device_is_available(dev)) {
708 pr_warning("%s: disabled by the firmware.\n",
709 dev->full_name);
710 return -ENODEV;
711 }
76fe1ffc
JR		 712 pr_debug("Adding PCI host bridge %s\n", dev->full_name);
713
714 /* Fetch host bridge registers address */
5b70a097
JR		 715 if (of_address_to_resource(dev, 0, &rsrc_reg)) {
716 printk(KERN_WARNING "Can't get pci register base!\n");
717 return -ENOMEM;
718 }
719
720 memset(&rsrc_cfg, 0, sizeof(rsrc_cfg));
721
722 if (of_address_to_resource(dev, 1, &rsrc_cfg)) {
723 printk(KERN_WARNING
724 "No pci config register base in dev tree, "
725 "using default\n");
726 /*
727 * MPC83xx supports up to two host controllers
728 * one at 0x8500 has config space registers at 0x8300
729 * one at 0x8600 has config space registers at 0x8380
730 */
731 if ((rsrc_reg.start & 0xfffff) == 0x8500)
732 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300;
733 else if ((rsrc_reg.start & 0xfffff) == 0x8600)
734 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380;
735 }
736 /*
737 * Controller at offset 0x8500 is primary
738 */
739 if ((rsrc_reg.start & 0xfffff) == 0x8500)
740 primary = 1;
741 else
742 primary = 0;
76fe1ffc
JR		 743
744 /* Get bus range if any */
745 bus_range = of_get_property(dev, "bus-range", &len);
746 if (bus_range == NULL || len < 2 * sizeof(int)) {
747 printk(KERN_WARNING "Can't get bus-range for %s, assume"
748 " bus 0\n", dev->full_name);
749 }
750
0e47ff1c 751 pci_add_flags(PCI_REASSIGN_ALL_BUS);
76fe1ffc
JR		 752 hose = pcibios_alloc_controller(dev);
753 if (!hose)
754 return -ENOMEM;
755
756 hose->first_busno = bus_range ? bus_range[0] : 0;
757 hose->last_busno = bus_range ? bus_range[1] : 0xff;
758
598804cd
AV		 759 if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) {
760 ret = mpc83xx_pcie_setup(hose, &rsrc_reg);
761 if (ret)
762 goto err0;
763 } else {
764 setup_indirect_pci(hose, rsrc_cfg.start,
765 rsrc_cfg.start + 4, 0);
766 }
76fe1ffc 767
35225802 768 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
76fe1ffc 769 "Firmware bus number: %d->%d\n",
5b70a097 770 (unsigned long long)rsrc_reg.start, hose->first_busno,
76fe1ffc
JR		 771 hose->last_busno);
772
773 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
774 hose, hose->cfg_addr, hose->cfg_data);
775
776 /* Interpret the "ranges" property */
777 /* This also maps the I/O region and sets isa_io/mem_base */
778 pci_process_bridge_OF_ranges(hose, dev, primary);
779
780 return 0;
598804cd
AV		 781err0:
782 pcibios_free_controller(hose);
783 return ret;
76fe1ffc
JR		 784}
785#endif /* CONFIG_PPC_83xx */
b8f44ec2
KG		 786
787u64 fsl_pci_immrbar_base(struct pci_controller *hose)
788{
789#ifdef CONFIG_PPC_83xx
790 if (is_mpc83xx_pci) {
791 struct mpc83xx_pcie_priv *pcie = hose->dn->data;
792 struct pex_inbound_window *in;
793 int i;
794
795 /* Walk the Root Complex Inbound windows to match IMMR base */
796 in = pcie->cfg_type0 + PEX_RC_INWIN_BASE;
797 for (i = 0; i < 4; i++) {
798 /* not enabled, skip */
799 if (!in_le32(&in[i].ar) & PEX_RCIWARn_EN)
800 continue;
801
802 if (get_immrbase() == in_le32(&in[i].tar))
803 return (u64)in_le32(&in[i].barh) << 32 |
804 in_le32(&in[i].barl);
805 }
806
807 printk(KERN_WARNING "could not find PCI BAR matching IMMR\n");
808 }
809#endif
810
811#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
812 if (!is_mpc83xx_pci) {
813 u32 base;
814
815 pci_bus_read_config_dword(hose->bus,
816 PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base);
817 return base;
818 }
819#endif
820
821 return 0;
822}
07e4f801
SW		 823
824#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
825static const struct of_device_id pci_ids[] = {
826 { .compatible = "fsl,mpc8540-pci", },
827 { .compatible = "fsl,mpc8548-pcie", },
828 { .compatible = "fsl,mpc8610-pci", },
829 { .compatible = "fsl,mpc8641-pcie", },
830 { .compatible = "fsl,p1022-pcie", },
831 { .compatible = "fsl,p1010-pcie", },
832 { .compatible = "fsl,p1023-pcie", },
833 { .compatible = "fsl,p4080-pcie", },
708998c9 834 { .compatible = "fsl,qoriq-pcie-v2.4", },
07e4f801
SW		 835 { .compatible = "fsl,qoriq-pcie-v2.3", },
836 { .compatible = "fsl,qoriq-pcie-v2.2", },
837 {},
838};
839
840struct device_node *fsl_pci_primary;
841
905e75c4 842void fsl_pci_assign_primary(void)
07e4f801 843{
905e75c4 844 struct device_node *np;
07e4f801
SW		 845
846 /* Callers can specify the primary bus using other means. */
905e75c4
JH		 847 if (fsl_pci_primary)
848 return;
849
850 /* If a PCI host bridge contains an ISA node, it's primary. */
851 np = of_find_node_by_type(NULL, "isa");
852 while ((fsl_pci_primary = of_get_parent(np))) {
853 of_node_put(np);
854 np = fsl_pci_primary;
855
856 if (of_match_node(pci_ids, np) && of_device_is_available(np))
857 return;
07e4f801
SW		 858 }
859
905e75c4
JH		 860 /*
861 * If there's no PCI host bridge with ISA, arbitrarily
862 * designate one as primary. This can go away once
863 * various bugs with primary-less systems are fixed.
864 */
865 for_each_matching_node(np, pci_ids) {
866 if (of_device_is_available(np)) {
867 fsl_pci_primary = np;
868 of_node_put(np);
869 return;
07e4f801
SW		 870 }
871 }
905e75c4
JH		 872}
873
cad5cef6 874static int fsl_pci_probe(struct platform_device *pdev)
905e75c4
JH		 875{
876 int ret;
877 struct device_node *node;
4d56dec5 878#ifdef CONFIG_SWIOTLB
905e75c4 879 struct pci_controller *hose;
4d56dec5 880#endif
905e75c4
JH		 881
882 node = pdev->dev.of_node;
883 ret = fsl_add_bridge(node, fsl_pci_primary == node);
07e4f801
SW		 884
885#ifdef CONFIG_SWIOTLB
905e75c4
JH		 886 if (ret == 0) {
887 hose = pci_find_hose_for_OF_device(pdev->dev.of_node);
888
889 /*
890 * if we couldn't map all of DRAM via the dma windows
891 * we need SWIOTLB to handle buffers located outside of
892 * dma capable memory region
893 */
894 if (memblock_end_of_DRAM() - 1 > hose->dma_window_base_cur +
895 hose->dma_window_size)
896 ppc_swiotlb_enable = 1;
897 }
07e4f801 898#endif
905e75c4
JH		 899
900 mpc85xx_pci_err_probe(pdev);
901
902 return 0;
903}
904
a393d897
JH		 905#ifdef CONFIG_PM
906static int fsl_pci_resume(struct device *dev)
907{
908 struct pci_controller *hose;
909 struct resource pci_rsrc;
910
911 hose = pci_find_hose_for_OF_device(dev->of_node);
912 if (!hose)
913 return -ENODEV;
914
915 if (of_address_to_resource(dev->of_node, 0, &pci_rsrc)) {
916 dev_err(dev, "Get pci register base failed.");
917 return -ENODEV;
918 }
919
920 setup_pci_atmu(hose, &pci_rsrc);
921
922 return 0;
923}
924
925static const struct dev_pm_ops pci_pm_ops = {
926 .resume = fsl_pci_resume,
927};
928
929#define PCI_PM_OPS (&pci_pm_ops)
930
931#else
932
933#define PCI_PM_OPS NULL
934
935#endif
936
905e75c4
JH		 937static struct platform_driver fsl_pci_driver = {
938 .driver = {
939 .name = "fsl-pci",
a393d897 940 .pm = PCI_PM_OPS,
905e75c4
JH		 941 .of_match_table = pci_ids,
942 },
943 .probe = fsl_pci_probe,
944};
945
946static int __init fsl_pci_init(void)
947{
948 return platform_driver_register(&fsl_pci_driver);
07e4f801 949}
905e75c4 950arch_initcall(fsl_pci_init);
07e4f801 951#endif
Linux kernel - Deliverables
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