[deliverable/linux.git] / arch / powerpc / sysdev / fsl_pci.h

/*
 * MPC85xx/86xx PCI Express structure define
 *
 * Copyright 2007,2011 Freescale Semiconductor, Inc
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 */

#ifdef __KERNEL__
#ifndef __POWERPC_FSL_PCI_H
#define __POWERPC_FSL_PCI_H

struct platform_device;


/* FSL PCI controller BRR1 register */
#define PCI_FSL_BRR1      0xbf8
#define PCI_FSL_BRR1_VER 0xffff

#define PCIE_LTSSM	0x0404		/* PCIE Link Training and Status */
#define PCIE_LTSSM_L0	0x16		/* L0 state */
#define PCIE_IP_REV_2_2		0x02080202 /* PCIE IP block version Rev2.2 */
#define PCIE_IP_REV_3_0		0x02080300 /* PCIE IP block version Rev3.0 */
#define PIWAR_EN		0x80000000	/* Enable */
#define PIWAR_PF		0x20000000	/* prefetch */
#define PIWAR_TGI_LOCAL		0x00f00000	/* target - local memory */
#define PIWAR_READ_SNOOP	0x00050000
#define PIWAR_WRITE_SNOOP	0x00005000
#define PIWAR_SZ_MASK          0x0000003f

#define PEX_PMCR_PTOMR		0x1
#define PEX_PMCR_EXL2S		0x2

#define PME_DISR_EN_PTOD	0x00008000
#define PME_DISR_EN_ENL23D	0x00002000
#define PME_DISR_EN_EXL23D	0x00001000

/* PCI/PCI Express outbound window reg */
struct pci_outbound_window_regs {
	__be32	potar;	/* 0x.0 - Outbound translation address register */
	__be32	potear;	/* 0x.4 - Outbound translation extended address register */
	__be32	powbar;	/* 0x.8 - Outbound window base address register */
	u8	res1[4];
	__be32	powar;	/* 0x.10 - Outbound window attributes register */
	u8	res2[12];
};

/* PCI/PCI Express inbound window reg */
struct pci_inbound_window_regs {
	__be32	pitar;	/* 0x.0 - Inbound translation address register */
	u8	res1[4];
	__be32	piwbar;	/* 0x.8 - Inbound window base address register */
	__be32	piwbear;	/* 0x.c - Inbound window base extended address register */
	__be32	piwar;	/* 0x.10 - Inbound window attributes register */
	u8	res2[12];
};

/* PCI/PCI Express IO block registers for 85xx/86xx */
struct ccsr_pci {
	__be32	config_addr;		/* 0x.000 - PCI/PCIE Configuration Address Register */
	__be32	config_data;		/* 0x.004 - PCI/PCIE Configuration Data Register */
	__be32	int_ack;		/* 0x.008 - PCI Interrupt Acknowledge Register */
	__be32	pex_otb_cpl_tor;	/* 0x.00c - PCIE Outbound completion timeout register */
	__be32	pex_conf_tor;		/* 0x.010 - PCIE configuration timeout register */
	__be32	pex_config;		/* 0x.014 - PCIE CONFIG Register */
	__be32	pex_int_status;		/* 0x.018 - PCIE interrupt status */
	u8	res2[4];
	__be32	pex_pme_mes_dr;		/* 0x.020 - PCIE PME and message detect register */
	__be32	pex_pme_mes_disr;	/* 0x.024 - PCIE PME and message disable register */
	__be32	pex_pme_mes_ier;	/* 0x.028 - PCIE PME and message interrupt enable register */
	__be32	pex_pmcr;		/* 0x.02c - PCIE power management command register */
	u8	res3[3016];
	__be32	block_rev1;	/* 0x.bf8 - PCIE Block Revision register 1 */
	__be32	block_rev2;	/* 0x.bfc - PCIE Block Revision register 2 */

/* PCI/PCI Express outbound window 0-4
 * Window 0 is the default window and is the only window enabled upon reset.
 * The default outbound register set is used when a transaction misses
 * in all of the other outbound windows.
 */
	struct pci_outbound_window_regs pow[5];
	u8	res14[96];
	struct pci_inbound_window_regs	pmit;	/* 0xd00 - 0xd9c Inbound MSI */
	u8	res6[96];
/* PCI/PCI Express inbound window 3-0
 * inbound window 1 supports only a 32-bit base address and does not
 * define an inbound window base extended address register.
 */
	struct pci_inbound_window_regs piw[4];

	__be32	pex_err_dr;		/* 0x.e00 - PCI/PCIE error detect register */
	u8	res21[4];
	__be32	pex_err_en;		/* 0x.e08 - PCI/PCIE error interrupt enable register */
	u8	res22[4];
	__be32	pex_err_disr;		/* 0x.e10 - PCI/PCIE error disable register */
	u8	res23[12];
	__be32	pex_err_cap_stat;	/* 0x.e20 - PCI/PCIE error capture status register */
	u8	res24[4];
	__be32	pex_err_cap_r0;		/* 0x.e28 - PCIE error capture register 0 */
	__be32	pex_err_cap_r1;		/* 0x.e2c - PCIE error capture register 0 */
	__be32	pex_err_cap_r2;		/* 0x.e30 - PCIE error capture register 0 */
	__be32	pex_err_cap_r3;		/* 0x.e34 - PCIE error capture register 0 */
	u8	res_e38[200];
	__be32	pdb_stat;		/* 0x.f00 - PCIE Debug Status */
	u8	res_f04[16];
	__be32	pex_csr0;		/* 0x.f14 - PEX Control/Status register 0*/
#define PEX_CSR0_LTSSM_MASK	0xFC
#define PEX_CSR0_LTSSM_SHIFT	2
#define PEX_CSR0_LTSSM_L0	0x11
	__be32	pex_csr1;		/* 0x.f18 - PEX Control/Status register 1*/
	u8	res_f1c[228];

};

extern int fsl_add_bridge(struct platform_device *pdev, int is_primary);
extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
extern void fsl_pcibios_fixup_phb(struct pci_controller *phb);
extern int mpc83xx_add_bridge(struct device_node *dev);
u64 fsl_pci_immrbar_base(struct pci_controller *hose);

extern struct device_node *fsl_pci_primary;

#ifdef CONFIG_PCI
void fsl_pci_assign_primary(void);
#else
static inline void fsl_pci_assign_primary(void) {}
#endif

#ifdef CONFIG_FSL_PCI
extern int fsl_pci_mcheck_exception(struct pt_regs *);
#else
static inline int fsl_pci_mcheck_exception(struct pt_regs *regs) {return 0; }
#endif

#endif /* __POWERPC_FSL_PCI_H */
#endif /* __KERNEL__ */
Commit	Line	Data
9eb90a0c ZR	1	/*
	2	* MPC85xx/86xx PCI Express structure define
	3	*
f4154e16	4	* Copyright 2007,2011 Freescale Semiconductor, Inc
9eb90a0c ZR	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*
	11	*/
	12
	13	#ifdef __KERNEL__
9ac4dd30 ZR	14	#ifndef __POWERPC_FSL_PCI_H
9ac4dd30 ZR	15	#define __POWERPC_FSL_PCI_H
9eb90a0c	16
c7417202 JH	17	struct platform_device;
c7417202 JH	18
695093e3 VS	19
	20	/* FSL PCI controller BRR1 register */
	21	#define PCI_FSL_BRR1 0xbf8
	22	#define PCI_FSL_BRR1_VER 0xffff
	23
9ac4dd30 ZR	24	#define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */
9ac4dd30 ZR	25	#define PCIE_LTSSM_L0 0x16 /* L0 state */
6cc1b4e9	26	#define PCIE_IP_REV_2_2 0x02080202 /* PCIE IP block version Rev2.2 */
cc6ea0dd	27	#define PCIE_IP_REV_3_0 0x02080300 /* PCIE IP block version Rev3.0 */
54c18193 KG	28	#define PIWAR_EN 0x80000000 /* Enable */
	29	#define PIWAR_PF 0x20000000 /* prefetch */
	30	#define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */
	31	#define PIWAR_READ_SNOOP 0x00050000
	32	#define PIWAR_WRITE_SNOOP 0x00005000
f4154e16	33	#define PIWAR_SZ_MASK 0x0000003f
9eb90a0c	34
48b16180 WD	35	#define PEX_PMCR_PTOMR 0x1
	36	#define PEX_PMCR_EXL2S 0x2
	37
	38	#define PME_DISR_EN_PTOD 0x00008000
	39	#define PME_DISR_EN_ENL23D 0x00002000
	40	#define PME_DISR_EN_EXL23D 0x00001000
	41
9ac4dd30 ZR	42	/* PCI/PCI Express outbound window reg */
	43	struct pci_outbound_window_regs {
	44	__be32 potar; /* 0x.0 - Outbound translation address register */
	45	__be32 potear; /* 0x.4 - Outbound translation extended address register */
	46	__be32 powbar; /* 0x.8 - Outbound window base address register */
	47	u8 res1[4];
	48	__be32 powar; /* 0x.10 - Outbound window attributes register */
	49	u8 res2[12];
9eb90a0c ZR	50	};
9eb90a0c ZR	51
9ac4dd30 ZR	52	/* PCI/PCI Express inbound window reg */
	53	struct pci_inbound_window_regs {
	54	__be32 pitar; /* 0x.0 - Inbound translation address register */
	55	u8 res1[4];
	56	__be32 piwbar; /* 0x.8 - Inbound window base address register */
	57	__be32 piwbear; /* 0x.c - Inbound window base extended address register */
	58	__be32 piwar; /* 0x.10 - Inbound window attributes register */
	59	u8 res2[12];
	60	};
	61
	62	/* PCI/PCI Express IO block registers for 85xx/86xx */
	63	struct ccsr_pci {
	64	__be32 config_addr; /* 0x.000 - PCI/PCIE Configuration Address Register */
	65	__be32 config_data; /* 0x.004 - PCI/PCIE Configuration Data Register */
	66	__be32 int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */
	67	__be32 pex_otb_cpl_tor; /* 0x.00c - PCIE Outbound completion timeout register */
	68	__be32 pex_conf_tor; /* 0x.010 - PCIE configuration timeout register */
f4154e16 PK	69	__be32 pex_config; /* 0x.014 - PCIE CONFIG Register */
	70	__be32 pex_int_status; /* 0x.018 - PCIE interrupt status */
	71	u8 res2[4];
9ac4dd30 ZR	72	__be32 pex_pme_mes_dr; /* 0x.020 - PCIE PME and message detect register */
	73	__be32 pex_pme_mes_disr; /* 0x.024 - PCIE PME and message disable register */
	74	__be32 pex_pme_mes_ier; /* 0x.028 - PCIE PME and message interrupt enable register */
	75	__be32 pex_pmcr; /* 0x.02c - PCIE power management command register */
6cc1b4e9 RZ	76	u8 res3[3016];
	77	__be32 block_rev1; /* 0x.bf8 - PCIE Block Revision register 1 */
	78	__be32 block_rev2; /* 0x.bfc - PCIE Block Revision register 2 */
9ac4dd30 ZR	79
	80	/* PCI/PCI Express outbound window 0-4
	81	* Window 0 is the default window and is the only window enabled upon reset.
	82	* The default outbound register set is used when a transaction misses
	83	* in all of the other outbound windows.
	84	*/
	85	struct pci_outbound_window_regs pow[5];
f4154e16 PK	86	u8 res14[96];
	87	struct pci_inbound_window_regs pmit; /* 0xd00 - 0xd9c Inbound MSI */
	88	u8 res6[96];
	89	/* PCI/PCI Express inbound window 3-0
9ac4dd30 ZR	90	* inbound window 1 supports only a 32-bit base address and does not
	91	* define an inbound window base extended address register.
	92	*/
f4154e16	93	struct pci_inbound_window_regs piw[4];
9ac4dd30 ZR	94
	95	__be32 pex_err_dr; /* 0x.e00 - PCI/PCIE error detect register */
	96	u8 res21[4];
	97	__be32 pex_err_en; /* 0x.e08 - PCI/PCIE error interrupt enable register */
	98	u8 res22[4];
	99	__be32 pex_err_disr; /* 0x.e10 - PCI/PCIE error disable register */
	100	u8 res23[12];
	101	__be32 pex_err_cap_stat; /* 0x.e20 - PCI/PCIE error capture status register */
	102	u8 res24[4];
	103	__be32 pex_err_cap_r0; /* 0x.e28 - PCIE error capture register 0 */
	104	__be32 pex_err_cap_r1; /* 0x.e2c - PCIE error capture register 0 */
	105	__be32 pex_err_cap_r2; /* 0x.e30 - PCIE error capture register 0 */
	106	__be32 pex_err_cap_r3; /* 0x.e34 - PCIE error capture register 0 */
cc6ea0dd RZ	107	u8 res_e38[200];
	108	__be32 pdb_stat; /* 0x.f00 - PCIE Debug Status */
	109	u8 res_f04[16];
	110	__be32 pex_csr0; /* 0x.f14 - PEX Control/Status register 0*/
	111	#define PEX_CSR0_LTSSM_MASK 0xFC
	112	#define PEX_CSR0_LTSSM_SHIFT 2
	113	#define PEX_CSR0_LTSSM_L0 0x11
	114	__be32 pex_csr1; /* 0x.f18 - PEX Control/Status register 1*/
	115	u8 res_f1c[228];
	116
9ac4dd30 ZR	117	};
9ac4dd30 ZR	118
52c5affc	119	extern int fsl_add_bridge(struct platform_device *pdev, int is_primary);
6c0a11c1	120	extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
48b16180	121	extern void fsl_pcibios_fixup_phb(struct pci_controller *phb);
76fe1ffc	122	extern int mpc83xx_add_bridge(struct device_node *dev);
b8f44ec2	123	u64 fsl_pci_immrbar_base(struct pci_controller *hose);
9ac4dd30	124
07e4f801 SW	125	extern struct device_node *fsl_pci_primary;
07e4f801 SW	126
905e75c4 JH	127	#ifdef CONFIG_PCI
905e75c4 JH	128	void fsl_pci_assign_primary(void);
07e4f801	129	#else
905e75c4 JH	130	static inline void fsl_pci_assign_primary(void) {}
	131	#endif
	132
4e0e3435 HJ	133	#ifdef CONFIG_FSL_PCI
	134	extern int fsl_pci_mcheck_exception(struct pt_regs *);
	135	#else
	136	static inline int fsl_pci_mcheck_exception(struct pt_regs *regs) {return 0; }
	137	#endif
	138
9ac4dd30	139	#endif /* __POWERPC_FSL_PCI_H */
9eb90a0c	140	#endif /* __KERNEL__ */