projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 9eb90a0c ZR |
1 | /* |
| 2 | * MPC85xx/86xx PCI Express structure define | |
| 3 | * | |
| f4154e16 | 4 | * Copyright 2007,2011 Freescale Semiconductor, Inc |
| 9eb90a0c ZR |
5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it | |
| 7 | * under the terms of the GNU General Public License as published by the | |
| 8 | * Free Software Foundation; either version 2 of the License, or (at your | |
| 9 | * option) any later version. | |
| 10 | * | |
| 11 | */ | |
| 12 | ||
| 13 | #ifdef __KERNEL__ | |
| 9ac4dd30 ZR |
14 | #ifndef __POWERPC_FSL_PCI_H |
| 15 | #define __POWERPC_FSL_PCI_H | |
| 9eb90a0c | 16 | |
| 9ac4dd30 ZR |
17 | #define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */ |
| 18 | #define PCIE_LTSSM_L0 0x16 /* L0 state */ | |
| 54c18193 KG |
19 | #define PIWAR_EN 0x80000000 /* Enable */ |
| 20 | #define PIWAR_PF 0x20000000 /* prefetch */ | |
| 21 | #define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */ | |
| 22 | #define PIWAR_READ_SNOOP 0x00050000 | |
| 23 | #define PIWAR_WRITE_SNOOP 0x00005000 | |
| f4154e16 | 24 | #define PIWAR_SZ_MASK 0x0000003f |
| 9eb90a0c | 25 | |
| 9ac4dd30 ZR |
26 | /* PCI/PCI Express outbound window reg */ |
| 27 | struct pci_outbound_window_regs { | |
| 28 | __be32 potar; /* 0x.0 - Outbound translation address register */ | |
| 29 | __be32 potear; /* 0x.4 - Outbound translation extended address register */ | |
| 30 | __be32 powbar; /* 0x.8 - Outbound window base address register */ | |
| 31 | u8 res1[4]; | |
| 32 | __be32 powar; /* 0x.10 - Outbound window attributes register */ | |
| 33 | u8 res2[12]; | |
| 9eb90a0c ZR |
34 | }; |
| 35 | ||
| 9ac4dd30 ZR |
36 | /* PCI/PCI Express inbound window reg */ |
| 37 | struct pci_inbound_window_regs { | |
| 38 | __be32 pitar; /* 0x.0 - Inbound translation address register */ | |
| 39 | u8 res1[4]; | |
| 40 | __be32 piwbar; /* 0x.8 - Inbound window base address register */ | |
| 41 | __be32 piwbear; /* 0x.c - Inbound window base extended address register */ | |
| 42 | __be32 piwar; /* 0x.10 - Inbound window attributes register */ | |
| 43 | u8 res2[12]; | |
| 44 | }; | |
| 45 | ||
| 46 | /* PCI/PCI Express IO block registers for 85xx/86xx */ | |
| 47 | struct ccsr_pci { | |
| 48 | __be32 config_addr; /* 0x.000 - PCI/PCIE Configuration Address Register */ | |
| 49 | __be32 config_data; /* 0x.004 - PCI/PCIE Configuration Data Register */ | |
| 50 | __be32 int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */ | |
| 51 | __be32 pex_otb_cpl_tor; /* 0x.00c - PCIE Outbound completion timeout register */ | |
| 52 | __be32 pex_conf_tor; /* 0x.010 - PCIE configuration timeout register */ | |
| f4154e16 PK |
53 | __be32 pex_config; /* 0x.014 - PCIE CONFIG Register */ |
| 54 | __be32 pex_int_status; /* 0x.018 - PCIE interrupt status */ | |
| 55 | u8 res2[4]; | |
| 9ac4dd30 ZR |
56 | __be32 pex_pme_mes_dr; /* 0x.020 - PCIE PME and message detect register */ |
| 57 | __be32 pex_pme_mes_disr; /* 0x.024 - PCIE PME and message disable register */ | |
| 58 | __be32 pex_pme_mes_ier; /* 0x.028 - PCIE PME and message interrupt enable register */ | |
| 59 | __be32 pex_pmcr; /* 0x.02c - PCIE power management command register */ | |
| 60 | u8 res3[3024]; | |
| 61 | ||
| 62 | /* PCI/PCI Express outbound window 0-4 | |
| 63 | * Window 0 is the default window and is the only window enabled upon reset. | |
| 64 | * The default outbound register set is used when a transaction misses | |
| 65 | * in all of the other outbound windows. | |
| 66 | */ | |
| 67 | struct pci_outbound_window_regs pow[5]; | |
| f4154e16 PK |
68 | u8 res14[96]; |
| 69 | struct pci_inbound_window_regs pmit; /* 0xd00 - 0xd9c Inbound MSI */ | |
| 70 | u8 res6[96]; | |
| 71 | /* PCI/PCI Express inbound window 3-0 | |
| 9ac4dd30 ZR |
72 | * inbound window 1 supports only a 32-bit base address and does not |
| 73 | * define an inbound window base extended address register. | |
| 74 | */ | |
| f4154e16 | 75 | struct pci_inbound_window_regs piw[4]; |
| 9ac4dd30 ZR |
76 | |
| 77 | __be32 pex_err_dr; /* 0x.e00 - PCI/PCIE error detect register */ | |
| 78 | u8 res21[4]; | |
| 79 | __be32 pex_err_en; /* 0x.e08 - PCI/PCIE error interrupt enable register */ | |
| 80 | u8 res22[4]; | |
| 81 | __be32 pex_err_disr; /* 0x.e10 - PCI/PCIE error disable register */ | |
| 82 | u8 res23[12]; | |
| 83 | __be32 pex_err_cap_stat; /* 0x.e20 - PCI/PCIE error capture status register */ | |
| 84 | u8 res24[4]; | |
| 85 | __be32 pex_err_cap_r0; /* 0x.e28 - PCIE error capture register 0 */ | |
| 86 | __be32 pex_err_cap_r1; /* 0x.e2c - PCIE error capture register 0 */ | |
| 87 | __be32 pex_err_cap_r2; /* 0x.e30 - PCIE error capture register 0 */ | |
| 88 | __be32 pex_err_cap_r3; /* 0x.e34 - PCIE error capture register 0 */ | |
| 89 | }; | |
| 90 | ||
| 91 | extern int fsl_add_bridge(struct device_node *dev, int is_primary); | |
| 6c0a11c1 | 92 | extern void fsl_pcibios_fixup_bus(struct pci_bus *bus); |
| 76fe1ffc | 93 | extern int mpc83xx_add_bridge(struct device_node *dev); |
| b8f44ec2 | 94 | u64 fsl_pci_immrbar_base(struct pci_controller *hose); |
| 9ac4dd30 ZR |
95 | |
| 96 | #endif /* __POWERPC_FSL_PCI_H */ | |
| 9eb90a0c | 97 | #endif /* __KERNEL__ */ |