Commit | Line | Data |
---|---|---|
f9bd170a PM |
1 | /* |
2 | * i8259 interrupt controller driver. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version | |
7 | * 2 of the License, or (at your option) any later version. | |
8 | */ | |
0ebfff14 BH |
9 | #undef DEBUG |
10 | ||
1da177e4 LT |
11 | #include <linux/ioport.h> |
12 | #include <linux/interrupt.h> | |
0ebfff14 BH |
13 | #include <linux/kernel.h> |
14 | #include <linux/delay.h> | |
1da177e4 LT |
15 | #include <asm/io.h> |
16 | #include <asm/i8259.h> | |
0ebfff14 | 17 | #include <asm/prom.h> |
1da177e4 | 18 | |
f9bd170a | 19 | static volatile void __iomem *pci_intack; /* RO, gives us the irq vector */ |
1da177e4 | 20 | |
f9bd170a | 21 | static unsigned char cached_8259[2] = { 0xff, 0xff }; |
1da177e4 LT |
22 | #define cached_A1 (cached_8259[0]) |
23 | #define cached_21 (cached_8259[1]) | |
24 | ||
47e3c904 | 25 | static DEFINE_RAW_SPINLOCK(i8259_lock); |
1da177e4 | 26 | |
bae1d8f1 | 27 | static struct irq_domain *i8259_host; |
1da177e4 LT |
28 | |
29 | /* | |
30 | * Acknowledge the IRQ using either the PCI host bridge's interrupt | |
31 | * acknowledge feature or poll. How i8259_init() is called determines | |
32 | * which is called. It should be noted that polling is broken on some | |
33 | * IBM and Motorola PReP boxes so we must use the int-ack feature on them. | |
34 | */ | |
35a84c2f | 35 | unsigned int i8259_irq(void) |
1da177e4 LT |
36 | { |
37 | int irq; | |
0ebfff14 | 38 | int lock = 0; |
1da177e4 LT |
39 | |
40 | /* Either int-ack or poll for the IRQ */ | |
41 | if (pci_intack) | |
f9bd170a | 42 | irq = readb(pci_intack); |
1da177e4 | 43 | else { |
47e3c904 | 44 | raw_spin_lock(&i8259_lock); |
0ebfff14 BH |
45 | lock = 1; |
46 | ||
1da177e4 LT |
47 | /* Perform an interrupt acknowledge cycle on controller 1. */ |
48 | outb(0x0C, 0x20); /* prepare for poll */ | |
49 | irq = inb(0x20) & 7; | |
50 | if (irq == 2 ) { | |
51 | /* | |
52 | * Interrupt is cascaded so perform interrupt | |
53 | * acknowledge on controller 2. | |
54 | */ | |
55 | outb(0x0C, 0xA0); /* prepare for poll */ | |
56 | irq = (inb(0xA0) & 7) + 8; | |
57 | } | |
58 | } | |
59 | ||
60 | if (irq == 7) { | |
61 | /* | |
62 | * This may be a spurious interrupt. | |
63 | * | |
64 | * Read the interrupt status register (ISR). If the most | |
65 | * significant bit is not set then there is no valid | |
66 | * interrupt. | |
67 | */ | |
68 | if (!pci_intack) | |
69 | outb(0x0B, 0x20); /* ISR register */ | |
70 | if(~inb(0x20) & 0x80) | |
0ebfff14 BH |
71 | irq = NO_IRQ; |
72 | } else if (irq == 0xff) | |
73 | irq = NO_IRQ; | |
1da177e4 | 74 | |
0ebfff14 | 75 | if (lock) |
47e3c904 | 76 | raw_spin_unlock(&i8259_lock); |
0ebfff14 | 77 | return irq; |
f9bd170a PM |
78 | } |
79 | ||
d4201184 | 80 | static void i8259_mask_and_ack_irq(struct irq_data *d) |
1da177e4 LT |
81 | { |
82 | unsigned long flags; | |
83 | ||
47e3c904 | 84 | raw_spin_lock_irqsave(&i8259_lock, flags); |
d4201184 LB |
85 | if (d->irq > 7) { |
86 | cached_A1 |= 1 << (d->irq-8); | |
f9bd170a PM |
87 | inb(0xA1); /* DUMMY */ |
88 | outb(cached_A1, 0xA1); | |
89 | outb(0x20, 0xA0); /* Non-specific EOI */ | |
90 | outb(0x20, 0x20); /* Non-specific EOI to cascade */ | |
1da177e4 | 91 | } else { |
d4201184 | 92 | cached_21 |= 1 << d->irq; |
f9bd170a PM |
93 | inb(0x21); /* DUMMY */ |
94 | outb(cached_21, 0x21); | |
95 | outb(0x20, 0x20); /* Non-specific EOI */ | |
1da177e4 | 96 | } |
47e3c904 | 97 | raw_spin_unlock_irqrestore(&i8259_lock, flags); |
1da177e4 LT |
98 | } |
99 | ||
100 | static void i8259_set_irq_mask(int irq_nr) | |
101 | { | |
102 | outb(cached_A1,0xA1); | |
103 | outb(cached_21,0x21); | |
104 | } | |
105 | ||
d4201184 | 106 | static void i8259_mask_irq(struct irq_data *d) |
1da177e4 LT |
107 | { |
108 | unsigned long flags; | |
109 | ||
d4201184 | 110 | pr_debug("i8259_mask_irq(%d)\n", d->irq); |
0ebfff14 | 111 | |
47e3c904 | 112 | raw_spin_lock_irqsave(&i8259_lock, flags); |
d4201184 LB |
113 | if (d->irq < 8) |
114 | cached_21 |= 1 << d->irq; | |
1da177e4 | 115 | else |
d4201184 LB |
116 | cached_A1 |= 1 << (d->irq-8); |
117 | i8259_set_irq_mask(d->irq); | |
47e3c904 | 118 | raw_spin_unlock_irqrestore(&i8259_lock, flags); |
1da177e4 LT |
119 | } |
120 | ||
d4201184 | 121 | static void i8259_unmask_irq(struct irq_data *d) |
1da177e4 LT |
122 | { |
123 | unsigned long flags; | |
124 | ||
d4201184 | 125 | pr_debug("i8259_unmask_irq(%d)\n", d->irq); |
0ebfff14 | 126 | |
47e3c904 | 127 | raw_spin_lock_irqsave(&i8259_lock, flags); |
d4201184 LB |
128 | if (d->irq < 8) |
129 | cached_21 &= ~(1 << d->irq); | |
1da177e4 | 130 | else |
d4201184 LB |
131 | cached_A1 &= ~(1 << (d->irq-8)); |
132 | i8259_set_irq_mask(d->irq); | |
47e3c904 | 133 | raw_spin_unlock_irqrestore(&i8259_lock, flags); |
1da177e4 LT |
134 | } |
135 | ||
b9e5b4e6 | 136 | static struct irq_chip i8259_pic = { |
fc380c0c | 137 | .name = "i8259", |
d4201184 LB |
138 | .irq_mask = i8259_mask_irq, |
139 | .irq_disable = i8259_mask_irq, | |
140 | .irq_unmask = i8259_unmask_irq, | |
141 | .irq_mask_ack = i8259_mask_and_ack_irq, | |
1da177e4 LT |
142 | }; |
143 | ||
144 | static struct resource pic1_iores = { | |
145 | .name = "8259 (master)", | |
146 | .start = 0x20, | |
147 | .end = 0x21, | |
148 | .flags = IORESOURCE_BUSY, | |
149 | }; | |
150 | ||
151 | static struct resource pic2_iores = { | |
152 | .name = "8259 (slave)", | |
153 | .start = 0xa0, | |
154 | .end = 0xa1, | |
155 | .flags = IORESOURCE_BUSY, | |
156 | }; | |
157 | ||
158 | static struct resource pic_edgectrl_iores = { | |
159 | .name = "8259 edge control", | |
160 | .start = 0x4d0, | |
161 | .end = 0x4d1, | |
162 | .flags = IORESOURCE_BUSY, | |
163 | }; | |
164 | ||
ad3aedfb MZ |
165 | static int i8259_host_match(struct irq_domain *h, struct device_node *node, |
166 | enum irq_domain_bus_token bus_token) | |
0ebfff14 | 167 | { |
5d4c9bc7 MZ |
168 | struct device_node *of_node = irq_domain_get_of_node(h); |
169 | return of_node == NULL || of_node == node; | |
0ebfff14 BH |
170 | } |
171 | ||
bae1d8f1 | 172 | static int i8259_host_map(struct irq_domain *h, unsigned int virq, |
6e99e458 | 173 | irq_hw_number_t hw) |
0ebfff14 BH |
174 | { |
175 | pr_debug("i8259_host_map(%d, 0x%lx)\n", virq, hw); | |
176 | ||
177 | /* We block the internal cascade */ | |
178 | if (hw == 2) | |
98488db9 | 179 | irq_set_status_flags(virq, IRQ_NOREQUEST); |
0ebfff14 | 180 | |
6e99e458 | 181 | /* We use the level handler only for now, we might want to |
0ebfff14 BH |
182 | * be more cautious here but that works for now |
183 | */ | |
98488db9 | 184 | irq_set_status_flags(virq, IRQ_LEVEL); |
ec775d0e | 185 | irq_set_chip_and_handler(virq, &i8259_pic, handle_level_irq); |
0ebfff14 BH |
186 | return 0; |
187 | } | |
188 | ||
bae1d8f1 | 189 | static int i8259_host_xlate(struct irq_domain *h, struct device_node *ct, |
40d50cf7 | 190 | const u32 *intspec, unsigned int intsize, |
0ebfff14 BH |
191 | irq_hw_number_t *out_hwirq, unsigned int *out_flags) |
192 | { | |
193 | static unsigned char map_isa_senses[4] = { | |
194 | IRQ_TYPE_LEVEL_LOW, | |
195 | IRQ_TYPE_LEVEL_HIGH, | |
196 | IRQ_TYPE_EDGE_FALLING, | |
197 | IRQ_TYPE_EDGE_RISING, | |
198 | }; | |
199 | ||
200 | *out_hwirq = intspec[0]; | |
201 | if (intsize > 1 && intspec[1] < 4) | |
202 | *out_flags = map_isa_senses[intspec[1]]; | |
203 | else | |
204 | *out_flags = IRQ_TYPE_NONE; | |
205 | ||
206 | return 0; | |
207 | } | |
208 | ||
202648a6 | 209 | static const struct irq_domain_ops i8259_host_ops = { |
0ebfff14 BH |
210 | .match = i8259_host_match, |
211 | .map = i8259_host_map, | |
0ebfff14 | 212 | .xlate = i8259_host_xlate, |
1da177e4 LT |
213 | }; |
214 | ||
bae1d8f1 | 215 | struct irq_domain *i8259_get_host(void) |
f4d4c354 BH |
216 | { |
217 | return i8259_host; | |
218 | } | |
219 | ||
40681b95 | 220 | /** |
0ebfff14 BH |
221 | * i8259_init - Initialize the legacy controller |
222 | * @node: device node of the legacy PIC (can be NULL, but then, it will match | |
223 | * all interrupts, so beware) | |
224 | * @intack_addr: PCI interrupt acknowledge (real) address which will return | |
225 | * the active irq from the 8259 | |
1da177e4 | 226 | */ |
0ebfff14 | 227 | void i8259_init(struct device_node *node, unsigned long intack_addr) |
1da177e4 LT |
228 | { |
229 | unsigned long flags; | |
230 | ||
0ebfff14 | 231 | /* initialize the controller */ |
47e3c904 | 232 | raw_spin_lock_irqsave(&i8259_lock, flags); |
0ebfff14 BH |
233 | |
234 | /* Mask all first */ | |
235 | outb(0xff, 0xA1); | |
236 | outb(0xff, 0x21); | |
f9bd170a | 237 | |
1da177e4 LT |
238 | /* init master interrupt controller */ |
239 | outb(0x11, 0x20); /* Start init sequence */ | |
240 | outb(0x00, 0x21); /* Vector base */ | |
446957ba | 241 | outb(0x04, 0x21); /* edge triggered, Cascade (slave) on IRQ2 */ |
1da177e4 LT |
242 | outb(0x01, 0x21); /* Select 8086 mode */ |
243 | ||
244 | /* init slave interrupt controller */ | |
245 | outb(0x11, 0xA0); /* Start init sequence */ | |
246 | outb(0x08, 0xA1); /* Vector base */ | |
247 | outb(0x02, 0xA1); /* edge triggered, Cascade (slave) on IRQ2 */ | |
248 | outb(0x01, 0xA1); /* Select 8086 mode */ | |
249 | ||
0ebfff14 BH |
250 | /* That thing is slow */ |
251 | udelay(100); | |
252 | ||
1da177e4 LT |
253 | /* always read ISR */ |
254 | outb(0x0B, 0x20); | |
255 | outb(0x0B, 0xA0); | |
256 | ||
0ebfff14 BH |
257 | /* Unmask the internal cascade */ |
258 | cached_21 &= ~(1 << 2); | |
259 | ||
260 | /* Set interrupt masks */ | |
1da177e4 LT |
261 | outb(cached_A1, 0xA1); |
262 | outb(cached_21, 0x21); | |
263 | ||
47e3c904 | 264 | raw_spin_unlock_irqrestore(&i8259_lock, flags); |
1da177e4 | 265 | |
0ebfff14 | 266 | /* create a legacy host */ |
1bc04f2c | 267 | i8259_host = irq_domain_add_legacy_isa(node, &i8259_host_ops, NULL); |
0ebfff14 BH |
268 | if (i8259_host == NULL) { |
269 | printk(KERN_ERR "i8259: failed to allocate irq host !\n"); | |
270 | return; | |
b9e5b4e6 | 271 | } |
9d2ba6fa | 272 | |
1da177e4 | 273 | /* reserve our resources */ |
0ebfff14 BH |
274 | /* XXX should we continue doing that ? it seems to cause problems |
275 | * with further requesting of PCI IO resources for that range... | |
276 | * need to look into it. | |
277 | */ | |
1da177e4 LT |
278 | request_resource(&ioport_resource, &pic1_iores); |
279 | request_resource(&ioport_resource, &pic2_iores); | |
280 | request_resource(&ioport_resource, &pic_edgectrl_iores); | |
281 | ||
282 | if (intack_addr != 0) | |
283 | pci_intack = ioremap(intack_addr, 1); | |
f9bd170a | 284 | |
0ebfff14 | 285 | printk(KERN_INFO "i8259 legacy interrupt controller initialized\n"); |
1da177e4 | 286 | } |