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daec962e PM |
1 | /* |
2 | * Support for indirect PCI bridges. | |
3 | * | |
4 | * Copyright (C) 1998 Gabriel Paubert. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/pci.h> | |
14 | #include <linux/delay.h> | |
15 | #include <linux/string.h> | |
16 | #include <linux/init.h> | |
17 | ||
18 | #include <asm/io.h> | |
19 | #include <asm/prom.h> | |
20 | #include <asm/pci-bridge.h> | |
21 | #include <asm/machdep.h> | |
22 | ||
6d5f6a0e KP |
23 | int __indirect_read_config(struct pci_controller *hose, |
24 | unsigned char bus_number, unsigned int devfn, | |
25 | int offset, int len, u32 *val) | |
daec962e | 26 | { |
daec962e PM |
27 | volatile void __iomem *cfg_data; |
28 | u8 cfg_type = 0; | |
ab0f9ad3 | 29 | u32 bus_no, reg; |
daec962e | 30 | |
62c66c8e | 31 | if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) { |
6d5f6a0e | 32 | if (bus_number != hose->first_busno) |
62c66c8e KG |
33 | return PCIBIOS_DEVICE_NOT_FOUND; |
34 | if (devfn != 0) | |
35 | return PCIBIOS_DEVICE_NOT_FOUND; | |
36 | } | |
37 | ||
daec962e | 38 | if (ppc_md.pci_exclude_device) |
6d5f6a0e | 39 | if (ppc_md.pci_exclude_device(hose, bus_number, devfn)) |
daec962e | 40 | return PCIBIOS_DEVICE_NOT_FOUND; |
62c66c8e | 41 | |
ab0f9ad3 | 42 | if (hose->indirect_type & PPC_INDIRECT_TYPE_SET_CFG_TYPE) |
6d5f6a0e | 43 | if (bus_number != hose->first_busno) |
daec962e PM |
44 | cfg_type = 1; |
45 | ||
6d5f6a0e KP |
46 | bus_no = (bus_number == hose->first_busno) ? |
47 | hose->self_busno : bus_number; | |
5ab65ecd | 48 | |
ab0f9ad3 KG |
49 | if (hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG) |
50 | reg = ((offset & 0xf00) << 16) | (offset & 0xfc); | |
51 | else | |
52 | reg = offset & 0xfc; | |
53 | ||
2e56ff20 KG |
54 | if (hose->indirect_type & PPC_INDIRECT_TYPE_BIG_ENDIAN) |
55 | out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) | | |
56 | (devfn << 8) | reg | cfg_type)); | |
57 | else | |
58 | out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) | | |
59 | (devfn << 8) | reg | cfg_type)); | |
daec962e PM |
60 | |
61 | /* | |
62 | * Note: the caller has already checked that offset is | |
63 | * suitably aligned and that len is 1, 2 or 4. | |
64 | */ | |
65 | cfg_data = hose->cfg_data + (offset & 3); | |
66 | switch (len) { | |
67 | case 1: | |
68 | *val = in_8(cfg_data); | |
69 | break; | |
70 | case 2: | |
71 | *val = in_le16(cfg_data); | |
72 | break; | |
73 | default: | |
74 | *val = in_le32(cfg_data); | |
75 | break; | |
76 | } | |
77 | return PCIBIOS_SUCCESSFUL; | |
78 | } | |
79 | ||
6d5f6a0e KP |
80 | int indirect_read_config(struct pci_bus *bus, unsigned int devfn, |
81 | int offset, int len, u32 *val) | |
82 | { | |
83 | struct pci_controller *hose = pci_bus_to_host(bus); | |
84 | ||
85 | return __indirect_read_config(hose, bus->number, devfn, offset, len, | |
86 | val); | |
87 | } | |
88 | ||
50d8f87d RI |
89 | int indirect_write_config(struct pci_bus *bus, unsigned int devfn, |
90 | int offset, int len, u32 val) | |
daec962e | 91 | { |
19afa407 | 92 | struct pci_controller *hose = pci_bus_to_host(bus); |
daec962e PM |
93 | volatile void __iomem *cfg_data; |
94 | u8 cfg_type = 0; | |
ab0f9ad3 | 95 | u32 bus_no, reg; |
daec962e | 96 | |
62c66c8e KG |
97 | if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) { |
98 | if (bus->number != hose->first_busno) | |
99 | return PCIBIOS_DEVICE_NOT_FOUND; | |
100 | if (devfn != 0) | |
101 | return PCIBIOS_DEVICE_NOT_FOUND; | |
102 | } | |
103 | ||
daec962e | 104 | if (ppc_md.pci_exclude_device) |
7d52c7b0 | 105 | if (ppc_md.pci_exclude_device(hose, bus->number, devfn)) |
daec962e PM |
106 | return PCIBIOS_DEVICE_NOT_FOUND; |
107 | ||
ab0f9ad3 | 108 | if (hose->indirect_type & PPC_INDIRECT_TYPE_SET_CFG_TYPE) |
daec962e PM |
109 | if (bus->number != hose->first_busno) |
110 | cfg_type = 1; | |
111 | ||
5ab65ecd | 112 | bus_no = (bus->number == hose->first_busno) ? |
0a3786c5 | 113 | hose->self_busno : bus->number; |
5ab65ecd | 114 | |
ab0f9ad3 KG |
115 | if (hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG) |
116 | reg = ((offset & 0xf00) << 16) | (offset & 0xfc); | |
117 | else | |
118 | reg = offset & 0xfc; | |
119 | ||
2e56ff20 KG |
120 | if (hose->indirect_type & PPC_INDIRECT_TYPE_BIG_ENDIAN) |
121 | out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) | | |
122 | (devfn << 8) | reg | cfg_type)); | |
123 | else | |
124 | out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) | | |
125 | (devfn << 8) | reg | cfg_type)); | |
daec962e | 126 | |
25985edc | 127 | /* suppress setting of PCI_PRIMARY_BUS */ |
476f5779 KG |
128 | if (hose->indirect_type & PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS) |
129 | if ((offset == PCI_PRIMARY_BUS) && | |
130 | (bus->number == hose->first_busno)) | |
131 | val &= 0xffffff00; | |
132 | ||
5ce4b596 JB |
133 | /* Workaround for PCI_28 Errata in 440EPx/GRx */ |
134 | if ((hose->indirect_type & PPC_INDIRECT_TYPE_BROKEN_MRM) && | |
135 | offset == PCI_CACHE_LINE_SIZE) { | |
136 | val = 0; | |
137 | } | |
138 | ||
daec962e PM |
139 | /* |
140 | * Note: the caller has already checked that offset is | |
141 | * suitably aligned and that len is 1, 2 or 4. | |
142 | */ | |
143 | cfg_data = hose->cfg_data + (offset & 3); | |
144 | switch (len) { | |
145 | case 1: | |
146 | out_8(cfg_data, val); | |
147 | break; | |
148 | case 2: | |
149 | out_le16(cfg_data, val); | |
150 | break; | |
151 | default: | |
152 | out_le32(cfg_data, val); | |
153 | break; | |
154 | } | |
155 | return PCIBIOS_SUCCESSFUL; | |
156 | } | |
157 | ||
158 | static struct pci_ops indirect_pci_ops = | |
159 | { | |
c78d453b NL |
160 | .read = indirect_read_config, |
161 | .write = indirect_write_config, | |
daec962e PM |
162 | }; |
163 | ||
1e83bf87 CE |
164 | void setup_indirect_pci(struct pci_controller *hose, resource_size_t cfg_addr, |
165 | resource_size_t cfg_data, u32 flags) | |
daec962e | 166 | { |
d94bad82 | 167 | resource_size_t base = cfg_addr & PAGE_MASK; |
d5269966 | 168 | void __iomem *mbase; |
daec962e PM |
169 | |
170 | mbase = ioremap(base, PAGE_SIZE); | |
d5269966 | 171 | hose->cfg_addr = mbase + (cfg_addr & ~PAGE_MASK); |
daec962e PM |
172 | if ((cfg_data & PAGE_MASK) != base) |
173 | mbase = ioremap(cfg_data & PAGE_MASK, PAGE_SIZE); | |
d5269966 KG |
174 | hose->cfg_data = mbase + (cfg_data & ~PAGE_MASK); |
175 | hose->ops = &indirect_pci_ops; | |
7659c038 | 176 | hose->indirect_type = flags; |
daec962e | 177 | } |