Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
f30c2269 | 2 | * arch/powerpc/sysdev/ipic.c |
1da177e4 LT |
3 | * |
4 | * IPIC routines implementations. | |
5 | * | |
6 | * Copyright 2005 Freescale Semiconductor, Inc. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | */ | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/errno.h> | |
16 | #include <linux/reboot.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/stddef.h> | |
19 | #include <linux/sched.h> | |
20 | #include <linux/signal.h> | |
21 | #include <linux/sysdev.h> | |
b9f0f1bb KP |
22 | #include <linux/device.h> |
23 | #include <linux/bootmem.h> | |
24 | #include <linux/spinlock.h> | |
d49747bd | 25 | #include <linux/fsl_devices.h> |
1da177e4 LT |
26 | #include <asm/irq.h> |
27 | #include <asm/io.h> | |
b9f0f1bb | 28 | #include <asm/prom.h> |
1da177e4 | 29 | #include <asm/ipic.h> |
1da177e4 LT |
30 | |
31 | #include "ipic.h" | |
32 | ||
1da177e4 | 33 | static struct ipic * primary_ipic; |
77d4309e | 34 | static struct irq_chip ipic_level_irq_chip, ipic_edge_irq_chip; |
a9e8bf21 | 35 | static DEFINE_RAW_SPINLOCK(ipic_lock); |
1da177e4 LT |
36 | |
37 | static struct ipic_info ipic_info[] = { | |
f03ca957 | 38 | [1] = { |
f03ca957 LY |
39 | .mask = IPIC_SIMSR_H, |
40 | .prio = IPIC_SIPRR_C, | |
41 | .force = IPIC_SIFCR_H, | |
42 | .bit = 16, | |
43 | .prio_mask = 0, | |
44 | }, | |
45 | [2] = { | |
f03ca957 LY |
46 | .mask = IPIC_SIMSR_H, |
47 | .prio = IPIC_SIPRR_C, | |
48 | .force = IPIC_SIFCR_H, | |
49 | .bit = 17, | |
50 | .prio_mask = 1, | |
51 | }, | |
a7267d67 JR |
52 | [3] = { |
53 | .mask = IPIC_SIMSR_H, | |
54 | .prio = IPIC_SIPRR_C, | |
55 | .force = IPIC_SIFCR_H, | |
56 | .bit = 18, | |
57 | .prio_mask = 2, | |
58 | }, | |
f03ca957 | 59 | [4] = { |
f03ca957 LY |
60 | .mask = IPIC_SIMSR_H, |
61 | .prio = IPIC_SIPRR_C, | |
62 | .force = IPIC_SIFCR_H, | |
63 | .bit = 19, | |
64 | .prio_mask = 3, | |
65 | }, | |
a7267d67 JR |
66 | [5] = { |
67 | .mask = IPIC_SIMSR_H, | |
68 | .prio = IPIC_SIPRR_C, | |
69 | .force = IPIC_SIFCR_H, | |
70 | .bit = 20, | |
71 | .prio_mask = 4, | |
72 | }, | |
73 | [6] = { | |
74 | .mask = IPIC_SIMSR_H, | |
75 | .prio = IPIC_SIPRR_C, | |
76 | .force = IPIC_SIFCR_H, | |
77 | .bit = 21, | |
78 | .prio_mask = 5, | |
79 | }, | |
80 | [7] = { | |
81 | .mask = IPIC_SIMSR_H, | |
82 | .prio = IPIC_SIPRR_C, | |
83 | .force = IPIC_SIFCR_H, | |
84 | .bit = 22, | |
85 | .prio_mask = 6, | |
86 | }, | |
87 | [8] = { | |
88 | .mask = IPIC_SIMSR_H, | |
89 | .prio = IPIC_SIPRR_C, | |
90 | .force = IPIC_SIFCR_H, | |
91 | .bit = 23, | |
92 | .prio_mask = 7, | |
93 | }, | |
1da177e4 | 94 | [9] = { |
1da177e4 LT |
95 | .mask = IPIC_SIMSR_H, |
96 | .prio = IPIC_SIPRR_D, | |
97 | .force = IPIC_SIFCR_H, | |
98 | .bit = 24, | |
99 | .prio_mask = 0, | |
100 | }, | |
101 | [10] = { | |
1da177e4 LT |
102 | .mask = IPIC_SIMSR_H, |
103 | .prio = IPIC_SIPRR_D, | |
104 | .force = IPIC_SIFCR_H, | |
105 | .bit = 25, | |
106 | .prio_mask = 1, | |
107 | }, | |
108 | [11] = { | |
1da177e4 LT |
109 | .mask = IPIC_SIMSR_H, |
110 | .prio = IPIC_SIPRR_D, | |
111 | .force = IPIC_SIFCR_H, | |
112 | .bit = 26, | |
113 | .prio_mask = 2, | |
114 | }, | |
f03ca957 | 115 | [12] = { |
f03ca957 LY |
116 | .mask = IPIC_SIMSR_H, |
117 | .prio = IPIC_SIPRR_D, | |
118 | .force = IPIC_SIFCR_H, | |
119 | .bit = 27, | |
120 | .prio_mask = 3, | |
121 | }, | |
122 | [13] = { | |
f03ca957 LY |
123 | .mask = IPIC_SIMSR_H, |
124 | .prio = IPIC_SIPRR_D, | |
125 | .force = IPIC_SIFCR_H, | |
126 | .bit = 28, | |
127 | .prio_mask = 4, | |
128 | }, | |
1da177e4 | 129 | [14] = { |
1da177e4 LT |
130 | .mask = IPIC_SIMSR_H, |
131 | .prio = IPIC_SIPRR_D, | |
132 | .force = IPIC_SIFCR_H, | |
133 | .bit = 29, | |
134 | .prio_mask = 5, | |
135 | }, | |
136 | [15] = { | |
1da177e4 LT |
137 | .mask = IPIC_SIMSR_H, |
138 | .prio = IPIC_SIPRR_D, | |
139 | .force = IPIC_SIFCR_H, | |
140 | .bit = 30, | |
141 | .prio_mask = 6, | |
142 | }, | |
143 | [16] = { | |
1da177e4 LT |
144 | .mask = IPIC_SIMSR_H, |
145 | .prio = IPIC_SIPRR_D, | |
146 | .force = IPIC_SIFCR_H, | |
147 | .bit = 31, | |
148 | .prio_mask = 7, | |
149 | }, | |
150 | [17] = { | |
77d4309e | 151 | .ack = IPIC_SEPNR, |
1da177e4 LT |
152 | .mask = IPIC_SEMSR, |
153 | .prio = IPIC_SMPRR_A, | |
154 | .force = IPIC_SEFCR, | |
155 | .bit = 1, | |
156 | .prio_mask = 5, | |
157 | }, | |
158 | [18] = { | |
77d4309e | 159 | .ack = IPIC_SEPNR, |
1da177e4 LT |
160 | .mask = IPIC_SEMSR, |
161 | .prio = IPIC_SMPRR_A, | |
162 | .force = IPIC_SEFCR, | |
163 | .bit = 2, | |
164 | .prio_mask = 6, | |
165 | }, | |
166 | [19] = { | |
77d4309e | 167 | .ack = IPIC_SEPNR, |
1da177e4 LT |
168 | .mask = IPIC_SEMSR, |
169 | .prio = IPIC_SMPRR_A, | |
170 | .force = IPIC_SEFCR, | |
171 | .bit = 3, | |
172 | .prio_mask = 7, | |
173 | }, | |
174 | [20] = { | |
77d4309e | 175 | .ack = IPIC_SEPNR, |
1da177e4 LT |
176 | .mask = IPIC_SEMSR, |
177 | .prio = IPIC_SMPRR_B, | |
178 | .force = IPIC_SEFCR, | |
179 | .bit = 4, | |
180 | .prio_mask = 4, | |
181 | }, | |
182 | [21] = { | |
77d4309e | 183 | .ack = IPIC_SEPNR, |
1da177e4 LT |
184 | .mask = IPIC_SEMSR, |
185 | .prio = IPIC_SMPRR_B, | |
186 | .force = IPIC_SEFCR, | |
187 | .bit = 5, | |
188 | .prio_mask = 5, | |
189 | }, | |
190 | [22] = { | |
77d4309e | 191 | .ack = IPIC_SEPNR, |
1da177e4 LT |
192 | .mask = IPIC_SEMSR, |
193 | .prio = IPIC_SMPRR_B, | |
194 | .force = IPIC_SEFCR, | |
195 | .bit = 6, | |
196 | .prio_mask = 6, | |
197 | }, | |
198 | [23] = { | |
77d4309e | 199 | .ack = IPIC_SEPNR, |
1da177e4 LT |
200 | .mask = IPIC_SEMSR, |
201 | .prio = IPIC_SMPRR_B, | |
202 | .force = IPIC_SEFCR, | |
203 | .bit = 7, | |
204 | .prio_mask = 7, | |
205 | }, | |
206 | [32] = { | |
1da177e4 LT |
207 | .mask = IPIC_SIMSR_H, |
208 | .prio = IPIC_SIPRR_A, | |
209 | .force = IPIC_SIFCR_H, | |
210 | .bit = 0, | |
211 | .prio_mask = 0, | |
212 | }, | |
213 | [33] = { | |
1da177e4 LT |
214 | .mask = IPIC_SIMSR_H, |
215 | .prio = IPIC_SIPRR_A, | |
216 | .force = IPIC_SIFCR_H, | |
217 | .bit = 1, | |
218 | .prio_mask = 1, | |
219 | }, | |
220 | [34] = { | |
1da177e4 LT |
221 | .mask = IPIC_SIMSR_H, |
222 | .prio = IPIC_SIPRR_A, | |
223 | .force = IPIC_SIFCR_H, | |
224 | .bit = 2, | |
225 | .prio_mask = 2, | |
226 | }, | |
227 | [35] = { | |
1da177e4 LT |
228 | .mask = IPIC_SIMSR_H, |
229 | .prio = IPIC_SIPRR_A, | |
230 | .force = IPIC_SIFCR_H, | |
231 | .bit = 3, | |
232 | .prio_mask = 3, | |
233 | }, | |
234 | [36] = { | |
1da177e4 LT |
235 | .mask = IPIC_SIMSR_H, |
236 | .prio = IPIC_SIPRR_A, | |
237 | .force = IPIC_SIFCR_H, | |
238 | .bit = 4, | |
239 | .prio_mask = 4, | |
240 | }, | |
241 | [37] = { | |
1da177e4 LT |
242 | .mask = IPIC_SIMSR_H, |
243 | .prio = IPIC_SIPRR_A, | |
244 | .force = IPIC_SIFCR_H, | |
245 | .bit = 5, | |
246 | .prio_mask = 5, | |
247 | }, | |
248 | [38] = { | |
1da177e4 LT |
249 | .mask = IPIC_SIMSR_H, |
250 | .prio = IPIC_SIPRR_A, | |
251 | .force = IPIC_SIFCR_H, | |
252 | .bit = 6, | |
253 | .prio_mask = 6, | |
254 | }, | |
255 | [39] = { | |
1da177e4 LT |
256 | .mask = IPIC_SIMSR_H, |
257 | .prio = IPIC_SIPRR_A, | |
258 | .force = IPIC_SIFCR_H, | |
259 | .bit = 7, | |
260 | .prio_mask = 7, | |
261 | }, | |
a7267d67 JR |
262 | [40] = { |
263 | .mask = IPIC_SIMSR_H, | |
264 | .prio = IPIC_SIPRR_B, | |
265 | .force = IPIC_SIFCR_H, | |
266 | .bit = 8, | |
267 | .prio_mask = 0, | |
268 | }, | |
269 | [41] = { | |
270 | .mask = IPIC_SIMSR_H, | |
271 | .prio = IPIC_SIPRR_B, | |
272 | .force = IPIC_SIFCR_H, | |
273 | .bit = 9, | |
274 | .prio_mask = 1, | |
275 | }, | |
f03ca957 | 276 | [42] = { |
f03ca957 LY |
277 | .mask = IPIC_SIMSR_H, |
278 | .prio = IPIC_SIPRR_B, | |
279 | .force = IPIC_SIFCR_H, | |
280 | .bit = 10, | |
281 | .prio_mask = 2, | |
282 | }, | |
a7267d67 JR |
283 | [43] = { |
284 | .mask = IPIC_SIMSR_H, | |
285 | .prio = IPIC_SIPRR_B, | |
286 | .force = IPIC_SIFCR_H, | |
287 | .bit = 11, | |
288 | .prio_mask = 3, | |
289 | }, | |
f03ca957 | 290 | [44] = { |
f03ca957 LY |
291 | .mask = IPIC_SIMSR_H, |
292 | .prio = IPIC_SIPRR_B, | |
293 | .force = IPIC_SIFCR_H, | |
294 | .bit = 12, | |
295 | .prio_mask = 4, | |
296 | }, | |
297 | [45] = { | |
f03ca957 LY |
298 | .mask = IPIC_SIMSR_H, |
299 | .prio = IPIC_SIPRR_B, | |
300 | .force = IPIC_SIFCR_H, | |
301 | .bit = 13, | |
302 | .prio_mask = 5, | |
303 | }, | |
304 | [46] = { | |
f03ca957 LY |
305 | .mask = IPIC_SIMSR_H, |
306 | .prio = IPIC_SIPRR_B, | |
307 | .force = IPIC_SIFCR_H, | |
308 | .bit = 14, | |
309 | .prio_mask = 6, | |
310 | }, | |
311 | [47] = { | |
f03ca957 LY |
312 | .mask = IPIC_SIMSR_H, |
313 | .prio = IPIC_SIPRR_B, | |
314 | .force = IPIC_SIFCR_H, | |
315 | .bit = 15, | |
316 | .prio_mask = 7, | |
317 | }, | |
1da177e4 | 318 | [48] = { |
1da177e4 LT |
319 | .mask = IPIC_SEMSR, |
320 | .prio = IPIC_SMPRR_A, | |
321 | .force = IPIC_SEFCR, | |
322 | .bit = 0, | |
323 | .prio_mask = 4, | |
324 | }, | |
325 | [64] = { | |
1da177e4 LT |
326 | .mask = IPIC_SIMSR_L, |
327 | .prio = IPIC_SMPRR_A, | |
328 | .force = IPIC_SIFCR_L, | |
329 | .bit = 0, | |
330 | .prio_mask = 0, | |
331 | }, | |
332 | [65] = { | |
1da177e4 LT |
333 | .mask = IPIC_SIMSR_L, |
334 | .prio = IPIC_SMPRR_A, | |
335 | .force = IPIC_SIFCR_L, | |
336 | .bit = 1, | |
337 | .prio_mask = 1, | |
338 | }, | |
339 | [66] = { | |
1da177e4 LT |
340 | .mask = IPIC_SIMSR_L, |
341 | .prio = IPIC_SMPRR_A, | |
342 | .force = IPIC_SIFCR_L, | |
343 | .bit = 2, | |
344 | .prio_mask = 2, | |
345 | }, | |
346 | [67] = { | |
1da177e4 LT |
347 | .mask = IPIC_SIMSR_L, |
348 | .prio = IPIC_SMPRR_A, | |
349 | .force = IPIC_SIFCR_L, | |
350 | .bit = 3, | |
351 | .prio_mask = 3, | |
352 | }, | |
353 | [68] = { | |
1da177e4 LT |
354 | .mask = IPIC_SIMSR_L, |
355 | .prio = IPIC_SMPRR_B, | |
356 | .force = IPIC_SIFCR_L, | |
357 | .bit = 4, | |
358 | .prio_mask = 0, | |
359 | }, | |
360 | [69] = { | |
1da177e4 LT |
361 | .mask = IPIC_SIMSR_L, |
362 | .prio = IPIC_SMPRR_B, | |
363 | .force = IPIC_SIFCR_L, | |
364 | .bit = 5, | |
365 | .prio_mask = 1, | |
366 | }, | |
367 | [70] = { | |
1da177e4 LT |
368 | .mask = IPIC_SIMSR_L, |
369 | .prio = IPIC_SMPRR_B, | |
370 | .force = IPIC_SIFCR_L, | |
371 | .bit = 6, | |
372 | .prio_mask = 2, | |
373 | }, | |
374 | [71] = { | |
1da177e4 LT |
375 | .mask = IPIC_SIMSR_L, |
376 | .prio = IPIC_SMPRR_B, | |
377 | .force = IPIC_SIFCR_L, | |
378 | .bit = 7, | |
379 | .prio_mask = 3, | |
380 | }, | |
381 | [72] = { | |
1da177e4 LT |
382 | .mask = IPIC_SIMSR_L, |
383 | .prio = 0, | |
384 | .force = IPIC_SIFCR_L, | |
385 | .bit = 8, | |
386 | }, | |
387 | [73] = { | |
1da177e4 LT |
388 | .mask = IPIC_SIMSR_L, |
389 | .prio = 0, | |
390 | .force = IPIC_SIFCR_L, | |
391 | .bit = 9, | |
392 | }, | |
393 | [74] = { | |
1da177e4 LT |
394 | .mask = IPIC_SIMSR_L, |
395 | .prio = 0, | |
396 | .force = IPIC_SIFCR_L, | |
397 | .bit = 10, | |
398 | }, | |
399 | [75] = { | |
1da177e4 LT |
400 | .mask = IPIC_SIMSR_L, |
401 | .prio = 0, | |
402 | .force = IPIC_SIFCR_L, | |
403 | .bit = 11, | |
404 | }, | |
405 | [76] = { | |
1da177e4 LT |
406 | .mask = IPIC_SIMSR_L, |
407 | .prio = 0, | |
408 | .force = IPIC_SIFCR_L, | |
409 | .bit = 12, | |
410 | }, | |
411 | [77] = { | |
1da177e4 LT |
412 | .mask = IPIC_SIMSR_L, |
413 | .prio = 0, | |
414 | .force = IPIC_SIFCR_L, | |
415 | .bit = 13, | |
416 | }, | |
417 | [78] = { | |
1da177e4 LT |
418 | .mask = IPIC_SIMSR_L, |
419 | .prio = 0, | |
420 | .force = IPIC_SIFCR_L, | |
421 | .bit = 14, | |
422 | }, | |
423 | [79] = { | |
1da177e4 LT |
424 | .mask = IPIC_SIMSR_L, |
425 | .prio = 0, | |
426 | .force = IPIC_SIFCR_L, | |
427 | .bit = 15, | |
428 | }, | |
429 | [80] = { | |
1da177e4 LT |
430 | .mask = IPIC_SIMSR_L, |
431 | .prio = 0, | |
432 | .force = IPIC_SIFCR_L, | |
433 | .bit = 16, | |
434 | }, | |
f03ca957 | 435 | [81] = { |
f03ca957 LY |
436 | .mask = IPIC_SIMSR_L, |
437 | .prio = 0, | |
438 | .force = IPIC_SIFCR_L, | |
439 | .bit = 17, | |
440 | }, | |
441 | [82] = { | |
f03ca957 LY |
442 | .mask = IPIC_SIMSR_L, |
443 | .prio = 0, | |
444 | .force = IPIC_SIFCR_L, | |
445 | .bit = 18, | |
446 | }, | |
a7267d67 JR |
447 | [83] = { |
448 | .mask = IPIC_SIMSR_L, | |
449 | .prio = 0, | |
450 | .force = IPIC_SIFCR_L, | |
451 | .bit = 19, | |
452 | }, | |
1da177e4 | 453 | [84] = { |
1da177e4 LT |
454 | .mask = IPIC_SIMSR_L, |
455 | .prio = 0, | |
456 | .force = IPIC_SIFCR_L, | |
457 | .bit = 20, | |
458 | }, | |
459 | [85] = { | |
1da177e4 LT |
460 | .mask = IPIC_SIMSR_L, |
461 | .prio = 0, | |
462 | .force = IPIC_SIFCR_L, | |
463 | .bit = 21, | |
464 | }, | |
f03ca957 | 465 | [86] = { |
f03ca957 LY |
466 | .mask = IPIC_SIMSR_L, |
467 | .prio = 0, | |
468 | .force = IPIC_SIFCR_L, | |
469 | .bit = 22, | |
470 | }, | |
471 | [87] = { | |
f03ca957 LY |
472 | .mask = IPIC_SIMSR_L, |
473 | .prio = 0, | |
474 | .force = IPIC_SIFCR_L, | |
475 | .bit = 23, | |
476 | }, | |
477 | [88] = { | |
f03ca957 LY |
478 | .mask = IPIC_SIMSR_L, |
479 | .prio = 0, | |
480 | .force = IPIC_SIFCR_L, | |
481 | .bit = 24, | |
482 | }, | |
483 | [89] = { | |
f03ca957 LY |
484 | .mask = IPIC_SIMSR_L, |
485 | .prio = 0, | |
486 | .force = IPIC_SIFCR_L, | |
487 | .bit = 25, | |
488 | }, | |
1da177e4 | 489 | [90] = { |
1da177e4 LT |
490 | .mask = IPIC_SIMSR_L, |
491 | .prio = 0, | |
492 | .force = IPIC_SIFCR_L, | |
493 | .bit = 26, | |
494 | }, | |
495 | [91] = { | |
1da177e4 LT |
496 | .mask = IPIC_SIMSR_L, |
497 | .prio = 0, | |
498 | .force = IPIC_SIFCR_L, | |
499 | .bit = 27, | |
500 | }, | |
8cf6b195 KP |
501 | [94] = { |
502 | .mask = IPIC_SIMSR_L, | |
503 | .prio = 0, | |
504 | .force = IPIC_SIFCR_L, | |
505 | .bit = 30, | |
506 | }, | |
1da177e4 LT |
507 | }; |
508 | ||
509 | static inline u32 ipic_read(volatile u32 __iomem *base, unsigned int reg) | |
510 | { | |
511 | return in_be32(base + (reg >> 2)); | |
512 | } | |
513 | ||
514 | static inline void ipic_write(volatile u32 __iomem *base, unsigned int reg, u32 value) | |
515 | { | |
516 | out_be32(base + (reg >> 2), value); | |
517 | } | |
518 | ||
b9f0f1bb | 519 | static inline struct ipic * ipic_from_irq(unsigned int virq) |
1da177e4 LT |
520 | { |
521 | return primary_ipic; | |
522 | } | |
523 | ||
b9f0f1bb KP |
524 | #define ipic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq) |
525 | ||
687228ad | 526 | static void ipic_unmask_irq(struct irq_data *d) |
1da177e4 | 527 | { |
687228ad LB |
528 | struct ipic *ipic = ipic_from_irq(d->irq); |
529 | unsigned int src = ipic_irq_to_hw(d->irq); | |
b9f0f1bb | 530 | unsigned long flags; |
1da177e4 LT |
531 | u32 temp; |
532 | ||
a9e8bf21 | 533 | raw_spin_lock_irqsave(&ipic_lock, flags); |
b9f0f1bb | 534 | |
1da177e4 LT |
535 | temp = ipic_read(ipic->regs, ipic_info[src].mask); |
536 | temp |= (1 << (31 - ipic_info[src].bit)); | |
537 | ipic_write(ipic->regs, ipic_info[src].mask, temp); | |
b9f0f1bb | 538 | |
a9e8bf21 | 539 | raw_spin_unlock_irqrestore(&ipic_lock, flags); |
1da177e4 LT |
540 | } |
541 | ||
687228ad | 542 | static void ipic_mask_irq(struct irq_data *d) |
1da177e4 | 543 | { |
687228ad LB |
544 | struct ipic *ipic = ipic_from_irq(d->irq); |
545 | unsigned int src = ipic_irq_to_hw(d->irq); | |
b9f0f1bb | 546 | unsigned long flags; |
1da177e4 LT |
547 | u32 temp; |
548 | ||
a9e8bf21 | 549 | raw_spin_lock_irqsave(&ipic_lock, flags); |
b9f0f1bb | 550 | |
1da177e4 LT |
551 | temp = ipic_read(ipic->regs, ipic_info[src].mask); |
552 | temp &= ~(1 << (31 - ipic_info[src].bit)); | |
553 | ipic_write(ipic->regs, ipic_info[src].mask, temp); | |
b9f0f1bb | 554 | |
77d4309e LY |
555 | /* mb() can't guarantee that masking is finished. But it does finish |
556 | * for nearly all cases. */ | |
557 | mb(); | |
558 | ||
a9e8bf21 | 559 | raw_spin_unlock_irqrestore(&ipic_lock, flags); |
1da177e4 LT |
560 | } |
561 | ||
687228ad | 562 | static void ipic_ack_irq(struct irq_data *d) |
1da177e4 | 563 | { |
687228ad LB |
564 | struct ipic *ipic = ipic_from_irq(d->irq); |
565 | unsigned int src = ipic_irq_to_hw(d->irq); | |
b9f0f1bb | 566 | unsigned long flags; |
1da177e4 LT |
567 | u32 temp; |
568 | ||
a9e8bf21 | 569 | raw_spin_lock_irqsave(&ipic_lock, flags); |
1da177e4 | 570 | |
30c40469 | 571 | temp = 1 << (31 - ipic_info[src].bit); |
77d4309e LY |
572 | ipic_write(ipic->regs, ipic_info[src].ack, temp); |
573 | ||
574 | /* mb() can't guarantee that ack is finished. But it does finish | |
575 | * for nearly all cases. */ | |
576 | mb(); | |
b9f0f1bb | 577 | |
a9e8bf21 | 578 | raw_spin_unlock_irqrestore(&ipic_lock, flags); |
1da177e4 LT |
579 | } |
580 | ||
687228ad | 581 | static void ipic_mask_irq_and_ack(struct irq_data *d) |
1da177e4 | 582 | { |
687228ad LB |
583 | struct ipic *ipic = ipic_from_irq(d->irq); |
584 | unsigned int src = ipic_irq_to_hw(d->irq); | |
b9f0f1bb KP |
585 | unsigned long flags; |
586 | u32 temp; | |
587 | ||
a9e8bf21 | 588 | raw_spin_lock_irqsave(&ipic_lock, flags); |
b9f0f1bb KP |
589 | |
590 | temp = ipic_read(ipic->regs, ipic_info[src].mask); | |
591 | temp &= ~(1 << (31 - ipic_info[src].bit)); | |
592 | ipic_write(ipic->regs, ipic_info[src].mask, temp); | |
593 | ||
30c40469 | 594 | temp = 1 << (31 - ipic_info[src].bit); |
77d4309e LY |
595 | ipic_write(ipic->regs, ipic_info[src].ack, temp); |
596 | ||
597 | /* mb() can't guarantee that ack is finished. But it does finish | |
598 | * for nearly all cases. */ | |
599 | mb(); | |
b9f0f1bb | 600 | |
a9e8bf21 | 601 | raw_spin_unlock_irqrestore(&ipic_lock, flags); |
1da177e4 LT |
602 | } |
603 | ||
687228ad | 604 | static int ipic_set_irq_type(struct irq_data *d, unsigned int flow_type) |
b9f0f1bb | 605 | { |
687228ad LB |
606 | struct ipic *ipic = ipic_from_irq(d->irq); |
607 | unsigned int src = ipic_irq_to_hw(d->irq); | |
b9f0f1bb KP |
608 | unsigned int vold, vnew, edibit; |
609 | ||
610 | if (flow_type == IRQ_TYPE_NONE) | |
611 | flow_type = IRQ_TYPE_LEVEL_LOW; | |
612 | ||
613 | /* ipic supports only low assertion and high-to-low change senses | |
614 | */ | |
615 | if (!(flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))) { | |
616 | printk(KERN_ERR "ipic: sense type 0x%x not supported\n", | |
617 | flow_type); | |
618 | return -EINVAL; | |
619 | } | |
77d4309e LY |
620 | /* ipic supports only edge mode on external interrupts */ |
621 | if ((flow_type & IRQ_TYPE_EDGE_FALLING) && !ipic_info[src].ack) { | |
622 | printk(KERN_ERR "ipic: edge sense not supported on internal " | |
623 | "interrupts\n"); | |
624 | return -EINVAL; | |
ecf4b196 | 625 | |
77d4309e | 626 | } |
b9f0f1bb | 627 | |
ecf4b196 | 628 | irqd_set_trigger_type(d, flow_type); |
b9f0f1bb | 629 | if (flow_type & IRQ_TYPE_LEVEL_LOW) { |
ecf4b196 TG |
630 | __irq_set_handler_locked(d->irq, handle_level_irq); |
631 | d->chip = &ipic_level_irq_chip; | |
b9f0f1bb | 632 | } else { |
ecf4b196 TG |
633 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
634 | d->chip = &ipic_edge_irq_chip; | |
b9f0f1bb KP |
635 | } |
636 | ||
637 | /* only EXT IRQ senses are programmable on ipic | |
638 | * internal IRQ senses are LEVEL_LOW | |
639 | */ | |
640 | if (src == IPIC_IRQ_EXT0) | |
641 | edibit = 15; | |
642 | else | |
643 | if (src >= IPIC_IRQ_EXT1 && src <= IPIC_IRQ_EXT7) | |
644 | edibit = (14 - (src - IPIC_IRQ_EXT1)); | |
645 | else | |
646 | return (flow_type & IRQ_TYPE_LEVEL_LOW) ? 0 : -EINVAL; | |
647 | ||
648 | vold = ipic_read(ipic->regs, IPIC_SECNR); | |
649 | if ((flow_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_FALLING) { | |
650 | vnew = vold | (1 << edibit); | |
651 | } else { | |
652 | vnew = vold & ~(1 << edibit); | |
653 | } | |
654 | if (vold != vnew) | |
655 | ipic_write(ipic->regs, IPIC_SECNR, vnew); | |
ecf4b196 | 656 | return IRQ_SET_MASK_OK_NOCOPY; |
b9f0f1bb KP |
657 | } |
658 | ||
77d4309e LY |
659 | /* level interrupts and edge interrupts have different ack operations */ |
660 | static struct irq_chip ipic_level_irq_chip = { | |
fc380c0c | 661 | .name = "IPIC", |
687228ad LB |
662 | .irq_unmask = ipic_unmask_irq, |
663 | .irq_mask = ipic_mask_irq, | |
664 | .irq_mask_ack = ipic_mask_irq, | |
665 | .irq_set_type = ipic_set_irq_type, | |
77d4309e LY |
666 | }; |
667 | ||
668 | static struct irq_chip ipic_edge_irq_chip = { | |
fc380c0c | 669 | .name = "IPIC", |
687228ad LB |
670 | .irq_unmask = ipic_unmask_irq, |
671 | .irq_mask = ipic_mask_irq, | |
672 | .irq_mask_ack = ipic_mask_irq_and_ack, | |
673 | .irq_ack = ipic_ack_irq, | |
674 | .irq_set_type = ipic_set_irq_type, | |
b9f0f1bb KP |
675 | }; |
676 | ||
677 | static int ipic_host_match(struct irq_host *h, struct device_node *node) | |
678 | { | |
b9f0f1bb | 679 | /* Exact match, unless ipic node is NULL */ |
52964f87 | 680 | return h->of_node == NULL || h->of_node == node; |
b9f0f1bb KP |
681 | } |
682 | ||
683 | static int ipic_host_map(struct irq_host *h, unsigned int virq, | |
684 | irq_hw_number_t hw) | |
685 | { | |
686 | struct ipic *ipic = h->host_data; | |
b9f0f1bb | 687 | |
ec775d0e TG |
688 | irq_set_chip_data(virq, ipic); |
689 | irq_set_chip_and_handler(virq, &ipic_level_irq_chip, handle_level_irq); | |
b9f0f1bb KP |
690 | |
691 | /* Set default irq type */ | |
ec775d0e | 692 | irq_set_irq_type(virq, IRQ_TYPE_NONE); |
b9f0f1bb KP |
693 | |
694 | return 0; | |
695 | } | |
696 | ||
697 | static int ipic_host_xlate(struct irq_host *h, struct device_node *ct, | |
40d50cf7 | 698 | const u32 *intspec, unsigned int intsize, |
b9f0f1bb KP |
699 | irq_hw_number_t *out_hwirq, unsigned int *out_flags) |
700 | ||
701 | { | |
702 | /* interrupt sense values coming from the device tree equal either | |
703 | * LEVEL_LOW (low assertion) or EDGE_FALLING (high-to-low change) | |
704 | */ | |
705 | *out_hwirq = intspec[0]; | |
706 | if (intsize > 1) | |
707 | *out_flags = intspec[1]; | |
708 | else | |
709 | *out_flags = IRQ_TYPE_NONE; | |
710 | return 0; | |
711 | } | |
712 | ||
713 | static struct irq_host_ops ipic_host_ops = { | |
714 | .match = ipic_host_match, | |
715 | .map = ipic_host_map, | |
716 | .xlate = ipic_host_xlate, | |
1da177e4 LT |
717 | }; |
718 | ||
126186a0 | 719 | struct ipic * __init ipic_init(struct device_node *node, unsigned int flags) |
1da177e4 | 720 | { |
b9f0f1bb KP |
721 | struct ipic *ipic; |
722 | struct resource res; | |
723 | u32 temp = 0, ret; | |
724 | ||
84f1c1e0 ME |
725 | ret = of_address_to_resource(node, 0, &res); |
726 | if (ret) | |
727 | return NULL; | |
728 | ||
ea96025a | 729 | ipic = kzalloc(sizeof(*ipic), GFP_KERNEL); |
b9f0f1bb | 730 | if (ipic == NULL) |
126186a0 | 731 | return NULL; |
b9f0f1bb | 732 | |
19fc65b5 | 733 | ipic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR, |
b9f0f1bb KP |
734 | NR_IPIC_INTS, |
735 | &ipic_host_ops, 0); | |
7a626b66 JL |
736 | if (ipic->irqhost == NULL) { |
737 | kfree(ipic); | |
126186a0 | 738 | return NULL; |
7a626b66 | 739 | } |
b9f0f1bb | 740 | |
b9f0f1bb | 741 | ipic->regs = ioremap(res.start, res.end - res.start + 1); |
1da177e4 | 742 | |
b9f0f1bb | 743 | ipic->irqhost->host_data = ipic; |
1da177e4 | 744 | |
b9f0f1bb KP |
745 | /* init hw */ |
746 | ipic_write(ipic->regs, IPIC_SICNR, 0x0); | |
1da177e4 LT |
747 | |
748 | /* default priority scheme is grouped. If spread mode is required | |
749 | * configure SICFR accordingly */ | |
750 | if (flags & IPIC_SPREADMODE_GRP_A) | |
751 | temp |= SICFR_IPSA; | |
f03ca957 LY |
752 | if (flags & IPIC_SPREADMODE_GRP_B) |
753 | temp |= SICFR_IPSB; | |
754 | if (flags & IPIC_SPREADMODE_GRP_C) | |
755 | temp |= SICFR_IPSC; | |
1da177e4 LT |
756 | if (flags & IPIC_SPREADMODE_GRP_D) |
757 | temp |= SICFR_IPSD; | |
758 | if (flags & IPIC_SPREADMODE_MIX_A) | |
759 | temp |= SICFR_MPSA; | |
760 | if (flags & IPIC_SPREADMODE_MIX_B) | |
761 | temp |= SICFR_MPSB; | |
762 | ||
f03ca957 | 763 | ipic_write(ipic->regs, IPIC_SICFR, temp); |
1da177e4 LT |
764 | |
765 | /* handle MCP route */ | |
766 | temp = 0; | |
767 | if (flags & IPIC_DISABLE_MCP_OUT) | |
768 | temp = SERCR_MCPR; | |
b9f0f1bb | 769 | ipic_write(ipic->regs, IPIC_SERCR, temp); |
1da177e4 LT |
770 | |
771 | /* handle routing of IRQ0 to MCP */ | |
b9f0f1bb | 772 | temp = ipic_read(ipic->regs, IPIC_SEMSR); |
1da177e4 LT |
773 | |
774 | if (flags & IPIC_IRQ0_MCP) | |
775 | temp |= SEMSR_SIRQ0; | |
776 | else | |
777 | temp &= ~SEMSR_SIRQ0; | |
778 | ||
b9f0f1bb | 779 | ipic_write(ipic->regs, IPIC_SEMSR, temp); |
1da177e4 | 780 | |
b9f0f1bb KP |
781 | primary_ipic = ipic; |
782 | irq_set_default_host(primary_ipic->irqhost); | |
1da177e4 | 783 | |
8640d3bf SAS |
784 | ipic_write(ipic->regs, IPIC_SIMSR_H, 0); |
785 | ipic_write(ipic->regs, IPIC_SIMSR_L, 0); | |
786 | ||
b9f0f1bb KP |
787 | printk ("IPIC (%d IRQ sources) at %p\n", NR_IPIC_INTS, |
788 | primary_ipic->regs); | |
126186a0 KG |
789 | |
790 | return ipic; | |
1da177e4 LT |
791 | } |
792 | ||
b9f0f1bb | 793 | int ipic_set_priority(unsigned int virq, unsigned int priority) |
1da177e4 | 794 | { |
b9f0f1bb KP |
795 | struct ipic *ipic = ipic_from_irq(virq); |
796 | unsigned int src = ipic_irq_to_hw(virq); | |
1da177e4 LT |
797 | u32 temp; |
798 | ||
799 | if (priority > 7) | |
800 | return -EINVAL; | |
801 | if (src > 127) | |
802 | return -EINVAL; | |
803 | if (ipic_info[src].prio == 0) | |
804 | return -EINVAL; | |
805 | ||
806 | temp = ipic_read(ipic->regs, ipic_info[src].prio); | |
807 | ||
808 | if (priority < 4) { | |
809 | temp &= ~(0x7 << (20 + (3 - priority) * 3)); | |
810 | temp |= ipic_info[src].prio_mask << (20 + (3 - priority) * 3); | |
811 | } else { | |
812 | temp &= ~(0x7 << (4 + (7 - priority) * 3)); | |
813 | temp |= ipic_info[src].prio_mask << (4 + (7 - priority) * 3); | |
814 | } | |
815 | ||
816 | ipic_write(ipic->regs, ipic_info[src].prio, temp); | |
817 | ||
818 | return 0; | |
819 | } | |
820 | ||
b9f0f1bb | 821 | void ipic_set_highest_priority(unsigned int virq) |
1da177e4 | 822 | { |
b9f0f1bb KP |
823 | struct ipic *ipic = ipic_from_irq(virq); |
824 | unsigned int src = ipic_irq_to_hw(virq); | |
1da177e4 LT |
825 | u32 temp; |
826 | ||
827 | temp = ipic_read(ipic->regs, IPIC_SICFR); | |
828 | ||
829 | /* clear and set HPI */ | |
830 | temp &= 0x7f000000; | |
831 | temp |= (src & 0x7f) << 24; | |
832 | ||
833 | ipic_write(ipic->regs, IPIC_SICFR, temp); | |
834 | } | |
835 | ||
836 | void ipic_set_default_priority(void) | |
837 | { | |
f03ca957 LY |
838 | ipic_write(primary_ipic->regs, IPIC_SIPRR_A, IPIC_PRIORITY_DEFAULT); |
839 | ipic_write(primary_ipic->regs, IPIC_SIPRR_B, IPIC_PRIORITY_DEFAULT); | |
840 | ipic_write(primary_ipic->regs, IPIC_SIPRR_C, IPIC_PRIORITY_DEFAULT); | |
841 | ipic_write(primary_ipic->regs, IPIC_SIPRR_D, IPIC_PRIORITY_DEFAULT); | |
842 | ipic_write(primary_ipic->regs, IPIC_SMPRR_A, IPIC_PRIORITY_DEFAULT); | |
843 | ipic_write(primary_ipic->regs, IPIC_SMPRR_B, IPIC_PRIORITY_DEFAULT); | |
1da177e4 LT |
844 | } |
845 | ||
846 | void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq) | |
847 | { | |
848 | struct ipic *ipic = primary_ipic; | |
849 | u32 temp; | |
850 | ||
851 | temp = ipic_read(ipic->regs, IPIC_SERMR); | |
852 | temp |= (1 << (31 - mcp_irq)); | |
853 | ipic_write(ipic->regs, IPIC_SERMR, temp); | |
854 | } | |
855 | ||
856 | void ipic_disable_mcp(enum ipic_mcp_irq mcp_irq) | |
857 | { | |
858 | struct ipic *ipic = primary_ipic; | |
859 | u32 temp; | |
860 | ||
861 | temp = ipic_read(ipic->regs, IPIC_SERMR); | |
862 | temp &= (1 << (31 - mcp_irq)); | |
863 | ipic_write(ipic->regs, IPIC_SERMR, temp); | |
864 | } | |
865 | ||
866 | u32 ipic_get_mcp_status(void) | |
867 | { | |
868 | return ipic_read(primary_ipic->regs, IPIC_SERMR); | |
869 | } | |
870 | ||
871 | void ipic_clear_mcp_status(u32 mask) | |
872 | { | |
873 | ipic_write(primary_ipic->regs, IPIC_SERMR, mask); | |
874 | } | |
875 | ||
b9f0f1bb | 876 | /* Return an interrupt vector or NO_IRQ if no interrupt is pending. */ |
35a84c2f | 877 | unsigned int ipic_get_irq(void) |
1da177e4 LT |
878 | { |
879 | int irq; | |
880 | ||
b9f0f1bb KP |
881 | BUG_ON(primary_ipic == NULL); |
882 | ||
883 | #define IPIC_SIVCR_VECTOR_MASK 0x7f | |
884 | irq = ipic_read(primary_ipic->regs, IPIC_SIVCR) & IPIC_SIVCR_VECTOR_MASK; | |
1da177e4 LT |
885 | |
886 | if (irq == 0) /* 0 --> no irq is pending */ | |
b9f0f1bb | 887 | return NO_IRQ; |
1da177e4 | 888 | |
b9f0f1bb | 889 | return irq_linear_revmap(primary_ipic->irqhost, irq); |
1da177e4 LT |
890 | } |
891 | ||
e2a02ba6 | 892 | #ifdef CONFIG_SUSPEND |
d49747bd SW |
893 | static struct { |
894 | u32 sicfr; | |
895 | u32 siprr[2]; | |
896 | u32 simsr[2]; | |
897 | u32 sicnr; | |
898 | u32 smprr[2]; | |
899 | u32 semsr; | |
900 | u32 secnr; | |
901 | u32 sermr; | |
902 | u32 sercr; | |
903 | } ipic_saved_state; | |
904 | ||
905 | static int ipic_suspend(struct sys_device *sdev, pm_message_t state) | |
906 | { | |
907 | struct ipic *ipic = primary_ipic; | |
908 | ||
909 | ipic_saved_state.sicfr = ipic_read(ipic->regs, IPIC_SICFR); | |
910 | ipic_saved_state.siprr[0] = ipic_read(ipic->regs, IPIC_SIPRR_A); | |
911 | ipic_saved_state.siprr[1] = ipic_read(ipic->regs, IPIC_SIPRR_D); | |
912 | ipic_saved_state.simsr[0] = ipic_read(ipic->regs, IPIC_SIMSR_H); | |
913 | ipic_saved_state.simsr[1] = ipic_read(ipic->regs, IPIC_SIMSR_L); | |
914 | ipic_saved_state.sicnr = ipic_read(ipic->regs, IPIC_SICNR); | |
915 | ipic_saved_state.smprr[0] = ipic_read(ipic->regs, IPIC_SMPRR_A); | |
916 | ipic_saved_state.smprr[1] = ipic_read(ipic->regs, IPIC_SMPRR_B); | |
917 | ipic_saved_state.semsr = ipic_read(ipic->regs, IPIC_SEMSR); | |
918 | ipic_saved_state.secnr = ipic_read(ipic->regs, IPIC_SECNR); | |
919 | ipic_saved_state.sermr = ipic_read(ipic->regs, IPIC_SERMR); | |
920 | ipic_saved_state.sercr = ipic_read(ipic->regs, IPIC_SERCR); | |
921 | ||
922 | if (fsl_deep_sleep()) { | |
923 | /* In deep sleep, make sure there can be no | |
924 | * pending interrupts, as this can cause | |
925 | * problems on 831x. | |
926 | */ | |
927 | ipic_write(ipic->regs, IPIC_SIMSR_H, 0); | |
928 | ipic_write(ipic->regs, IPIC_SIMSR_L, 0); | |
929 | ipic_write(ipic->regs, IPIC_SEMSR, 0); | |
930 | ipic_write(ipic->regs, IPIC_SERMR, 0); | |
931 | } | |
932 | ||
933 | return 0; | |
934 | } | |
935 | ||
936 | static int ipic_resume(struct sys_device *sdev) | |
937 | { | |
938 | struct ipic *ipic = primary_ipic; | |
939 | ||
940 | ipic_write(ipic->regs, IPIC_SICFR, ipic_saved_state.sicfr); | |
941 | ipic_write(ipic->regs, IPIC_SIPRR_A, ipic_saved_state.siprr[0]); | |
942 | ipic_write(ipic->regs, IPIC_SIPRR_D, ipic_saved_state.siprr[1]); | |
943 | ipic_write(ipic->regs, IPIC_SIMSR_H, ipic_saved_state.simsr[0]); | |
944 | ipic_write(ipic->regs, IPIC_SIMSR_L, ipic_saved_state.simsr[1]); | |
945 | ipic_write(ipic->regs, IPIC_SICNR, ipic_saved_state.sicnr); | |
946 | ipic_write(ipic->regs, IPIC_SMPRR_A, ipic_saved_state.smprr[0]); | |
947 | ipic_write(ipic->regs, IPIC_SMPRR_B, ipic_saved_state.smprr[1]); | |
948 | ipic_write(ipic->regs, IPIC_SEMSR, ipic_saved_state.semsr); | |
949 | ipic_write(ipic->regs, IPIC_SECNR, ipic_saved_state.secnr); | |
950 | ipic_write(ipic->regs, IPIC_SERMR, ipic_saved_state.sermr); | |
951 | ipic_write(ipic->regs, IPIC_SERCR, ipic_saved_state.sercr); | |
952 | ||
953 | return 0; | |
954 | } | |
955 | #else | |
956 | #define ipic_suspend NULL | |
957 | #define ipic_resume NULL | |
958 | #endif | |
959 | ||
1da177e4 | 960 | static struct sysdev_class ipic_sysclass = { |
af5ca3f4 | 961 | .name = "ipic", |
d49747bd SW |
962 | .suspend = ipic_suspend, |
963 | .resume = ipic_resume, | |
1da177e4 LT |
964 | }; |
965 | ||
966 | static struct sys_device device_ipic = { | |
967 | .id = 0, | |
968 | .cls = &ipic_sysclass, | |
969 | }; | |
970 | ||
971 | static int __init init_ipic_sysfs(void) | |
972 | { | |
973 | int rc; | |
974 | ||
1428a9fa | 975 | if (!primary_ipic || !primary_ipic->regs) |
1da177e4 LT |
976 | return -ENODEV; |
977 | printk(KERN_DEBUG "Registering ipic with sysfs...\n"); | |
978 | ||
979 | rc = sysdev_class_register(&ipic_sysclass); | |
980 | if (rc) { | |
981 | printk(KERN_ERR "Failed registering ipic sys class\n"); | |
982 | return -ENODEV; | |
983 | } | |
984 | rc = sysdev_register(&device_ipic); | |
985 | if (rc) { | |
986 | printk(KERN_ERR "Failed registering ipic sys device\n"); | |
987 | return -ENODEV; | |
988 | } | |
989 | return 0; | |
990 | } | |
991 | ||
992 | subsys_initcall(init_ipic_sysfs); |