Commit | Line | Data |
---|---|---|
f2a0bd37 | 1 | #include <linux/kernel.h> |
f2a0bd37 | 2 | #include <linux/stddef.h> |
f2a0bd37 VB |
3 | #include <linux/sched.h> |
4 | #include <linux/signal.h> | |
5 | #include <linux/irq.h> | |
6 | #include <linux/dma-mapping.h> | |
7 | #include <asm/prom.h> | |
8 | #include <asm/irq.h> | |
9 | #include <asm/io.h> | |
10 | #include <asm/8xx_immap.h> | |
f2a0bd37 VB |
11 | |
12 | #include "mpc8xx_pic.h" | |
13 | ||
14 | ||
15 | #define PIC_VEC_SPURRIOUS 15 | |
16 | ||
17 | extern int cpm_get_irq(struct pt_regs *regs); | |
18 | ||
bae1d8f1 | 19 | static struct irq_domain *mpc8xx_pic_host; |
8751ed14 | 20 | static unsigned long mpc8xx_cached_irq_mask; |
fb533d0c | 21 | static sysconf8xx_t __iomem *siu_reg; |
f2a0bd37 | 22 | |
8751ed14 GL |
23 | static inline unsigned long mpc8xx_irqd_to_bit(struct irq_data *d) |
24 | { | |
25 | return 0x80000000 >> irqd_to_hwirq(d); | |
26 | } | |
f2a0bd37 | 27 | |
febd4017 | 28 | static void mpc8xx_unmask_irq(struct irq_data *d) |
f2a0bd37 | 29 | { |
8751ed14 GL |
30 | mpc8xx_cached_irq_mask |= mpc8xx_irqd_to_bit(d); |
31 | out_be32(&siu_reg->sc_simask, mpc8xx_cached_irq_mask); | |
f2a0bd37 VB |
32 | } |
33 | ||
febd4017 | 34 | static void mpc8xx_mask_irq(struct irq_data *d) |
f2a0bd37 | 35 | { |
8751ed14 GL |
36 | mpc8xx_cached_irq_mask &= ~mpc8xx_irqd_to_bit(d); |
37 | out_be32(&siu_reg->sc_simask, mpc8xx_cached_irq_mask); | |
f2a0bd37 VB |
38 | } |
39 | ||
febd4017 | 40 | static void mpc8xx_ack(struct irq_data *d) |
f2a0bd37 | 41 | { |
8751ed14 | 42 | out_be32(&siu_reg->sc_sipend, mpc8xx_irqd_to_bit(d)); |
f2a0bd37 VB |
43 | } |
44 | ||
febd4017 | 45 | static void mpc8xx_end_irq(struct irq_data *d) |
f2a0bd37 | 46 | { |
8751ed14 GL |
47 | mpc8xx_cached_irq_mask |= mpc8xx_irqd_to_bit(d); |
48 | out_be32(&siu_reg->sc_simask, mpc8xx_cached_irq_mask); | |
f2a0bd37 VB |
49 | } |
50 | ||
febd4017 | 51 | static int mpc8xx_set_irq_type(struct irq_data *d, unsigned int flow_type) |
f2a0bd37 | 52 | { |
8751ed14 GL |
53 | /* only external IRQ senses are programmable */ |
54 | if ((flow_type & IRQ_TYPE_EDGE_FALLING) && !(irqd_to_hwirq(d) & 1)) { | |
f2a0bd37 | 55 | unsigned int siel = in_be32(&siu_reg->sc_siel); |
8751ed14 GL |
56 | siel |= mpc8xx_irqd_to_bit(d); |
57 | out_be32(&siu_reg->sc_siel, siel); | |
9ca86b20 | 58 | irq_set_handler_locked(d, handle_edge_irq); |
f2a0bd37 VB |
59 | } |
60 | return 0; | |
61 | } | |
62 | ||
63 | static struct irq_chip mpc8xx_pic = { | |
255e8e04 | 64 | .name = "8XX SIU", |
febd4017 LB |
65 | .irq_unmask = mpc8xx_unmask_irq, |
66 | .irq_mask = mpc8xx_mask_irq, | |
67 | .irq_ack = mpc8xx_ack, | |
68 | .irq_eoi = mpc8xx_end_irq, | |
69 | .irq_set_type = mpc8xx_set_irq_type, | |
f2a0bd37 VB |
70 | }; |
71 | ||
72 | unsigned int mpc8xx_get_irq(void) | |
73 | { | |
74 | int irq; | |
75 | ||
76 | /* For MPC8xx, read the SIVEC register and shift the bits down | |
77 | * to get the irq number. | |
78 | */ | |
79 | irq = in_be32(&siu_reg->sc_sivec) >> 26; | |
80 | ||
81 | if (irq == PIC_VEC_SPURRIOUS) | |
82 | irq = NO_IRQ; | |
83 | ||
84 | return irq_linear_revmap(mpc8xx_pic_host, irq); | |
85 | ||
86 | } | |
87 | ||
bae1d8f1 | 88 | static int mpc8xx_pic_host_map(struct irq_domain *h, unsigned int virq, |
f2a0bd37 VB |
89 | irq_hw_number_t hw) |
90 | { | |
91 | pr_debug("mpc8xx_pic_host_map(%d, 0x%lx)\n", virq, hw); | |
92 | ||
93 | /* Set default irq handle */ | |
ec775d0e | 94 | irq_set_chip_and_handler(virq, &mpc8xx_pic, handle_level_irq); |
f2a0bd37 VB |
95 | return 0; |
96 | } | |
97 | ||
98 | ||
bae1d8f1 | 99 | static int mpc8xx_pic_host_xlate(struct irq_domain *h, struct device_node *ct, |
40d50cf7 | 100 | const u32 *intspec, unsigned int intsize, |
f2a0bd37 VB |
101 | irq_hw_number_t *out_hwirq, unsigned int *out_flags) |
102 | { | |
103 | static unsigned char map_pic_senses[4] = { | |
104 | IRQ_TYPE_EDGE_RISING, | |
105 | IRQ_TYPE_LEVEL_LOW, | |
106 | IRQ_TYPE_LEVEL_HIGH, | |
107 | IRQ_TYPE_EDGE_FALLING, | |
108 | }; | |
109 | ||
8751ed14 GL |
110 | if (intspec[0] > 0x1f) |
111 | return 0; | |
112 | ||
f2a0bd37 VB |
113 | *out_hwirq = intspec[0]; |
114 | if (intsize > 1 && intspec[1] < 4) | |
115 | *out_flags = map_pic_senses[intspec[1]]; | |
116 | else | |
117 | *out_flags = IRQ_TYPE_NONE; | |
118 | ||
119 | return 0; | |
120 | } | |
121 | ||
122 | ||
202648a6 | 123 | static const struct irq_domain_ops mpc8xx_pic_host_ops = { |
f2a0bd37 VB |
124 | .map = mpc8xx_pic_host_map, |
125 | .xlate = mpc8xx_pic_host_xlate, | |
126 | }; | |
127 | ||
128 | int mpc8xx_pic_init(void) | |
129 | { | |
130 | struct resource res; | |
fb533d0c | 131 | struct device_node *np; |
f2a0bd37 VB |
132 | int ret; |
133 | ||
fb533d0c SW |
134 | np = of_find_compatible_node(NULL, NULL, "fsl,pq1-pic"); |
135 | if (np == NULL) | |
136 | np = of_find_node_by_type(NULL, "mpc8xx-pic"); | |
f2a0bd37 | 137 | if (np == NULL) { |
fb533d0c | 138 | printk(KERN_ERR "Could not find fsl,pq1-pic node\n"); |
f2a0bd37 VB |
139 | return -ENOMEM; |
140 | } | |
141 | ||
f2a0bd37 | 142 | ret = of_address_to_resource(np, 0, &res); |
f2a0bd37 | 143 | if (ret) |
52964f87 | 144 | goto out; |
f2a0bd37 | 145 | |
28f65c11 | 146 | siu_reg = ioremap(res.start, resource_size(&res)); |
b1725c93 JL |
147 | if (siu_reg == NULL) { |
148 | ret = -EINVAL; | |
149 | goto out; | |
150 | } | |
f2a0bd37 | 151 | |
a8db8cf0 | 152 | mpc8xx_pic_host = irq_domain_add_linear(np, 64, &mpc8xx_pic_host_ops, NULL); |
f2a0bd37 VB |
153 | if (mpc8xx_pic_host == NULL) { |
154 | printk(KERN_ERR "MPC8xx PIC: failed to allocate irq host!\n"); | |
155 | ret = -ENOMEM; | |
b1725c93 | 156 | goto out; |
f2a0bd37 | 157 | } |
b1725c93 | 158 | return 0; |
f2a0bd37 | 159 | |
52964f87 ME |
160 | out: |
161 | of_node_put(np); | |
f2a0bd37 VB |
162 | return ret; |
163 | } |