Commit | Line | Data |
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14cf11af PM |
1 | /* |
2 | * arch/powerpc/kernel/mpic.c | |
3 | * | |
4 | * Driver for interrupt controllers following the OpenPIC standard, the | |
5 | * common implementation beeing IBM's MPIC. This driver also can deal | |
6 | * with various broken implementations of this HW. | |
7 | * | |
8 | * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp. | |
9 | * | |
10 | * This file is subject to the terms and conditions of the GNU General Public | |
11 | * License. See the file COPYING in the main directory of this archive | |
12 | * for more details. | |
13 | */ | |
14 | ||
15 | #undef DEBUG | |
1beb6a7d BH |
16 | #undef DEBUG_IPI |
17 | #undef DEBUG_IRQ | |
18 | #undef DEBUG_LOW | |
14cf11af | 19 | |
14cf11af PM |
20 | #include <linux/types.h> |
21 | #include <linux/kernel.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/irq.h> | |
24 | #include <linux/smp.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/bootmem.h> | |
27 | #include <linux/spinlock.h> | |
28 | #include <linux/pci.h> | |
29 | ||
30 | #include <asm/ptrace.h> | |
31 | #include <asm/signal.h> | |
32 | #include <asm/io.h> | |
33 | #include <asm/pgtable.h> | |
34 | #include <asm/irq.h> | |
35 | #include <asm/machdep.h> | |
36 | #include <asm/mpic.h> | |
37 | #include <asm/smp.h> | |
38 | ||
a7de7c74 ME |
39 | #include "mpic.h" |
40 | ||
14cf11af PM |
41 | #ifdef DEBUG |
42 | #define DBG(fmt...) printk(fmt) | |
43 | #else | |
44 | #define DBG(fmt...) | |
45 | #endif | |
46 | ||
47 | static struct mpic *mpics; | |
48 | static struct mpic *mpic_primary; | |
49 | static DEFINE_SPINLOCK(mpic_lock); | |
50 | ||
c0c0d996 | 51 | #ifdef CONFIG_PPC32 /* XXX for now */ |
e40c7f02 AW |
52 | #ifdef CONFIG_IRQ_ALL_CPUS |
53 | #define distribute_irqs (1) | |
54 | #else | |
55 | #define distribute_irqs (0) | |
56 | #endif | |
c0c0d996 | 57 | #endif |
14cf11af | 58 | |
7233593b ZR |
59 | #ifdef CONFIG_MPIC_WEIRD |
60 | static u32 mpic_infos[][MPIC_IDX_END] = { | |
61 | [0] = { /* Original OpenPIC compatible MPIC */ | |
62 | MPIC_GREG_BASE, | |
63 | MPIC_GREG_FEATURE_0, | |
64 | MPIC_GREG_GLOBAL_CONF_0, | |
65 | MPIC_GREG_VENDOR_ID, | |
66 | MPIC_GREG_IPI_VECTOR_PRI_0, | |
67 | MPIC_GREG_IPI_STRIDE, | |
68 | MPIC_GREG_SPURIOUS, | |
69 | MPIC_GREG_TIMER_FREQ, | |
70 | ||
71 | MPIC_TIMER_BASE, | |
72 | MPIC_TIMER_STRIDE, | |
73 | MPIC_TIMER_CURRENT_CNT, | |
74 | MPIC_TIMER_BASE_CNT, | |
75 | MPIC_TIMER_VECTOR_PRI, | |
76 | MPIC_TIMER_DESTINATION, | |
77 | ||
78 | MPIC_CPU_BASE, | |
79 | MPIC_CPU_STRIDE, | |
80 | MPIC_CPU_IPI_DISPATCH_0, | |
81 | MPIC_CPU_IPI_DISPATCH_STRIDE, | |
82 | MPIC_CPU_CURRENT_TASK_PRI, | |
83 | MPIC_CPU_WHOAMI, | |
84 | MPIC_CPU_INTACK, | |
85 | MPIC_CPU_EOI, | |
f365355e | 86 | MPIC_CPU_MCACK, |
7233593b ZR |
87 | |
88 | MPIC_IRQ_BASE, | |
89 | MPIC_IRQ_STRIDE, | |
90 | MPIC_IRQ_VECTOR_PRI, | |
91 | MPIC_VECPRI_VECTOR_MASK, | |
92 | MPIC_VECPRI_POLARITY_POSITIVE, | |
93 | MPIC_VECPRI_POLARITY_NEGATIVE, | |
94 | MPIC_VECPRI_SENSE_LEVEL, | |
95 | MPIC_VECPRI_SENSE_EDGE, | |
96 | MPIC_VECPRI_POLARITY_MASK, | |
97 | MPIC_VECPRI_SENSE_MASK, | |
98 | MPIC_IRQ_DESTINATION | |
99 | }, | |
100 | [1] = { /* Tsi108/109 PIC */ | |
101 | TSI108_GREG_BASE, | |
102 | TSI108_GREG_FEATURE_0, | |
103 | TSI108_GREG_GLOBAL_CONF_0, | |
104 | TSI108_GREG_VENDOR_ID, | |
105 | TSI108_GREG_IPI_VECTOR_PRI_0, | |
106 | TSI108_GREG_IPI_STRIDE, | |
107 | TSI108_GREG_SPURIOUS, | |
108 | TSI108_GREG_TIMER_FREQ, | |
109 | ||
110 | TSI108_TIMER_BASE, | |
111 | TSI108_TIMER_STRIDE, | |
112 | TSI108_TIMER_CURRENT_CNT, | |
113 | TSI108_TIMER_BASE_CNT, | |
114 | TSI108_TIMER_VECTOR_PRI, | |
115 | TSI108_TIMER_DESTINATION, | |
116 | ||
117 | TSI108_CPU_BASE, | |
118 | TSI108_CPU_STRIDE, | |
119 | TSI108_CPU_IPI_DISPATCH_0, | |
120 | TSI108_CPU_IPI_DISPATCH_STRIDE, | |
121 | TSI108_CPU_CURRENT_TASK_PRI, | |
122 | TSI108_CPU_WHOAMI, | |
123 | TSI108_CPU_INTACK, | |
124 | TSI108_CPU_EOI, | |
f365355e | 125 | TSI108_CPU_MCACK, |
7233593b ZR |
126 | |
127 | TSI108_IRQ_BASE, | |
128 | TSI108_IRQ_STRIDE, | |
129 | TSI108_IRQ_VECTOR_PRI, | |
130 | TSI108_VECPRI_VECTOR_MASK, | |
131 | TSI108_VECPRI_POLARITY_POSITIVE, | |
132 | TSI108_VECPRI_POLARITY_NEGATIVE, | |
133 | TSI108_VECPRI_SENSE_LEVEL, | |
134 | TSI108_VECPRI_SENSE_EDGE, | |
135 | TSI108_VECPRI_POLARITY_MASK, | |
136 | TSI108_VECPRI_SENSE_MASK, | |
137 | TSI108_IRQ_DESTINATION | |
138 | }, | |
139 | }; | |
140 | ||
141 | #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name] | |
142 | ||
143 | #else /* CONFIG_MPIC_WEIRD */ | |
144 | ||
145 | #define MPIC_INFO(name) MPIC_##name | |
146 | ||
147 | #endif /* CONFIG_MPIC_WEIRD */ | |
148 | ||
14cf11af PM |
149 | /* |
150 | * Register accessor functions | |
151 | */ | |
152 | ||
153 | ||
fbf0274e BH |
154 | static inline u32 _mpic_read(enum mpic_reg_type type, |
155 | struct mpic_reg_bank *rb, | |
156 | unsigned int reg) | |
14cf11af | 157 | { |
fbf0274e BH |
158 | switch(type) { |
159 | #ifdef CONFIG_PPC_DCR | |
160 | case mpic_access_dcr: | |
83f34df4 | 161 | return dcr_read(rb->dhost, reg); |
fbf0274e BH |
162 | #endif |
163 | case mpic_access_mmio_be: | |
164 | return in_be32(rb->base + (reg >> 2)); | |
165 | case mpic_access_mmio_le: | |
166 | default: | |
167 | return in_le32(rb->base + (reg >> 2)); | |
168 | } | |
14cf11af PM |
169 | } |
170 | ||
fbf0274e BH |
171 | static inline void _mpic_write(enum mpic_reg_type type, |
172 | struct mpic_reg_bank *rb, | |
173 | unsigned int reg, u32 value) | |
14cf11af | 174 | { |
fbf0274e BH |
175 | switch(type) { |
176 | #ifdef CONFIG_PPC_DCR | |
177 | case mpic_access_dcr: | |
d9d1063d JB |
178 | dcr_write(rb->dhost, reg, value); |
179 | break; | |
fbf0274e BH |
180 | #endif |
181 | case mpic_access_mmio_be: | |
d9d1063d JB |
182 | out_be32(rb->base + (reg >> 2), value); |
183 | break; | |
fbf0274e BH |
184 | case mpic_access_mmio_le: |
185 | default: | |
d9d1063d JB |
186 | out_le32(rb->base + (reg >> 2), value); |
187 | break; | |
fbf0274e | 188 | } |
14cf11af PM |
189 | } |
190 | ||
191 | static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi) | |
192 | { | |
fbf0274e | 193 | enum mpic_reg_type type = mpic->reg_type; |
7233593b ZR |
194 | unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) + |
195 | (ipi * MPIC_INFO(GREG_IPI_STRIDE)); | |
14cf11af | 196 | |
fbf0274e BH |
197 | if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le) |
198 | type = mpic_access_mmio_be; | |
199 | return _mpic_read(type, &mpic->gregs, offset); | |
14cf11af PM |
200 | } |
201 | ||
202 | static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value) | |
203 | { | |
7233593b ZR |
204 | unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) + |
205 | (ipi * MPIC_INFO(GREG_IPI_STRIDE)); | |
14cf11af | 206 | |
fbf0274e | 207 | _mpic_write(mpic->reg_type, &mpic->gregs, offset, value); |
14cf11af PM |
208 | } |
209 | ||
210 | static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg) | |
211 | { | |
212 | unsigned int cpu = 0; | |
213 | ||
214 | if (mpic->flags & MPIC_PRIMARY) | |
215 | cpu = hard_smp_processor_id(); | |
fbf0274e | 216 | return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg); |
14cf11af PM |
217 | } |
218 | ||
219 | static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value) | |
220 | { | |
221 | unsigned int cpu = 0; | |
222 | ||
223 | if (mpic->flags & MPIC_PRIMARY) | |
224 | cpu = hard_smp_processor_id(); | |
225 | ||
fbf0274e | 226 | _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value); |
14cf11af PM |
227 | } |
228 | ||
229 | static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg) | |
230 | { | |
231 | unsigned int isu = src_no >> mpic->isu_shift; | |
232 | unsigned int idx = src_no & mpic->isu_mask; | |
11a6b292 | 233 | unsigned int val; |
14cf11af | 234 | |
11a6b292 ME |
235 | val = _mpic_read(mpic->reg_type, &mpic->isus[isu], |
236 | reg + (idx * MPIC_INFO(IRQ_STRIDE))); | |
0d72ba93 OJ |
237 | #ifdef CONFIG_MPIC_BROKEN_REGREAD |
238 | if (reg == 0) | |
11a6b292 ME |
239 | val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) | |
240 | mpic->isu_reg0_shadow[src_no]; | |
0d72ba93 | 241 | #endif |
11a6b292 | 242 | return val; |
14cf11af PM |
243 | } |
244 | ||
245 | static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no, | |
246 | unsigned int reg, u32 value) | |
247 | { | |
248 | unsigned int isu = src_no >> mpic->isu_shift; | |
249 | unsigned int idx = src_no & mpic->isu_mask; | |
250 | ||
fbf0274e | 251 | _mpic_write(mpic->reg_type, &mpic->isus[isu], |
7233593b | 252 | reg + (idx * MPIC_INFO(IRQ_STRIDE)), value); |
0d72ba93 OJ |
253 | |
254 | #ifdef CONFIG_MPIC_BROKEN_REGREAD | |
255 | if (reg == 0) | |
11a6b292 ME |
256 | mpic->isu_reg0_shadow[src_no] = |
257 | value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY); | |
0d72ba93 | 258 | #endif |
14cf11af PM |
259 | } |
260 | ||
fbf0274e BH |
261 | #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r)) |
262 | #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v)) | |
14cf11af PM |
263 | #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i)) |
264 | #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v)) | |
265 | #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i)) | |
266 | #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v)) | |
267 | #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r)) | |
268 | #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v)) | |
269 | ||
270 | ||
271 | /* | |
272 | * Low level utility functions | |
273 | */ | |
274 | ||
275 | ||
c51a3fdc | 276 | static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr, |
fbf0274e BH |
277 | struct mpic_reg_bank *rb, unsigned int offset, |
278 | unsigned int size) | |
279 | { | |
280 | rb->base = ioremap(phys_addr + offset, size); | |
281 | BUG_ON(rb->base == NULL); | |
282 | } | |
283 | ||
284 | #ifdef CONFIG_PPC_DCR | |
5a2642f6 BH |
285 | static void _mpic_map_dcr(struct mpic *mpic, struct device_node *node, |
286 | struct mpic_reg_bank *rb, | |
fbf0274e BH |
287 | unsigned int offset, unsigned int size) |
288 | { | |
0411a5e2 ME |
289 | const u32 *dbasep; |
290 | ||
5a2642f6 | 291 | dbasep = of_get_property(node, "dcr-reg", NULL); |
0411a5e2 | 292 | |
5a2642f6 | 293 | rb->dhost = dcr_map(node, *dbasep + offset, size); |
fbf0274e BH |
294 | BUG_ON(!DCR_MAP_OK(rb->dhost)); |
295 | } | |
296 | ||
5a2642f6 BH |
297 | static inline void mpic_map(struct mpic *mpic, struct device_node *node, |
298 | phys_addr_t phys_addr, struct mpic_reg_bank *rb, | |
299 | unsigned int offset, unsigned int size) | |
fbf0274e BH |
300 | { |
301 | if (mpic->flags & MPIC_USES_DCR) | |
5a2642f6 | 302 | _mpic_map_dcr(mpic, node, rb, offset, size); |
fbf0274e BH |
303 | else |
304 | _mpic_map_mmio(mpic, phys_addr, rb, offset, size); | |
305 | } | |
306 | #else /* CONFIG_PPC_DCR */ | |
5a2642f6 | 307 | #define mpic_map(m,n,p,b,o,s) _mpic_map_mmio(m,p,b,o,s) |
fbf0274e BH |
308 | #endif /* !CONFIG_PPC_DCR */ |
309 | ||
310 | ||
14cf11af PM |
311 | |
312 | /* Check if we have one of those nice broken MPICs with a flipped endian on | |
313 | * reads from IPI registers | |
314 | */ | |
315 | static void __init mpic_test_broken_ipi(struct mpic *mpic) | |
316 | { | |
317 | u32 r; | |
318 | ||
7233593b ZR |
319 | mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK); |
320 | r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0)); | |
14cf11af PM |
321 | |
322 | if (r == le32_to_cpu(MPIC_VECPRI_MASK)) { | |
323 | printk(KERN_INFO "mpic: Detected reversed IPI registers\n"); | |
324 | mpic->flags |= MPIC_BROKEN_IPI; | |
325 | } | |
326 | } | |
327 | ||
6cfef5b2 | 328 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
14cf11af PM |
329 | |
330 | /* Test if an interrupt is sourced from HyperTransport (used on broken U3s) | |
331 | * to force the edge setting on the MPIC and do the ack workaround. | |
332 | */ | |
1beb6a7d | 333 | static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) |
14cf11af | 334 | { |
1beb6a7d | 335 | if (source >= 128 || !mpic->fixups) |
14cf11af | 336 | return 0; |
1beb6a7d | 337 | return mpic->fixups[source].base != NULL; |
14cf11af PM |
338 | } |
339 | ||
c4b22f26 | 340 | |
1beb6a7d | 341 | static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source) |
14cf11af | 342 | { |
1beb6a7d | 343 | struct mpic_irq_fixup *fixup = &mpic->fixups[source]; |
14cf11af | 344 | |
1beb6a7d BH |
345 | if (fixup->applebase) { |
346 | unsigned int soff = (fixup->index >> 3) & ~3; | |
347 | unsigned int mask = 1U << (fixup->index & 0x1f); | |
348 | writel(mask, fixup->applebase + soff); | |
349 | } else { | |
350 | spin_lock(&mpic->fixup_lock); | |
351 | writeb(0x11 + 2 * fixup->index, fixup->base + 2); | |
352 | writel(fixup->data, fixup->base + 4); | |
353 | spin_unlock(&mpic->fixup_lock); | |
354 | } | |
14cf11af PM |
355 | } |
356 | ||
1beb6a7d BH |
357 | static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source, |
358 | unsigned int irqflags) | |
359 | { | |
360 | struct mpic_irq_fixup *fixup = &mpic->fixups[source]; | |
361 | unsigned long flags; | |
362 | u32 tmp; | |
363 | ||
364 | if (fixup->base == NULL) | |
365 | return; | |
366 | ||
06fe98e6 | 367 | DBG("startup_ht_interrupt(0x%x, 0x%x) index: %d\n", |
1beb6a7d BH |
368 | source, irqflags, fixup->index); |
369 | spin_lock_irqsave(&mpic->fixup_lock, flags); | |
370 | /* Enable and configure */ | |
371 | writeb(0x10 + 2 * fixup->index, fixup->base + 2); | |
372 | tmp = readl(fixup->base + 4); | |
373 | tmp &= ~(0x23U); | |
374 | if (irqflags & IRQ_LEVEL) | |
375 | tmp |= 0x22; | |
376 | writel(tmp, fixup->base + 4); | |
377 | spin_unlock_irqrestore(&mpic->fixup_lock, flags); | |
3669e930 JB |
378 | |
379 | #ifdef CONFIG_PM | |
380 | /* use the lowest bit inverted to the actual HW, | |
381 | * set if this fixup was enabled, clear otherwise */ | |
382 | mpic->save_data[source].fixup_data = tmp | 1; | |
383 | #endif | |
1beb6a7d BH |
384 | } |
385 | ||
386 | static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source, | |
387 | unsigned int irqflags) | |
388 | { | |
389 | struct mpic_irq_fixup *fixup = &mpic->fixups[source]; | |
390 | unsigned long flags; | |
391 | u32 tmp; | |
392 | ||
393 | if (fixup->base == NULL) | |
394 | return; | |
395 | ||
06fe98e6 | 396 | DBG("shutdown_ht_interrupt(0x%x, 0x%x)\n", source, irqflags); |
1beb6a7d BH |
397 | |
398 | /* Disable */ | |
399 | spin_lock_irqsave(&mpic->fixup_lock, flags); | |
400 | writeb(0x10 + 2 * fixup->index, fixup->base + 2); | |
401 | tmp = readl(fixup->base + 4); | |
72b13819 | 402 | tmp |= 1; |
1beb6a7d BH |
403 | writel(tmp, fixup->base + 4); |
404 | spin_unlock_irqrestore(&mpic->fixup_lock, flags); | |
3669e930 JB |
405 | |
406 | #ifdef CONFIG_PM | |
407 | /* use the lowest bit inverted to the actual HW, | |
408 | * set if this fixup was enabled, clear otherwise */ | |
409 | mpic->save_data[source].fixup_data = tmp & ~1; | |
410 | #endif | |
1beb6a7d | 411 | } |
14cf11af | 412 | |
812fd1fd ME |
413 | #ifdef CONFIG_PCI_MSI |
414 | static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase, | |
415 | unsigned int devfn) | |
416 | { | |
417 | u8 __iomem *base; | |
418 | u8 pos, flags; | |
419 | u64 addr = 0; | |
420 | ||
421 | for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0; | |
422 | pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) { | |
423 | u8 id = readb(devbase + pos + PCI_CAP_LIST_ID); | |
424 | if (id == PCI_CAP_ID_HT) { | |
425 | id = readb(devbase + pos + 3); | |
426 | if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING) | |
427 | break; | |
428 | } | |
429 | } | |
430 | ||
431 | if (pos == 0) | |
432 | return; | |
433 | ||
434 | base = devbase + pos; | |
435 | ||
436 | flags = readb(base + HT_MSI_FLAGS); | |
437 | if (!(flags & HT_MSI_FLAGS_FIXED)) { | |
438 | addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK; | |
439 | addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32); | |
440 | } | |
441 | ||
fe333321 | 442 | printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%llx\n", |
812fd1fd ME |
443 | PCI_SLOT(devfn), PCI_FUNC(devfn), |
444 | flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr); | |
445 | ||
446 | if (!(flags & HT_MSI_FLAGS_ENABLE)) | |
447 | writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS); | |
448 | } | |
449 | #else | |
450 | static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase, | |
451 | unsigned int devfn) | |
452 | { | |
453 | return; | |
454 | } | |
455 | #endif | |
456 | ||
1beb6a7d BH |
457 | static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase, |
458 | unsigned int devfn, u32 vdid) | |
14cf11af | 459 | { |
c4b22f26 | 460 | int i, irq, n; |
1beb6a7d | 461 | u8 __iomem *base; |
14cf11af | 462 | u32 tmp; |
c4b22f26 | 463 | u8 pos; |
14cf11af | 464 | |
1beb6a7d BH |
465 | for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0; |
466 | pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) { | |
467 | u8 id = readb(devbase + pos + PCI_CAP_LIST_ID); | |
46ff3463 | 468 | if (id == PCI_CAP_ID_HT) { |
c4b22f26 | 469 | id = readb(devbase + pos + 3); |
beb7cc82 | 470 | if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ) |
c4b22f26 SB |
471 | break; |
472 | } | |
14cf11af | 473 | } |
c4b22f26 SB |
474 | if (pos == 0) |
475 | return; | |
476 | ||
1beb6a7d BH |
477 | base = devbase + pos; |
478 | writeb(0x01, base + 2); | |
479 | n = (readl(base + 4) >> 16) & 0xff; | |
14cf11af | 480 | |
1beb6a7d BH |
481 | printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x" |
482 | " has %d irqs\n", | |
483 | devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1); | |
c4b22f26 SB |
484 | |
485 | for (i = 0; i <= n; i++) { | |
1beb6a7d BH |
486 | writeb(0x10 + 2 * i, base + 2); |
487 | tmp = readl(base + 4); | |
14cf11af | 488 | irq = (tmp >> 16) & 0xff; |
1beb6a7d BH |
489 | DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp); |
490 | /* mask it , will be unmasked later */ | |
491 | tmp |= 0x1; | |
492 | writel(tmp, base + 4); | |
493 | mpic->fixups[irq].index = i; | |
494 | mpic->fixups[irq].base = base; | |
495 | /* Apple HT PIC has a non-standard way of doing EOIs */ | |
496 | if ((vdid & 0xffff) == 0x106b) | |
497 | mpic->fixups[irq].applebase = devbase + 0x60; | |
498 | else | |
499 | mpic->fixups[irq].applebase = NULL; | |
500 | writeb(0x11 + 2 * i, base + 2); | |
501 | mpic->fixups[irq].data = readl(base + 4) | 0x80000000; | |
14cf11af PM |
502 | } |
503 | } | |
504 | ||
c4b22f26 | 505 | |
1beb6a7d | 506 | static void __init mpic_scan_ht_pics(struct mpic *mpic) |
14cf11af PM |
507 | { |
508 | unsigned int devfn; | |
509 | u8 __iomem *cfgspace; | |
510 | ||
1beb6a7d | 511 | printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n"); |
14cf11af PM |
512 | |
513 | /* Allocate fixups array */ | |
ea96025a | 514 | mpic->fixups = kzalloc(128 * sizeof(*mpic->fixups), GFP_KERNEL); |
14cf11af | 515 | BUG_ON(mpic->fixups == NULL); |
14cf11af PM |
516 | |
517 | /* Init spinlock */ | |
518 | spin_lock_init(&mpic->fixup_lock); | |
519 | ||
c4b22f26 SB |
520 | /* Map U3 config space. We assume all IO-APICs are on the primary bus |
521 | * so we only need to map 64kB. | |
14cf11af | 522 | */ |
c4b22f26 | 523 | cfgspace = ioremap(0xf2000000, 0x10000); |
14cf11af PM |
524 | BUG_ON(cfgspace == NULL); |
525 | ||
1beb6a7d BH |
526 | /* Now we scan all slots. We do a very quick scan, we read the header |
527 | * type, vendor ID and device ID only, that's plenty enough | |
14cf11af | 528 | */ |
c4b22f26 | 529 | for (devfn = 0; devfn < 0x100; devfn++) { |
14cf11af PM |
530 | u8 __iomem *devbase = cfgspace + (devfn << 8); |
531 | u8 hdr_type = readb(devbase + PCI_HEADER_TYPE); | |
532 | u32 l = readl(devbase + PCI_VENDOR_ID); | |
1beb6a7d | 533 | u16 s; |
14cf11af PM |
534 | |
535 | DBG("devfn %x, l: %x\n", devfn, l); | |
536 | ||
537 | /* If no device, skip */ | |
538 | if (l == 0xffffffff || l == 0x00000000 || | |
539 | l == 0x0000ffff || l == 0xffff0000) | |
540 | goto next; | |
1beb6a7d BH |
541 | /* Check if is supports capability lists */ |
542 | s = readw(devbase + PCI_STATUS); | |
543 | if (!(s & PCI_STATUS_CAP_LIST)) | |
544 | goto next; | |
14cf11af | 545 | |
1beb6a7d | 546 | mpic_scan_ht_pic(mpic, devbase, devfn, l); |
812fd1fd | 547 | mpic_scan_ht_msi(mpic, devbase, devfn); |
c4b22f26 | 548 | |
14cf11af PM |
549 | next: |
550 | /* next device, if function 0 */ | |
c4b22f26 | 551 | if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0) |
14cf11af PM |
552 | devfn += 7; |
553 | } | |
554 | } | |
555 | ||
6cfef5b2 | 556 | #else /* CONFIG_MPIC_U3_HT_IRQS */ |
6e99e458 BH |
557 | |
558 | static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) | |
559 | { | |
560 | return 0; | |
561 | } | |
562 | ||
563 | static void __init mpic_scan_ht_pics(struct mpic *mpic) | |
564 | { | |
565 | } | |
566 | ||
6cfef5b2 | 567 | #endif /* CONFIG_MPIC_U3_HT_IRQS */ |
14cf11af | 568 | |
3c10c9c4 | 569 | #ifdef CONFIG_SMP |
38e1313f | 570 | static int irq_choose_cpu(const cpumask_t *mask) |
3c10c9c4 | 571 | { |
3c10c9c4 KG |
572 | int cpuid; |
573 | ||
38e1313f | 574 | if (cpumask_equal(mask, cpu_all_mask)) { |
3c10c9c4 KG |
575 | static int irq_rover; |
576 | static DEFINE_SPINLOCK(irq_rover_lock); | |
577 | unsigned long flags; | |
578 | ||
579 | /* Round-robin distribution... */ | |
580 | do_round_robin: | |
581 | spin_lock_irqsave(&irq_rover_lock, flags); | |
582 | ||
583 | while (!cpu_online(irq_rover)) { | |
584 | if (++irq_rover >= NR_CPUS) | |
585 | irq_rover = 0; | |
586 | } | |
587 | cpuid = irq_rover; | |
588 | do { | |
589 | if (++irq_rover >= NR_CPUS) | |
590 | irq_rover = 0; | |
591 | } while (!cpu_online(irq_rover)); | |
592 | ||
593 | spin_unlock_irqrestore(&irq_rover_lock, flags); | |
594 | } else { | |
38e1313f YL |
595 | cpuid = cpumask_first_and(mask, cpu_online_mask); |
596 | if (cpuid >= nr_cpu_ids) | |
3c10c9c4 | 597 | goto do_round_robin; |
3c10c9c4 KG |
598 | } |
599 | ||
7a0d7940 | 600 | return get_hard_smp_processor_id(cpuid); |
3c10c9c4 KG |
601 | } |
602 | #else | |
38e1313f | 603 | static int irq_choose_cpu(const cpumask_t *mask) |
3c10c9c4 KG |
604 | { |
605 | return hard_smp_processor_id(); | |
606 | } | |
607 | #endif | |
14cf11af | 608 | |
0ebfff14 BH |
609 | #define mpic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq) |
610 | ||
14cf11af | 611 | /* Find an mpic associated with a given linux interrupt */ |
d69a78d7 | 612 | static struct mpic *mpic_find(unsigned int irq) |
14cf11af | 613 | { |
0ebfff14 BH |
614 | if (irq < NUM_ISA_INTERRUPTS) |
615 | return NULL; | |
7df2457d | 616 | |
6cff46f4 | 617 | return irq_to_desc(irq)->chip_data; |
d69a78d7 | 618 | } |
7df2457d | 619 | |
d69a78d7 TB |
620 | /* Determine if the linux irq is an IPI */ |
621 | static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq) | |
622 | { | |
623 | unsigned int src = mpic_irq_to_hw(irq); | |
0ebfff14 | 624 | |
d69a78d7 | 625 | return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]); |
14cf11af PM |
626 | } |
627 | ||
d69a78d7 | 628 | |
14cf11af PM |
629 | /* Convert a cpu mask from logical to physical cpu numbers. */ |
630 | static inline u32 mpic_physmask(u32 cpumask) | |
631 | { | |
632 | int i; | |
633 | u32 mask = 0; | |
634 | ||
635 | for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1) | |
636 | mask |= (cpumask & 1) << get_hard_smp_processor_id(i); | |
637 | return mask; | |
638 | } | |
639 | ||
640 | #ifdef CONFIG_SMP | |
641 | /* Get the mpic structure from the IPI number */ | |
642 | static inline struct mpic * mpic_from_ipi(unsigned int ipi) | |
643 | { | |
6cff46f4 | 644 | return irq_to_desc(ipi)->chip_data; |
14cf11af PM |
645 | } |
646 | #endif | |
647 | ||
648 | /* Get the mpic structure from the irq number */ | |
649 | static inline struct mpic * mpic_from_irq(unsigned int irq) | |
650 | { | |
6cff46f4 | 651 | return irq_to_desc(irq)->chip_data; |
14cf11af PM |
652 | } |
653 | ||
654 | /* Send an EOI */ | |
655 | static inline void mpic_eoi(struct mpic *mpic) | |
656 | { | |
7233593b ZR |
657 | mpic_cpu_write(MPIC_INFO(CPU_EOI), 0); |
658 | (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI)); | |
14cf11af PM |
659 | } |
660 | ||
14cf11af PM |
661 | /* |
662 | * Linux descriptor level callbacks | |
663 | */ | |
664 | ||
665 | ||
05af7bd2 | 666 | void mpic_unmask_irq(unsigned int irq) |
14cf11af PM |
667 | { |
668 | unsigned int loops = 100000; | |
669 | struct mpic *mpic = mpic_from_irq(irq); | |
0ebfff14 | 670 | unsigned int src = mpic_irq_to_hw(irq); |
14cf11af | 671 | |
bd561c79 | 672 | DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src); |
14cf11af | 673 | |
7233593b ZR |
674 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), |
675 | mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & | |
e5356640 | 676 | ~MPIC_VECPRI_MASK); |
14cf11af PM |
677 | /* make sure mask gets to controller before we return to user */ |
678 | do { | |
679 | if (!loops--) { | |
680 | printk(KERN_ERR "mpic_enable_irq timeout\n"); | |
681 | break; | |
682 | } | |
7233593b | 683 | } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK); |
14cf11af PM |
684 | } |
685 | ||
05af7bd2 | 686 | void mpic_mask_irq(unsigned int irq) |
14cf11af PM |
687 | { |
688 | unsigned int loops = 100000; | |
689 | struct mpic *mpic = mpic_from_irq(irq); | |
0ebfff14 | 690 | unsigned int src = mpic_irq_to_hw(irq); |
14cf11af PM |
691 | |
692 | DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src); | |
693 | ||
7233593b ZR |
694 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), |
695 | mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) | | |
e5356640 | 696 | MPIC_VECPRI_MASK); |
14cf11af PM |
697 | |
698 | /* make sure mask gets to controller before we return to user */ | |
699 | do { | |
700 | if (!loops--) { | |
701 | printk(KERN_ERR "mpic_enable_irq timeout\n"); | |
702 | break; | |
703 | } | |
7233593b | 704 | } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK)); |
14cf11af PM |
705 | } |
706 | ||
05af7bd2 | 707 | void mpic_end_irq(unsigned int irq) |
1beb6a7d | 708 | { |
b9e5b4e6 BH |
709 | struct mpic *mpic = mpic_from_irq(irq); |
710 | ||
711 | #ifdef DEBUG_IRQ | |
712 | DBG("%s: end_irq: %d\n", mpic->name, irq); | |
713 | #endif | |
714 | /* We always EOI on end_irq() even for edge interrupts since that | |
715 | * should only lower the priority, the MPIC should have properly | |
716 | * latched another edge interrupt coming in anyway | |
717 | */ | |
718 | ||
719 | mpic_eoi(mpic); | |
720 | } | |
721 | ||
6cfef5b2 | 722 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
b9e5b4e6 BH |
723 | |
724 | static void mpic_unmask_ht_irq(unsigned int irq) | |
725 | { | |
1beb6a7d | 726 | struct mpic *mpic = mpic_from_irq(irq); |
0ebfff14 | 727 | unsigned int src = mpic_irq_to_hw(irq); |
1beb6a7d | 728 | |
b9e5b4e6 | 729 | mpic_unmask_irq(irq); |
1beb6a7d | 730 | |
6cff46f4 | 731 | if (irq_to_desc(irq)->status & IRQ_LEVEL) |
b9e5b4e6 BH |
732 | mpic_ht_end_irq(mpic, src); |
733 | } | |
734 | ||
735 | static unsigned int mpic_startup_ht_irq(unsigned int irq) | |
736 | { | |
737 | struct mpic *mpic = mpic_from_irq(irq); | |
0ebfff14 | 738 | unsigned int src = mpic_irq_to_hw(irq); |
1beb6a7d | 739 | |
b9e5b4e6 | 740 | mpic_unmask_irq(irq); |
6cff46f4 | 741 | mpic_startup_ht_interrupt(mpic, src, irq_to_desc(irq)->status); |
b9e5b4e6 BH |
742 | |
743 | return 0; | |
1beb6a7d BH |
744 | } |
745 | ||
b9e5b4e6 BH |
746 | static void mpic_shutdown_ht_irq(unsigned int irq) |
747 | { | |
748 | struct mpic *mpic = mpic_from_irq(irq); | |
0ebfff14 | 749 | unsigned int src = mpic_irq_to_hw(irq); |
b9e5b4e6 | 750 | |
6cff46f4 | 751 | mpic_shutdown_ht_interrupt(mpic, src, irq_to_desc(irq)->status); |
b9e5b4e6 BH |
752 | mpic_mask_irq(irq); |
753 | } | |
754 | ||
755 | static void mpic_end_ht_irq(unsigned int irq) | |
14cf11af PM |
756 | { |
757 | struct mpic *mpic = mpic_from_irq(irq); | |
0ebfff14 | 758 | unsigned int src = mpic_irq_to_hw(irq); |
14cf11af | 759 | |
1beb6a7d | 760 | #ifdef DEBUG_IRQ |
14cf11af | 761 | DBG("%s: end_irq: %d\n", mpic->name, irq); |
1beb6a7d | 762 | #endif |
14cf11af PM |
763 | /* We always EOI on end_irq() even for edge interrupts since that |
764 | * should only lower the priority, the MPIC should have properly | |
765 | * latched another edge interrupt coming in anyway | |
766 | */ | |
767 | ||
6cff46f4 | 768 | if (irq_to_desc(irq)->status & IRQ_LEVEL) |
b9e5b4e6 | 769 | mpic_ht_end_irq(mpic, src); |
14cf11af PM |
770 | mpic_eoi(mpic); |
771 | } | |
6cfef5b2 | 772 | #endif /* !CONFIG_MPIC_U3_HT_IRQS */ |
b9e5b4e6 | 773 | |
14cf11af PM |
774 | #ifdef CONFIG_SMP |
775 | ||
b9e5b4e6 | 776 | static void mpic_unmask_ipi(unsigned int irq) |
14cf11af PM |
777 | { |
778 | struct mpic *mpic = mpic_from_ipi(irq); | |
7df2457d | 779 | unsigned int src = mpic_irq_to_hw(irq) - mpic->ipi_vecs[0]; |
14cf11af PM |
780 | |
781 | DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, irq, src); | |
782 | mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK); | |
783 | } | |
784 | ||
b9e5b4e6 | 785 | static void mpic_mask_ipi(unsigned int irq) |
14cf11af PM |
786 | { |
787 | /* NEVER disable an IPI... that's just plain wrong! */ | |
788 | } | |
789 | ||
790 | static void mpic_end_ipi(unsigned int irq) | |
791 | { | |
792 | struct mpic *mpic = mpic_from_ipi(irq); | |
793 | ||
794 | /* | |
795 | * IPIs are marked IRQ_PER_CPU. This has the side effect of | |
796 | * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from | |
797 | * applying to them. We EOI them late to avoid re-entering. | |
6714465e | 798 | * We mark IPI's with IRQF_DISABLED as they must run with |
14cf11af PM |
799 | * irqs disabled. |
800 | */ | |
801 | mpic_eoi(mpic); | |
802 | } | |
803 | ||
804 | #endif /* CONFIG_SMP */ | |
805 | ||
d5dedd45 | 806 | int mpic_set_affinity(unsigned int irq, const struct cpumask *cpumask) |
14cf11af PM |
807 | { |
808 | struct mpic *mpic = mpic_from_irq(irq); | |
0ebfff14 | 809 | unsigned int src = mpic_irq_to_hw(irq); |
14cf11af | 810 | |
3c10c9c4 | 811 | if (mpic->flags & MPIC_SINGLE_DEST_CPU) { |
38e1313f | 812 | int cpuid = irq_choose_cpu(cpumask); |
14cf11af | 813 | |
3c10c9c4 KG |
814 | mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid); |
815 | } else { | |
816 | cpumask_t tmp; | |
14cf11af | 817 | |
0de26520 | 818 | cpumask_and(&tmp, cpumask, cpu_online_mask); |
3c10c9c4 KG |
819 | |
820 | mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), | |
821 | mpic_physmask(cpus_addr(tmp)[0])); | |
822 | } | |
d5dedd45 YL |
823 | |
824 | return 0; | |
14cf11af PM |
825 | } |
826 | ||
7233593b | 827 | static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type) |
0ebfff14 | 828 | { |
0ebfff14 | 829 | /* Now convert sense value */ |
6e99e458 | 830 | switch(type & IRQ_TYPE_SENSE_MASK) { |
0ebfff14 | 831 | case IRQ_TYPE_EDGE_RISING: |
7233593b ZR |
832 | return MPIC_INFO(VECPRI_SENSE_EDGE) | |
833 | MPIC_INFO(VECPRI_POLARITY_POSITIVE); | |
0ebfff14 | 834 | case IRQ_TYPE_EDGE_FALLING: |
6e99e458 | 835 | case IRQ_TYPE_EDGE_BOTH: |
7233593b ZR |
836 | return MPIC_INFO(VECPRI_SENSE_EDGE) | |
837 | MPIC_INFO(VECPRI_POLARITY_NEGATIVE); | |
0ebfff14 | 838 | case IRQ_TYPE_LEVEL_HIGH: |
7233593b ZR |
839 | return MPIC_INFO(VECPRI_SENSE_LEVEL) | |
840 | MPIC_INFO(VECPRI_POLARITY_POSITIVE); | |
0ebfff14 BH |
841 | case IRQ_TYPE_LEVEL_LOW: |
842 | default: | |
7233593b ZR |
843 | return MPIC_INFO(VECPRI_SENSE_LEVEL) | |
844 | MPIC_INFO(VECPRI_POLARITY_NEGATIVE); | |
0ebfff14 | 845 | } |
6e99e458 BH |
846 | } |
847 | ||
05af7bd2 | 848 | int mpic_set_irq_type(unsigned int virq, unsigned int flow_type) |
6e99e458 BH |
849 | { |
850 | struct mpic *mpic = mpic_from_irq(virq); | |
851 | unsigned int src = mpic_irq_to_hw(virq); | |
6cff46f4 | 852 | struct irq_desc *desc = irq_to_desc(virq); |
6e99e458 BH |
853 | unsigned int vecpri, vold, vnew; |
854 | ||
06fe98e6 BH |
855 | DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n", |
856 | mpic, virq, src, flow_type); | |
6e99e458 BH |
857 | |
858 | if (src >= mpic->irq_count) | |
859 | return -EINVAL; | |
860 | ||
861 | if (flow_type == IRQ_TYPE_NONE) | |
862 | if (mpic->senses && src < mpic->senses_count) | |
863 | flow_type = mpic->senses[src]; | |
864 | if (flow_type == IRQ_TYPE_NONE) | |
865 | flow_type = IRQ_TYPE_LEVEL_LOW; | |
866 | ||
867 | desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); | |
868 | desc->status |= flow_type & IRQ_TYPE_SENSE_MASK; | |
869 | if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) | |
870 | desc->status |= IRQ_LEVEL; | |
871 | ||
872 | if (mpic_is_ht_interrupt(mpic, src)) | |
873 | vecpri = MPIC_VECPRI_POLARITY_POSITIVE | | |
874 | MPIC_VECPRI_SENSE_EDGE; | |
875 | else | |
7233593b | 876 | vecpri = mpic_type_to_vecpri(mpic, flow_type); |
6e99e458 | 877 | |
7233593b ZR |
878 | vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); |
879 | vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) | | |
880 | MPIC_INFO(VECPRI_SENSE_MASK)); | |
6e99e458 BH |
881 | vnew |= vecpri; |
882 | if (vold != vnew) | |
7233593b | 883 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew); |
6e99e458 BH |
884 | |
885 | return 0; | |
0ebfff14 BH |
886 | } |
887 | ||
38958dd9 OJ |
888 | void mpic_set_vector(unsigned int virq, unsigned int vector) |
889 | { | |
890 | struct mpic *mpic = mpic_from_irq(virq); | |
891 | unsigned int src = mpic_irq_to_hw(virq); | |
892 | unsigned int vecpri; | |
893 | ||
894 | DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n", | |
895 | mpic, virq, src, vector); | |
896 | ||
897 | if (src >= mpic->irq_count) | |
898 | return; | |
899 | ||
900 | vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); | |
901 | vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK); | |
902 | vecpri |= vector; | |
903 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); | |
904 | } | |
905 | ||
b9e5b4e6 | 906 | static struct irq_chip mpic_irq_chip = { |
6e99e458 BH |
907 | .mask = mpic_mask_irq, |
908 | .unmask = mpic_unmask_irq, | |
909 | .eoi = mpic_end_irq, | |
910 | .set_type = mpic_set_irq_type, | |
b9e5b4e6 BH |
911 | }; |
912 | ||
913 | #ifdef CONFIG_SMP | |
914 | static struct irq_chip mpic_ipi_chip = { | |
6e99e458 BH |
915 | .mask = mpic_mask_ipi, |
916 | .unmask = mpic_unmask_ipi, | |
917 | .eoi = mpic_end_ipi, | |
b9e5b4e6 BH |
918 | }; |
919 | #endif /* CONFIG_SMP */ | |
920 | ||
6cfef5b2 | 921 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
b9e5b4e6 BH |
922 | static struct irq_chip mpic_irq_ht_chip = { |
923 | .startup = mpic_startup_ht_irq, | |
924 | .shutdown = mpic_shutdown_ht_irq, | |
925 | .mask = mpic_mask_irq, | |
926 | .unmask = mpic_unmask_ht_irq, | |
927 | .eoi = mpic_end_ht_irq, | |
6e99e458 | 928 | .set_type = mpic_set_irq_type, |
b9e5b4e6 | 929 | }; |
6cfef5b2 | 930 | #endif /* CONFIG_MPIC_U3_HT_IRQS */ |
b9e5b4e6 | 931 | |
14cf11af | 932 | |
0ebfff14 BH |
933 | static int mpic_host_match(struct irq_host *h, struct device_node *node) |
934 | { | |
0ebfff14 | 935 | /* Exact match, unless mpic node is NULL */ |
52964f87 | 936 | return h->of_node == NULL || h->of_node == node; |
0ebfff14 BH |
937 | } |
938 | ||
939 | static int mpic_host_map(struct irq_host *h, unsigned int virq, | |
6e99e458 | 940 | irq_hw_number_t hw) |
0ebfff14 | 941 | { |
0ebfff14 | 942 | struct mpic *mpic = h->host_data; |
6e99e458 | 943 | struct irq_chip *chip; |
0ebfff14 | 944 | |
06fe98e6 | 945 | DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw); |
0ebfff14 | 946 | |
7df2457d | 947 | if (hw == mpic->spurious_vec) |
0ebfff14 | 948 | return -EINVAL; |
7fd72186 BH |
949 | if (mpic->protected && test_bit(hw, mpic->protected)) |
950 | return -EINVAL; | |
06fe98e6 | 951 | |
0ebfff14 | 952 | #ifdef CONFIG_SMP |
7df2457d | 953 | else if (hw >= mpic->ipi_vecs[0]) { |
0ebfff14 BH |
954 | WARN_ON(!(mpic->flags & MPIC_PRIMARY)); |
955 | ||
06fe98e6 | 956 | DBG("mpic: mapping as IPI\n"); |
0ebfff14 BH |
957 | set_irq_chip_data(virq, mpic); |
958 | set_irq_chip_and_handler(virq, &mpic->hc_ipi, | |
959 | handle_percpu_irq); | |
960 | return 0; | |
961 | } | |
962 | #endif /* CONFIG_SMP */ | |
963 | ||
964 | if (hw >= mpic->irq_count) | |
965 | return -EINVAL; | |
966 | ||
a7de7c74 ME |
967 | mpic_msi_reserve_hwirq(mpic, hw); |
968 | ||
6e99e458 | 969 | /* Default chip */ |
0ebfff14 BH |
970 | chip = &mpic->hc_irq; |
971 | ||
6cfef5b2 | 972 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
0ebfff14 | 973 | /* Check for HT interrupts, override vecpri */ |
6e99e458 | 974 | if (mpic_is_ht_interrupt(mpic, hw)) |
0ebfff14 | 975 | chip = &mpic->hc_ht_irq; |
6cfef5b2 | 976 | #endif /* CONFIG_MPIC_U3_HT_IRQS */ |
0ebfff14 | 977 | |
06fe98e6 | 978 | DBG("mpic: mapping to irq chip @%p\n", chip); |
0ebfff14 BH |
979 | |
980 | set_irq_chip_data(virq, mpic); | |
981 | set_irq_chip_and_handler(virq, chip, handle_fasteoi_irq); | |
6e99e458 BH |
982 | |
983 | /* Set default irq type */ | |
984 | set_irq_type(virq, IRQ_TYPE_NONE); | |
985 | ||
0ebfff14 BH |
986 | return 0; |
987 | } | |
988 | ||
989 | static int mpic_host_xlate(struct irq_host *h, struct device_node *ct, | |
40d50cf7 | 990 | const u32 *intspec, unsigned int intsize, |
0ebfff14 BH |
991 | irq_hw_number_t *out_hwirq, unsigned int *out_flags) |
992 | ||
993 | { | |
994 | static unsigned char map_mpic_senses[4] = { | |
995 | IRQ_TYPE_EDGE_RISING, | |
996 | IRQ_TYPE_LEVEL_LOW, | |
997 | IRQ_TYPE_LEVEL_HIGH, | |
998 | IRQ_TYPE_EDGE_FALLING, | |
999 | }; | |
1000 | ||
1001 | *out_hwirq = intspec[0]; | |
06fe98e6 BH |
1002 | if (intsize > 1) { |
1003 | u32 mask = 0x3; | |
1004 | ||
1005 | /* Apple invented a new race of encoding on machines with | |
1006 | * an HT APIC. They encode, among others, the index within | |
1007 | * the HT APIC. We don't care about it here since thankfully, | |
1008 | * it appears that they have the APIC already properly | |
1009 | * configured, and thus our current fixup code that reads the | |
1010 | * APIC config works fine. However, we still need to mask out | |
1011 | * bits in the specifier to make sure we only get bit 0 which | |
1012 | * is the level/edge bit (the only sense bit exposed by Apple), | |
1013 | * as their bit 1 means something else. | |
1014 | */ | |
1015 | if (machine_is(powermac)) | |
1016 | mask = 0x1; | |
1017 | *out_flags = map_mpic_senses[intspec[1] & mask]; | |
1018 | } else | |
0ebfff14 BH |
1019 | *out_flags = IRQ_TYPE_NONE; |
1020 | ||
06fe98e6 BH |
1021 | DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n", |
1022 | intsize, intspec[0], intspec[1], *out_hwirq, *out_flags); | |
1023 | ||
0ebfff14 BH |
1024 | return 0; |
1025 | } | |
1026 | ||
1027 | static struct irq_host_ops mpic_host_ops = { | |
1028 | .match = mpic_host_match, | |
1029 | .map = mpic_host_map, | |
1030 | .xlate = mpic_host_xlate, | |
1031 | }; | |
1032 | ||
14cf11af PM |
1033 | /* |
1034 | * Exported functions | |
1035 | */ | |
1036 | ||
0ebfff14 | 1037 | struct mpic * __init mpic_alloc(struct device_node *node, |
a959ff56 | 1038 | phys_addr_t phys_addr, |
14cf11af PM |
1039 | unsigned int flags, |
1040 | unsigned int isu_size, | |
14cf11af | 1041 | unsigned int irq_count, |
14cf11af PM |
1042 | const char *name) |
1043 | { | |
1044 | struct mpic *mpic; | |
d9d1063d | 1045 | u32 greg_feature; |
14cf11af PM |
1046 | const char *vers; |
1047 | int i; | |
7df2457d | 1048 | int intvec_top; |
a959ff56 | 1049 | u64 paddr = phys_addr; |
14cf11af | 1050 | |
85355bb2 | 1051 | mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL); |
14cf11af PM |
1052 | if (mpic == NULL) |
1053 | return NULL; | |
85355bb2 | 1054 | |
14cf11af PM |
1055 | mpic->name = name; |
1056 | ||
b9e5b4e6 | 1057 | mpic->hc_irq = mpic_irq_chip; |
b27df672 | 1058 | mpic->hc_irq.name = name; |
14cf11af PM |
1059 | if (flags & MPIC_PRIMARY) |
1060 | mpic->hc_irq.set_affinity = mpic_set_affinity; | |
6cfef5b2 | 1061 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
b9e5b4e6 | 1062 | mpic->hc_ht_irq = mpic_irq_ht_chip; |
b27df672 | 1063 | mpic->hc_ht_irq.name = name; |
b9e5b4e6 BH |
1064 | if (flags & MPIC_PRIMARY) |
1065 | mpic->hc_ht_irq.set_affinity = mpic_set_affinity; | |
6cfef5b2 | 1066 | #endif /* CONFIG_MPIC_U3_HT_IRQS */ |
fbf0274e | 1067 | |
14cf11af | 1068 | #ifdef CONFIG_SMP |
b9e5b4e6 | 1069 | mpic->hc_ipi = mpic_ipi_chip; |
b27df672 | 1070 | mpic->hc_ipi.name = name; |
14cf11af PM |
1071 | #endif /* CONFIG_SMP */ |
1072 | ||
1073 | mpic->flags = flags; | |
1074 | mpic->isu_size = isu_size; | |
14cf11af | 1075 | mpic->irq_count = irq_count; |
14cf11af | 1076 | mpic->num_sources = 0; /* so far */ |
14cf11af | 1077 | |
7df2457d OJ |
1078 | if (flags & MPIC_LARGE_VECTORS) |
1079 | intvec_top = 2047; | |
1080 | else | |
1081 | intvec_top = 255; | |
1082 | ||
1083 | mpic->timer_vecs[0] = intvec_top - 8; | |
1084 | mpic->timer_vecs[1] = intvec_top - 7; | |
1085 | mpic->timer_vecs[2] = intvec_top - 6; | |
1086 | mpic->timer_vecs[3] = intvec_top - 5; | |
1087 | mpic->ipi_vecs[0] = intvec_top - 4; | |
1088 | mpic->ipi_vecs[1] = intvec_top - 3; | |
1089 | mpic->ipi_vecs[2] = intvec_top - 2; | |
1090 | mpic->ipi_vecs[3] = intvec_top - 1; | |
1091 | mpic->spurious_vec = intvec_top; | |
1092 | ||
a959ff56 | 1093 | /* Check for "big-endian" in device-tree */ |
e2eb6392 | 1094 | if (node && of_get_property(node, "big-endian", NULL) != NULL) |
a959ff56 BH |
1095 | mpic->flags |= MPIC_BIG_ENDIAN; |
1096 | ||
7fd72186 BH |
1097 | /* Look for protected sources */ |
1098 | if (node) { | |
d9d1063d JB |
1099 | int psize; |
1100 | unsigned int bits, mapsize; | |
7fd72186 BH |
1101 | const u32 *psrc = |
1102 | of_get_property(node, "protected-sources", &psize); | |
1103 | if (psrc) { | |
1104 | psize /= 4; | |
1105 | bits = intvec_top + 1; | |
1106 | mapsize = BITS_TO_LONGS(bits) * sizeof(unsigned long); | |
ea96025a | 1107 | mpic->protected = kzalloc(mapsize, GFP_KERNEL); |
7fd72186 | 1108 | BUG_ON(mpic->protected == NULL); |
7fd72186 BH |
1109 | for (i = 0; i < psize; i++) { |
1110 | if (psrc[i] > intvec_top) | |
1111 | continue; | |
1112 | __set_bit(psrc[i], mpic->protected); | |
1113 | } | |
1114 | } | |
1115 | } | |
a959ff56 | 1116 | |
7233593b ZR |
1117 | #ifdef CONFIG_MPIC_WEIRD |
1118 | mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)]; | |
1119 | #endif | |
1120 | ||
fbf0274e BH |
1121 | /* default register type */ |
1122 | mpic->reg_type = (flags & MPIC_BIG_ENDIAN) ? | |
1123 | mpic_access_mmio_be : mpic_access_mmio_le; | |
1124 | ||
a959ff56 BH |
1125 | /* If no physical address is passed in, a device-node is mandatory */ |
1126 | BUG_ON(paddr == 0 && node == NULL); | |
1127 | ||
1128 | /* If no physical address passed in, check if it's dcr based */ | |
0411a5e2 | 1129 | if (paddr == 0 && of_get_property(node, "dcr-reg", NULL) != NULL) { |
fbf0274e | 1130 | #ifdef CONFIG_PPC_DCR |
0411a5e2 | 1131 | mpic->flags |= MPIC_USES_DCR; |
fbf0274e | 1132 | mpic->reg_type = mpic_access_dcr; |
fbf0274e | 1133 | #else |
0411a5e2 | 1134 | BUG(); |
fbf0274e | 1135 | #endif /* CONFIG_PPC_DCR */ |
0411a5e2 | 1136 | } |
fbf0274e | 1137 | |
a959ff56 BH |
1138 | /* If the MPIC is not DCR based, and no physical address was passed |
1139 | * in, try to obtain one | |
1140 | */ | |
1141 | if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) { | |
d9d1063d | 1142 | const u32 *reg = of_get_property(node, "reg", NULL); |
a959ff56 BH |
1143 | BUG_ON(reg == NULL); |
1144 | paddr = of_translate_address(node, reg); | |
1145 | BUG_ON(paddr == OF_BAD_ADDR); | |
1146 | } | |
1147 | ||
14cf11af | 1148 | /* Map the global registers */ |
5a2642f6 BH |
1149 | mpic_map(mpic, node, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000); |
1150 | mpic_map(mpic, node, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000); | |
14cf11af PM |
1151 | |
1152 | /* Reset */ | |
1153 | if (flags & MPIC_WANTS_RESET) { | |
7233593b ZR |
1154 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), |
1155 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) | |
14cf11af | 1156 | | MPIC_GREG_GCONF_RESET); |
7233593b | 1157 | while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) |
14cf11af PM |
1158 | & MPIC_GREG_GCONF_RESET) |
1159 | mb(); | |
1160 | } | |
1161 | ||
d91e4ea7 KG |
1162 | /* CoreInt */ |
1163 | if (flags & MPIC_ENABLE_COREINT) | |
1164 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), | |
1165 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) | |
1166 | | MPIC_GREG_GCONF_COREINT); | |
1167 | ||
f365355e OJ |
1168 | if (flags & MPIC_ENABLE_MCK) |
1169 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), | |
1170 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) | |
1171 | | MPIC_GREG_GCONF_MCK); | |
1172 | ||
14cf11af PM |
1173 | /* Read feature register, calculate num CPUs and, for non-ISU |
1174 | * MPICs, num sources as well. On ISU MPICs, sources are counted | |
1175 | * as ISUs are added | |
1176 | */ | |
d9d1063d JB |
1177 | greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0)); |
1178 | mpic->num_cpus = ((greg_feature & MPIC_GREG_FEATURE_LAST_CPU_MASK) | |
14cf11af | 1179 | >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1; |
5073e7ee | 1180 | if (isu_size == 0) { |
475ca391 KG |
1181 | if (flags & MPIC_BROKEN_FRR_NIRQS) |
1182 | mpic->num_sources = mpic->irq_count; | |
1183 | else | |
1184 | mpic->num_sources = | |
1185 | ((greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK) | |
1186 | >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1; | |
5073e7ee | 1187 | } |
14cf11af PM |
1188 | |
1189 | /* Map the per-CPU registers */ | |
1190 | for (i = 0; i < mpic->num_cpus; i++) { | |
5a2642f6 | 1191 | mpic_map(mpic, node, paddr, &mpic->cpuregs[i], |
fbf0274e BH |
1192 | MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE), |
1193 | 0x1000); | |
14cf11af PM |
1194 | } |
1195 | ||
1196 | /* Initialize main ISU if none provided */ | |
1197 | if (mpic->isu_size == 0) { | |
1198 | mpic->isu_size = mpic->num_sources; | |
5a2642f6 | 1199 | mpic_map(mpic, node, paddr, &mpic->isus[0], |
fbf0274e | 1200 | MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); |
14cf11af PM |
1201 | } |
1202 | mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1); | |
1203 | mpic->isu_mask = (1 << mpic->isu_shift) - 1; | |
1204 | ||
31207dab KG |
1205 | mpic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR, |
1206 | isu_size ? isu_size : mpic->num_sources, | |
1207 | &mpic_host_ops, | |
1208 | flags & MPIC_LARGE_VECTORS ? 2048 : 256); | |
1209 | if (mpic->irqhost == NULL) | |
1210 | return NULL; | |
1211 | ||
1212 | mpic->irqhost->host_data = mpic; | |
1213 | ||
14cf11af | 1214 | /* Display version */ |
d9d1063d | 1215 | switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) { |
14cf11af PM |
1216 | case 1: |
1217 | vers = "1.0"; | |
1218 | break; | |
1219 | case 2: | |
1220 | vers = "1.2"; | |
1221 | break; | |
1222 | case 3: | |
1223 | vers = "1.3"; | |
1224 | break; | |
1225 | default: | |
1226 | vers = "<unknown>"; | |
1227 | break; | |
1228 | } | |
a959ff56 BH |
1229 | printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx," |
1230 | " max %d CPUs\n", | |
1231 | name, vers, (unsigned long long)paddr, mpic->num_cpus); | |
1232 | printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n", | |
1233 | mpic->isu_size, mpic->isu_shift, mpic->isu_mask); | |
14cf11af PM |
1234 | |
1235 | mpic->next = mpics; | |
1236 | mpics = mpic; | |
1237 | ||
0ebfff14 | 1238 | if (flags & MPIC_PRIMARY) { |
14cf11af | 1239 | mpic_primary = mpic; |
0ebfff14 BH |
1240 | irq_set_default_host(mpic->irqhost); |
1241 | } | |
14cf11af PM |
1242 | |
1243 | return mpic; | |
1244 | } | |
1245 | ||
1246 | void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num, | |
a959ff56 | 1247 | phys_addr_t paddr) |
14cf11af PM |
1248 | { |
1249 | unsigned int isu_first = isu_num * mpic->isu_size; | |
1250 | ||
1251 | BUG_ON(isu_num >= MPIC_MAX_ISU); | |
1252 | ||
5a2642f6 BH |
1253 | mpic_map(mpic, mpic->irqhost->of_node, |
1254 | paddr, &mpic->isus[isu_num], 0, | |
fbf0274e | 1255 | MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); |
5a2642f6 | 1256 | |
14cf11af PM |
1257 | if ((isu_first + mpic->isu_size) > mpic->num_sources) |
1258 | mpic->num_sources = isu_first + mpic->isu_size; | |
1259 | } | |
1260 | ||
0ebfff14 BH |
1261 | void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count) |
1262 | { | |
1263 | mpic->senses = senses; | |
1264 | mpic->senses_count = count; | |
1265 | } | |
1266 | ||
14cf11af PM |
1267 | void __init mpic_init(struct mpic *mpic) |
1268 | { | |
1269 | int i; | |
cc353c30 | 1270 | int cpu; |
14cf11af PM |
1271 | |
1272 | BUG_ON(mpic->num_sources == 0); | |
1273 | ||
1274 | printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources); | |
1275 | ||
1276 | /* Set current processor priority to max */ | |
7233593b | 1277 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf); |
14cf11af PM |
1278 | |
1279 | /* Initialize timers: just disable them all */ | |
1280 | for (i = 0; i < 4; i++) { | |
1281 | mpic_write(mpic->tmregs, | |
7233593b ZR |
1282 | i * MPIC_INFO(TIMER_STRIDE) + |
1283 | MPIC_INFO(TIMER_DESTINATION), 0); | |
14cf11af | 1284 | mpic_write(mpic->tmregs, |
7233593b ZR |
1285 | i * MPIC_INFO(TIMER_STRIDE) + |
1286 | MPIC_INFO(TIMER_VECTOR_PRI), | |
14cf11af | 1287 | MPIC_VECPRI_MASK | |
7df2457d | 1288 | (mpic->timer_vecs[0] + i)); |
14cf11af PM |
1289 | } |
1290 | ||
1291 | /* Initialize IPIs to our reserved vectors and mark them disabled for now */ | |
1292 | mpic_test_broken_ipi(mpic); | |
1293 | for (i = 0; i < 4; i++) { | |
1294 | mpic_ipi_write(i, | |
1295 | MPIC_VECPRI_MASK | | |
1296 | (10 << MPIC_VECPRI_PRIORITY_SHIFT) | | |
7df2457d | 1297 | (mpic->ipi_vecs[0] + i)); |
14cf11af PM |
1298 | } |
1299 | ||
1300 | /* Initialize interrupt sources */ | |
1301 | if (mpic->irq_count == 0) | |
1302 | mpic->irq_count = mpic->num_sources; | |
1303 | ||
1beb6a7d | 1304 | /* Do the HT PIC fixups on U3 broken mpic */ |
14cf11af | 1305 | DBG("MPIC flags: %x\n", mpic->flags); |
05af7bd2 | 1306 | if ((mpic->flags & MPIC_U3_HT_IRQS) && (mpic->flags & MPIC_PRIMARY)) { |
3669e930 | 1307 | mpic_scan_ht_pics(mpic); |
05af7bd2 ME |
1308 | mpic_u3msi_init(mpic); |
1309 | } | |
14cf11af | 1310 | |
38958dd9 OJ |
1311 | mpic_pasemi_msi_init(mpic); |
1312 | ||
cc353c30 AB |
1313 | if (mpic->flags & MPIC_PRIMARY) |
1314 | cpu = hard_smp_processor_id(); | |
1315 | else | |
1316 | cpu = 0; | |
1317 | ||
14cf11af PM |
1318 | for (i = 0; i < mpic->num_sources; i++) { |
1319 | /* start with vector = source number, and masked */ | |
6e99e458 BH |
1320 | u32 vecpri = MPIC_VECPRI_MASK | i | |
1321 | (8 << MPIC_VECPRI_PRIORITY_SHIFT); | |
14cf11af | 1322 | |
7fd72186 BH |
1323 | /* check if protected */ |
1324 | if (mpic->protected && test_bit(i, mpic->protected)) | |
1325 | continue; | |
14cf11af | 1326 | /* init hw */ |
7233593b | 1327 | mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); |
cc353c30 | 1328 | mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu); |
14cf11af PM |
1329 | } |
1330 | ||
7df2457d OJ |
1331 | /* Init spurious vector */ |
1332 | mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec); | |
14cf11af | 1333 | |
7233593b ZR |
1334 | /* Disable 8259 passthrough, if supported */ |
1335 | if (!(mpic->flags & MPIC_NO_PTHROU_DIS)) | |
1336 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), | |
1337 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) | |
1338 | | MPIC_GREG_GCONF_8259_PTHROU_DIS); | |
14cf11af | 1339 | |
d87bf3be OJ |
1340 | if (mpic->flags & MPIC_NO_BIAS) |
1341 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), | |
1342 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) | |
1343 | | MPIC_GREG_GCONF_NO_BIAS); | |
1344 | ||
14cf11af | 1345 | /* Set current processor priority to 0 */ |
7233593b | 1346 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0); |
3669e930 JB |
1347 | |
1348 | #ifdef CONFIG_PM | |
1349 | /* allocate memory to save mpic state */ | |
ea96025a AV |
1350 | mpic->save_data = kmalloc(mpic->num_sources * sizeof(*mpic->save_data), |
1351 | GFP_KERNEL); | |
3669e930 JB |
1352 | BUG_ON(mpic->save_data == NULL); |
1353 | #endif | |
14cf11af PM |
1354 | } |
1355 | ||
868ea0c9 MG |
1356 | void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio) |
1357 | { | |
1358 | u32 v; | |
1359 | ||
1360 | v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1); | |
1361 | v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK; | |
1362 | v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio); | |
1363 | mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v); | |
1364 | } | |
14cf11af | 1365 | |
868ea0c9 MG |
1366 | void __init mpic_set_serial_int(struct mpic *mpic, int enable) |
1367 | { | |
ba1826e5 | 1368 | unsigned long flags; |
868ea0c9 MG |
1369 | u32 v; |
1370 | ||
ba1826e5 | 1371 | spin_lock_irqsave(&mpic_lock, flags); |
868ea0c9 MG |
1372 | v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1); |
1373 | if (enable) | |
1374 | v |= MPIC_GREG_GLOBAL_CONF_1_SIE; | |
1375 | else | |
1376 | v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE; | |
1377 | mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v); | |
ba1826e5 | 1378 | spin_unlock_irqrestore(&mpic_lock, flags); |
868ea0c9 | 1379 | } |
14cf11af PM |
1380 | |
1381 | void mpic_irq_set_priority(unsigned int irq, unsigned int pri) | |
1382 | { | |
d69a78d7 | 1383 | struct mpic *mpic = mpic_find(irq); |
0ebfff14 | 1384 | unsigned int src = mpic_irq_to_hw(irq); |
14cf11af PM |
1385 | unsigned long flags; |
1386 | u32 reg; | |
1387 | ||
06a901c5 SR |
1388 | if (!mpic) |
1389 | return; | |
1390 | ||
14cf11af | 1391 | spin_lock_irqsave(&mpic_lock, flags); |
d69a78d7 | 1392 | if (mpic_is_ipi(mpic, irq)) { |
7df2457d | 1393 | reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) & |
e5356640 | 1394 | ~MPIC_VECPRI_PRIORITY_MASK; |
7df2457d | 1395 | mpic_ipi_write(src - mpic->ipi_vecs[0], |
14cf11af PM |
1396 | reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); |
1397 | } else { | |
7233593b | 1398 | reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
e5356640 | 1399 | & ~MPIC_VECPRI_PRIORITY_MASK; |
7233593b | 1400 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), |
14cf11af PM |
1401 | reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); |
1402 | } | |
1403 | spin_unlock_irqrestore(&mpic_lock, flags); | |
1404 | } | |
1405 | ||
14cf11af PM |
1406 | void mpic_setup_this_cpu(void) |
1407 | { | |
1408 | #ifdef CONFIG_SMP | |
1409 | struct mpic *mpic = mpic_primary; | |
1410 | unsigned long flags; | |
1411 | u32 msk = 1 << hard_smp_processor_id(); | |
1412 | unsigned int i; | |
1413 | ||
1414 | BUG_ON(mpic == NULL); | |
1415 | ||
1416 | DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); | |
1417 | ||
1418 | spin_lock_irqsave(&mpic_lock, flags); | |
1419 | ||
1420 | /* let the mpic know we want intrs. default affinity is 0xffffffff | |
1421 | * until changed via /proc. That's how it's done on x86. If we want | |
1422 | * it differently, then we should make sure we also change the default | |
a53da52f | 1423 | * values of irq_desc[].affinity in irq.c. |
14cf11af PM |
1424 | */ |
1425 | if (distribute_irqs) { | |
1426 | for (i = 0; i < mpic->num_sources ; i++) | |
7233593b ZR |
1427 | mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), |
1428 | mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk); | |
14cf11af PM |
1429 | } |
1430 | ||
1431 | /* Set current processor priority to 0 */ | |
7233593b | 1432 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0); |
14cf11af PM |
1433 | |
1434 | spin_unlock_irqrestore(&mpic_lock, flags); | |
1435 | #endif /* CONFIG_SMP */ | |
1436 | } | |
1437 | ||
1438 | int mpic_cpu_get_priority(void) | |
1439 | { | |
1440 | struct mpic *mpic = mpic_primary; | |
1441 | ||
7233593b | 1442 | return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI)); |
14cf11af PM |
1443 | } |
1444 | ||
1445 | void mpic_cpu_set_priority(int prio) | |
1446 | { | |
1447 | struct mpic *mpic = mpic_primary; | |
1448 | ||
1449 | prio &= MPIC_CPU_TASKPRI_MASK; | |
7233593b | 1450 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio); |
14cf11af PM |
1451 | } |
1452 | ||
14cf11af PM |
1453 | void mpic_teardown_this_cpu(int secondary) |
1454 | { | |
1455 | struct mpic *mpic = mpic_primary; | |
1456 | unsigned long flags; | |
1457 | u32 msk = 1 << hard_smp_processor_id(); | |
1458 | unsigned int i; | |
1459 | ||
1460 | BUG_ON(mpic == NULL); | |
1461 | ||
1462 | DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); | |
1463 | spin_lock_irqsave(&mpic_lock, flags); | |
1464 | ||
1465 | /* let the mpic know we don't want intrs. */ | |
1466 | for (i = 0; i < mpic->num_sources ; i++) | |
7233593b ZR |
1467 | mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), |
1468 | mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk); | |
14cf11af PM |
1469 | |
1470 | /* Set current processor priority to max */ | |
7233593b | 1471 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf); |
7132799b VB |
1472 | /* We need to EOI the IPI since not all platforms reset the MPIC |
1473 | * on boot and new interrupts wouldn't get delivered otherwise. | |
1474 | */ | |
1475 | mpic_eoi(mpic); | |
14cf11af PM |
1476 | |
1477 | spin_unlock_irqrestore(&mpic_lock, flags); | |
1478 | } | |
1479 | ||
1480 | ||
1481 | void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask) | |
1482 | { | |
1483 | struct mpic *mpic = mpic_primary; | |
1484 | ||
1485 | BUG_ON(mpic == NULL); | |
1486 | ||
1beb6a7d | 1487 | #ifdef DEBUG_IPI |
14cf11af | 1488 | DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no); |
1beb6a7d | 1489 | #endif |
14cf11af | 1490 | |
7233593b ZR |
1491 | mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) + |
1492 | ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE), | |
14cf11af PM |
1493 | mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0])); |
1494 | } | |
1495 | ||
f365355e | 1496 | static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg) |
14cf11af | 1497 | { |
0ebfff14 | 1498 | u32 src; |
14cf11af | 1499 | |
f365355e | 1500 | src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK); |
1beb6a7d | 1501 | #ifdef DEBUG_LOW |
f365355e | 1502 | DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src); |
1beb6a7d | 1503 | #endif |
5cddd2e3 JB |
1504 | if (unlikely(src == mpic->spurious_vec)) { |
1505 | if (mpic->flags & MPIC_SPV_EOI) | |
1506 | mpic_eoi(mpic); | |
0ebfff14 | 1507 | return NO_IRQ; |
5cddd2e3 | 1508 | } |
7fd72186 BH |
1509 | if (unlikely(mpic->protected && test_bit(src, mpic->protected))) { |
1510 | if (printk_ratelimit()) | |
1511 | printk(KERN_WARNING "%s: Got protected source %d !\n", | |
1512 | mpic->name, (int)src); | |
1513 | mpic_eoi(mpic); | |
1514 | return NO_IRQ; | |
1515 | } | |
1516 | ||
0ebfff14 | 1517 | return irq_linear_revmap(mpic->irqhost, src); |
14cf11af PM |
1518 | } |
1519 | ||
f365355e OJ |
1520 | unsigned int mpic_get_one_irq(struct mpic *mpic) |
1521 | { | |
1522 | return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK)); | |
1523 | } | |
1524 | ||
35a84c2f | 1525 | unsigned int mpic_get_irq(void) |
14cf11af PM |
1526 | { |
1527 | struct mpic *mpic = mpic_primary; | |
1528 | ||
1529 | BUG_ON(mpic == NULL); | |
1530 | ||
35a84c2f | 1531 | return mpic_get_one_irq(mpic); |
14cf11af PM |
1532 | } |
1533 | ||
d91e4ea7 KG |
1534 | unsigned int mpic_get_coreint_irq(void) |
1535 | { | |
1536 | #ifdef CONFIG_BOOKE | |
1537 | struct mpic *mpic = mpic_primary; | |
1538 | u32 src; | |
1539 | ||
1540 | BUG_ON(mpic == NULL); | |
1541 | ||
1542 | src = mfspr(SPRN_EPR); | |
1543 | ||
1544 | if (unlikely(src == mpic->spurious_vec)) { | |
1545 | if (mpic->flags & MPIC_SPV_EOI) | |
1546 | mpic_eoi(mpic); | |
1547 | return NO_IRQ; | |
1548 | } | |
1549 | if (unlikely(mpic->protected && test_bit(src, mpic->protected))) { | |
1550 | if (printk_ratelimit()) | |
1551 | printk(KERN_WARNING "%s: Got protected source %d !\n", | |
1552 | mpic->name, (int)src); | |
1553 | return NO_IRQ; | |
1554 | } | |
1555 | ||
1556 | return irq_linear_revmap(mpic->irqhost, src); | |
1557 | #else | |
1558 | return NO_IRQ; | |
1559 | #endif | |
1560 | } | |
1561 | ||
f365355e OJ |
1562 | unsigned int mpic_get_mcirq(void) |
1563 | { | |
1564 | struct mpic *mpic = mpic_primary; | |
1565 | ||
1566 | BUG_ON(mpic == NULL); | |
1567 | ||
1568 | return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK)); | |
1569 | } | |
14cf11af PM |
1570 | |
1571 | #ifdef CONFIG_SMP | |
1572 | void mpic_request_ipis(void) | |
1573 | { | |
1574 | struct mpic *mpic = mpic_primary; | |
78608dd3 | 1575 | int i; |
14cf11af | 1576 | BUG_ON(mpic == NULL); |
14cf11af | 1577 | |
0ebfff14 BH |
1578 | printk(KERN_INFO "mpic: requesting IPIs ... \n"); |
1579 | ||
1580 | for (i = 0; i < 4; i++) { | |
1581 | unsigned int vipi = irq_create_mapping(mpic->irqhost, | |
7df2457d | 1582 | mpic->ipi_vecs[0] + i); |
0ebfff14 | 1583 | if (vipi == NO_IRQ) { |
78608dd3 MM |
1584 | printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]); |
1585 | continue; | |
d16f1b64 | 1586 | } |
78608dd3 | 1587 | smp_request_message_ipi(vipi, i); |
0ebfff14 | 1588 | } |
14cf11af | 1589 | } |
a9c59264 PM |
1590 | |
1591 | void smp_mpic_message_pass(int target, int msg) | |
1592 | { | |
1593 | /* make sure we're sending something that translates to an IPI */ | |
1594 | if ((unsigned int)msg > 3) { | |
1595 | printk("SMP %d: smp_message_pass: unknown msg %d\n", | |
1596 | smp_processor_id(), msg); | |
1597 | return; | |
1598 | } | |
1599 | switch (target) { | |
1600 | case MSG_ALL: | |
1601 | mpic_send_ipi(msg, 0xffffffff); | |
1602 | break; | |
1603 | case MSG_ALL_BUT_SELF: | |
1604 | mpic_send_ipi(msg, 0xffffffff & ~(1 << smp_processor_id())); | |
1605 | break; | |
1606 | default: | |
1607 | mpic_send_ipi(msg, 1 << target); | |
1608 | break; | |
1609 | } | |
1610 | } | |
775aeff4 ME |
1611 | |
1612 | int __init smp_mpic_probe(void) | |
1613 | { | |
1614 | int nr_cpus; | |
1615 | ||
1616 | DBG("smp_mpic_probe()...\n"); | |
1617 | ||
1618 | nr_cpus = cpus_weight(cpu_possible_map); | |
1619 | ||
1620 | DBG("nr_cpus: %d\n", nr_cpus); | |
1621 | ||
1622 | if (nr_cpus > 1) | |
1623 | mpic_request_ipis(); | |
1624 | ||
1625 | return nr_cpus; | |
1626 | } | |
1627 | ||
1628 | void __devinit smp_mpic_setup_cpu(int cpu) | |
1629 | { | |
1630 | mpic_setup_this_cpu(); | |
1631 | } | |
14cf11af | 1632 | #endif /* CONFIG_SMP */ |
3669e930 JB |
1633 | |
1634 | #ifdef CONFIG_PM | |
1635 | static int mpic_suspend(struct sys_device *dev, pm_message_t state) | |
1636 | { | |
1637 | struct mpic *mpic = container_of(dev, struct mpic, sysdev); | |
1638 | int i; | |
1639 | ||
1640 | for (i = 0; i < mpic->num_sources; i++) { | |
1641 | mpic->save_data[i].vecprio = | |
1642 | mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI)); | |
1643 | mpic->save_data[i].dest = | |
1644 | mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)); | |
1645 | } | |
1646 | ||
1647 | return 0; | |
1648 | } | |
1649 | ||
1650 | static int mpic_resume(struct sys_device *dev) | |
1651 | { | |
1652 | struct mpic *mpic = container_of(dev, struct mpic, sysdev); | |
1653 | int i; | |
1654 | ||
1655 | for (i = 0; i < mpic->num_sources; i++) { | |
1656 | mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), | |
1657 | mpic->save_data[i].vecprio); | |
1658 | mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), | |
1659 | mpic->save_data[i].dest); | |
1660 | ||
1661 | #ifdef CONFIG_MPIC_U3_HT_IRQS | |
1662 | { | |
1663 | struct mpic_irq_fixup *fixup = &mpic->fixups[i]; | |
1664 | ||
1665 | if (fixup->base) { | |
1666 | /* we use the lowest bit in an inverted meaning */ | |
1667 | if ((mpic->save_data[i].fixup_data & 1) == 0) | |
1668 | continue; | |
1669 | ||
1670 | /* Enable and configure */ | |
1671 | writeb(0x10 + 2 * fixup->index, fixup->base + 2); | |
1672 | ||
1673 | writel(mpic->save_data[i].fixup_data & ~1, | |
1674 | fixup->base + 4); | |
1675 | } | |
1676 | } | |
1677 | #endif | |
1678 | } /* end for loop */ | |
1679 | ||
1680 | return 0; | |
1681 | } | |
1682 | #endif | |
1683 | ||
1684 | static struct sysdev_class mpic_sysclass = { | |
1685 | #ifdef CONFIG_PM | |
1686 | .resume = mpic_resume, | |
1687 | .suspend = mpic_suspend, | |
1688 | #endif | |
af5ca3f4 | 1689 | .name = "mpic", |
3669e930 JB |
1690 | }; |
1691 | ||
1692 | static int mpic_init_sys(void) | |
1693 | { | |
1694 | struct mpic *mpic = mpics; | |
1695 | int error, id = 0; | |
1696 | ||
1697 | error = sysdev_class_register(&mpic_sysclass); | |
1698 | ||
1699 | while (mpic && !error) { | |
1700 | mpic->sysdev.cls = &mpic_sysclass; | |
1701 | mpic->sysdev.id = id++; | |
1702 | error = sysdev_register(&mpic->sysdev); | |
1703 | mpic = mpic->next; | |
1704 | } | |
1705 | return error; | |
1706 | } | |
1707 | ||
1708 | device_initcall(mpic_init_sys); |