Commit | Line | Data |
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14cf11af PM |
1 | /* |
2 | * arch/powerpc/kernel/mpic.c | |
3 | * | |
4 | * Driver for interrupt controllers following the OpenPIC standard, the | |
5 | * common implementation beeing IBM's MPIC. This driver also can deal | |
6 | * with various broken implementations of this HW. | |
7 | * | |
8 | * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp. | |
22d168ce | 9 | * Copyright 2010-2011 Freescale Semiconductor, Inc. |
14cf11af PM |
10 | * |
11 | * This file is subject to the terms and conditions of the GNU General Public | |
12 | * License. See the file COPYING in the main directory of this archive | |
13 | * for more details. | |
14 | */ | |
15 | ||
16 | #undef DEBUG | |
1beb6a7d BH |
17 | #undef DEBUG_IPI |
18 | #undef DEBUG_IRQ | |
19 | #undef DEBUG_LOW | |
14cf11af | 20 | |
14cf11af PM |
21 | #include <linux/types.h> |
22 | #include <linux/kernel.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/irq.h> | |
25 | #include <linux/smp.h> | |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/bootmem.h> | |
28 | #include <linux/spinlock.h> | |
29 | #include <linux/pci.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
f5a592f7 | 31 | #include <linux/syscore_ops.h> |
76462232 | 32 | #include <linux/ratelimit.h> |
14cf11af PM |
33 | |
34 | #include <asm/ptrace.h> | |
35 | #include <asm/signal.h> | |
36 | #include <asm/io.h> | |
37 | #include <asm/pgtable.h> | |
38 | #include <asm/irq.h> | |
39 | #include <asm/machdep.h> | |
40 | #include <asm/mpic.h> | |
41 | #include <asm/smp.h> | |
42 | ||
a7de7c74 ME |
43 | #include "mpic.h" |
44 | ||
14cf11af PM |
45 | #ifdef DEBUG |
46 | #define DBG(fmt...) printk(fmt) | |
47 | #else | |
48 | #define DBG(fmt...) | |
49 | #endif | |
50 | ||
51 | static struct mpic *mpics; | |
52 | static struct mpic *mpic_primary; | |
203041ad | 53 | static DEFINE_RAW_SPINLOCK(mpic_lock); |
14cf11af | 54 | |
c0c0d996 | 55 | #ifdef CONFIG_PPC32 /* XXX for now */ |
e40c7f02 AW |
56 | #ifdef CONFIG_IRQ_ALL_CPUS |
57 | #define distribute_irqs (1) | |
58 | #else | |
59 | #define distribute_irqs (0) | |
60 | #endif | |
c0c0d996 | 61 | #endif |
14cf11af | 62 | |
7233593b ZR |
63 | #ifdef CONFIG_MPIC_WEIRD |
64 | static u32 mpic_infos[][MPIC_IDX_END] = { | |
65 | [0] = { /* Original OpenPIC compatible MPIC */ | |
66 | MPIC_GREG_BASE, | |
67 | MPIC_GREG_FEATURE_0, | |
68 | MPIC_GREG_GLOBAL_CONF_0, | |
69 | MPIC_GREG_VENDOR_ID, | |
70 | MPIC_GREG_IPI_VECTOR_PRI_0, | |
71 | MPIC_GREG_IPI_STRIDE, | |
72 | MPIC_GREG_SPURIOUS, | |
73 | MPIC_GREG_TIMER_FREQ, | |
74 | ||
75 | MPIC_TIMER_BASE, | |
76 | MPIC_TIMER_STRIDE, | |
77 | MPIC_TIMER_CURRENT_CNT, | |
78 | MPIC_TIMER_BASE_CNT, | |
79 | MPIC_TIMER_VECTOR_PRI, | |
80 | MPIC_TIMER_DESTINATION, | |
81 | ||
82 | MPIC_CPU_BASE, | |
83 | MPIC_CPU_STRIDE, | |
84 | MPIC_CPU_IPI_DISPATCH_0, | |
85 | MPIC_CPU_IPI_DISPATCH_STRIDE, | |
86 | MPIC_CPU_CURRENT_TASK_PRI, | |
87 | MPIC_CPU_WHOAMI, | |
88 | MPIC_CPU_INTACK, | |
89 | MPIC_CPU_EOI, | |
f365355e | 90 | MPIC_CPU_MCACK, |
7233593b ZR |
91 | |
92 | MPIC_IRQ_BASE, | |
93 | MPIC_IRQ_STRIDE, | |
94 | MPIC_IRQ_VECTOR_PRI, | |
95 | MPIC_VECPRI_VECTOR_MASK, | |
96 | MPIC_VECPRI_POLARITY_POSITIVE, | |
97 | MPIC_VECPRI_POLARITY_NEGATIVE, | |
98 | MPIC_VECPRI_SENSE_LEVEL, | |
99 | MPIC_VECPRI_SENSE_EDGE, | |
100 | MPIC_VECPRI_POLARITY_MASK, | |
101 | MPIC_VECPRI_SENSE_MASK, | |
102 | MPIC_IRQ_DESTINATION | |
103 | }, | |
104 | [1] = { /* Tsi108/109 PIC */ | |
105 | TSI108_GREG_BASE, | |
106 | TSI108_GREG_FEATURE_0, | |
107 | TSI108_GREG_GLOBAL_CONF_0, | |
108 | TSI108_GREG_VENDOR_ID, | |
109 | TSI108_GREG_IPI_VECTOR_PRI_0, | |
110 | TSI108_GREG_IPI_STRIDE, | |
111 | TSI108_GREG_SPURIOUS, | |
112 | TSI108_GREG_TIMER_FREQ, | |
113 | ||
114 | TSI108_TIMER_BASE, | |
115 | TSI108_TIMER_STRIDE, | |
116 | TSI108_TIMER_CURRENT_CNT, | |
117 | TSI108_TIMER_BASE_CNT, | |
118 | TSI108_TIMER_VECTOR_PRI, | |
119 | TSI108_TIMER_DESTINATION, | |
120 | ||
121 | TSI108_CPU_BASE, | |
122 | TSI108_CPU_STRIDE, | |
123 | TSI108_CPU_IPI_DISPATCH_0, | |
124 | TSI108_CPU_IPI_DISPATCH_STRIDE, | |
125 | TSI108_CPU_CURRENT_TASK_PRI, | |
126 | TSI108_CPU_WHOAMI, | |
127 | TSI108_CPU_INTACK, | |
128 | TSI108_CPU_EOI, | |
f365355e | 129 | TSI108_CPU_MCACK, |
7233593b ZR |
130 | |
131 | TSI108_IRQ_BASE, | |
132 | TSI108_IRQ_STRIDE, | |
133 | TSI108_IRQ_VECTOR_PRI, | |
134 | TSI108_VECPRI_VECTOR_MASK, | |
135 | TSI108_VECPRI_POLARITY_POSITIVE, | |
136 | TSI108_VECPRI_POLARITY_NEGATIVE, | |
137 | TSI108_VECPRI_SENSE_LEVEL, | |
138 | TSI108_VECPRI_SENSE_EDGE, | |
139 | TSI108_VECPRI_POLARITY_MASK, | |
140 | TSI108_VECPRI_SENSE_MASK, | |
141 | TSI108_IRQ_DESTINATION | |
142 | }, | |
143 | }; | |
144 | ||
145 | #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name] | |
146 | ||
147 | #else /* CONFIG_MPIC_WEIRD */ | |
148 | ||
149 | #define MPIC_INFO(name) MPIC_##name | |
150 | ||
151 | #endif /* CONFIG_MPIC_WEIRD */ | |
152 | ||
d6a2639b MI |
153 | static inline unsigned int mpic_processor_id(struct mpic *mpic) |
154 | { | |
155 | unsigned int cpu = 0; | |
156 | ||
be8bec56 | 157 | if (!(mpic->flags & MPIC_SECONDARY)) |
d6a2639b MI |
158 | cpu = hard_smp_processor_id(); |
159 | ||
160 | return cpu; | |
161 | } | |
162 | ||
14cf11af PM |
163 | /* |
164 | * Register accessor functions | |
165 | */ | |
166 | ||
167 | ||
fbf0274e BH |
168 | static inline u32 _mpic_read(enum mpic_reg_type type, |
169 | struct mpic_reg_bank *rb, | |
170 | unsigned int reg) | |
14cf11af | 171 | { |
fbf0274e BH |
172 | switch(type) { |
173 | #ifdef CONFIG_PPC_DCR | |
174 | case mpic_access_dcr: | |
83f34df4 | 175 | return dcr_read(rb->dhost, reg); |
fbf0274e BH |
176 | #endif |
177 | case mpic_access_mmio_be: | |
178 | return in_be32(rb->base + (reg >> 2)); | |
179 | case mpic_access_mmio_le: | |
180 | default: | |
181 | return in_le32(rb->base + (reg >> 2)); | |
182 | } | |
14cf11af PM |
183 | } |
184 | ||
fbf0274e BH |
185 | static inline void _mpic_write(enum mpic_reg_type type, |
186 | struct mpic_reg_bank *rb, | |
187 | unsigned int reg, u32 value) | |
14cf11af | 188 | { |
fbf0274e BH |
189 | switch(type) { |
190 | #ifdef CONFIG_PPC_DCR | |
191 | case mpic_access_dcr: | |
d9d1063d JB |
192 | dcr_write(rb->dhost, reg, value); |
193 | break; | |
fbf0274e BH |
194 | #endif |
195 | case mpic_access_mmio_be: | |
d9d1063d JB |
196 | out_be32(rb->base + (reg >> 2), value); |
197 | break; | |
fbf0274e BH |
198 | case mpic_access_mmio_le: |
199 | default: | |
d9d1063d JB |
200 | out_le32(rb->base + (reg >> 2), value); |
201 | break; | |
fbf0274e | 202 | } |
14cf11af PM |
203 | } |
204 | ||
205 | static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi) | |
206 | { | |
fbf0274e | 207 | enum mpic_reg_type type = mpic->reg_type; |
7233593b ZR |
208 | unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) + |
209 | (ipi * MPIC_INFO(GREG_IPI_STRIDE)); | |
14cf11af | 210 | |
fbf0274e BH |
211 | if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le) |
212 | type = mpic_access_mmio_be; | |
213 | return _mpic_read(type, &mpic->gregs, offset); | |
14cf11af PM |
214 | } |
215 | ||
216 | static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value) | |
217 | { | |
7233593b ZR |
218 | unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) + |
219 | (ipi * MPIC_INFO(GREG_IPI_STRIDE)); | |
14cf11af | 220 | |
fbf0274e | 221 | _mpic_write(mpic->reg_type, &mpic->gregs, offset, value); |
14cf11af PM |
222 | } |
223 | ||
ea94187f SW |
224 | static inline u32 _mpic_tm_read(struct mpic *mpic, unsigned int tm) |
225 | { | |
226 | unsigned int offset = MPIC_INFO(TIMER_VECTOR_PRI) + | |
227 | ((tm & 3) * MPIC_INFO(TIMER_STRIDE)); | |
228 | ||
229 | if (tm >= 4) | |
230 | offset += 0x1000 / 4; | |
231 | ||
232 | return _mpic_read(mpic->reg_type, &mpic->tmregs, offset); | |
233 | } | |
234 | ||
235 | static inline void _mpic_tm_write(struct mpic *mpic, unsigned int tm, u32 value) | |
236 | { | |
237 | unsigned int offset = MPIC_INFO(TIMER_VECTOR_PRI) + | |
238 | ((tm & 3) * MPIC_INFO(TIMER_STRIDE)); | |
239 | ||
240 | if (tm >= 4) | |
241 | offset += 0x1000 / 4; | |
242 | ||
243 | _mpic_write(mpic->reg_type, &mpic->tmregs, offset, value); | |
244 | } | |
245 | ||
14cf11af PM |
246 | static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg) |
247 | { | |
d6a2639b | 248 | unsigned int cpu = mpic_processor_id(mpic); |
14cf11af | 249 | |
fbf0274e | 250 | return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg); |
14cf11af PM |
251 | } |
252 | ||
253 | static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value) | |
254 | { | |
d6a2639b | 255 | unsigned int cpu = mpic_processor_id(mpic); |
14cf11af | 256 | |
fbf0274e | 257 | _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value); |
14cf11af PM |
258 | } |
259 | ||
260 | static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg) | |
261 | { | |
262 | unsigned int isu = src_no >> mpic->isu_shift; | |
263 | unsigned int idx = src_no & mpic->isu_mask; | |
11a6b292 | 264 | unsigned int val; |
14cf11af | 265 | |
11a6b292 ME |
266 | val = _mpic_read(mpic->reg_type, &mpic->isus[isu], |
267 | reg + (idx * MPIC_INFO(IRQ_STRIDE))); | |
0d72ba93 OJ |
268 | #ifdef CONFIG_MPIC_BROKEN_REGREAD |
269 | if (reg == 0) | |
11a6b292 ME |
270 | val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) | |
271 | mpic->isu_reg0_shadow[src_no]; | |
0d72ba93 | 272 | #endif |
11a6b292 | 273 | return val; |
14cf11af PM |
274 | } |
275 | ||
276 | static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no, | |
277 | unsigned int reg, u32 value) | |
278 | { | |
279 | unsigned int isu = src_no >> mpic->isu_shift; | |
280 | unsigned int idx = src_no & mpic->isu_mask; | |
281 | ||
fbf0274e | 282 | _mpic_write(mpic->reg_type, &mpic->isus[isu], |
7233593b | 283 | reg + (idx * MPIC_INFO(IRQ_STRIDE)), value); |
0d72ba93 OJ |
284 | |
285 | #ifdef CONFIG_MPIC_BROKEN_REGREAD | |
286 | if (reg == 0) | |
11a6b292 ME |
287 | mpic->isu_reg0_shadow[src_no] = |
288 | value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY); | |
0d72ba93 | 289 | #endif |
14cf11af PM |
290 | } |
291 | ||
fbf0274e BH |
292 | #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r)) |
293 | #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v)) | |
14cf11af PM |
294 | #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i)) |
295 | #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v)) | |
ea94187f SW |
296 | #define mpic_tm_read(i) _mpic_tm_read(mpic,(i)) |
297 | #define mpic_tm_write(i,v) _mpic_tm_write(mpic,(i),(v)) | |
14cf11af PM |
298 | #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i)) |
299 | #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v)) | |
300 | #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r)) | |
301 | #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v)) | |
302 | ||
303 | ||
304 | /* | |
305 | * Low level utility functions | |
306 | */ | |
307 | ||
308 | ||
c51a3fdc | 309 | static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr, |
fbf0274e BH |
310 | struct mpic_reg_bank *rb, unsigned int offset, |
311 | unsigned int size) | |
312 | { | |
313 | rb->base = ioremap(phys_addr + offset, size); | |
314 | BUG_ON(rb->base == NULL); | |
315 | } | |
316 | ||
317 | #ifdef CONFIG_PPC_DCR | |
c51242e7 | 318 | static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb, |
fbf0274e BH |
319 | unsigned int offset, unsigned int size) |
320 | { | |
c51242e7 | 321 | phys_addr_t phys_addr = dcr_resource_start(mpic->node, 0); |
e62b7601 | 322 | rb->dhost = dcr_map(mpic->node, phys_addr + offset, size); |
fbf0274e BH |
323 | BUG_ON(!DCR_MAP_OK(rb->dhost)); |
324 | } | |
325 | ||
c51242e7 | 326 | static inline void mpic_map(struct mpic *mpic, |
5a2642f6 BH |
327 | phys_addr_t phys_addr, struct mpic_reg_bank *rb, |
328 | unsigned int offset, unsigned int size) | |
fbf0274e BH |
329 | { |
330 | if (mpic->flags & MPIC_USES_DCR) | |
c51242e7 | 331 | _mpic_map_dcr(mpic, rb, offset, size); |
fbf0274e BH |
332 | else |
333 | _mpic_map_mmio(mpic, phys_addr, rb, offset, size); | |
334 | } | |
335 | #else /* CONFIG_PPC_DCR */ | |
c51242e7 | 336 | #define mpic_map(m,p,b,o,s) _mpic_map_mmio(m,p,b,o,s) |
fbf0274e BH |
337 | #endif /* !CONFIG_PPC_DCR */ |
338 | ||
339 | ||
14cf11af PM |
340 | |
341 | /* Check if we have one of those nice broken MPICs with a flipped endian on | |
342 | * reads from IPI registers | |
343 | */ | |
344 | static void __init mpic_test_broken_ipi(struct mpic *mpic) | |
345 | { | |
346 | u32 r; | |
347 | ||
7233593b ZR |
348 | mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK); |
349 | r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0)); | |
14cf11af PM |
350 | |
351 | if (r == le32_to_cpu(MPIC_VECPRI_MASK)) { | |
352 | printk(KERN_INFO "mpic: Detected reversed IPI registers\n"); | |
353 | mpic->flags |= MPIC_BROKEN_IPI; | |
354 | } | |
355 | } | |
356 | ||
6cfef5b2 | 357 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
14cf11af PM |
358 | |
359 | /* Test if an interrupt is sourced from HyperTransport (used on broken U3s) | |
360 | * to force the edge setting on the MPIC and do the ack workaround. | |
361 | */ | |
1beb6a7d | 362 | static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) |
14cf11af | 363 | { |
1beb6a7d | 364 | if (source >= 128 || !mpic->fixups) |
14cf11af | 365 | return 0; |
1beb6a7d | 366 | return mpic->fixups[source].base != NULL; |
14cf11af PM |
367 | } |
368 | ||
c4b22f26 | 369 | |
1beb6a7d | 370 | static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source) |
14cf11af | 371 | { |
1beb6a7d | 372 | struct mpic_irq_fixup *fixup = &mpic->fixups[source]; |
14cf11af | 373 | |
1beb6a7d BH |
374 | if (fixup->applebase) { |
375 | unsigned int soff = (fixup->index >> 3) & ~3; | |
376 | unsigned int mask = 1U << (fixup->index & 0x1f); | |
377 | writel(mask, fixup->applebase + soff); | |
378 | } else { | |
203041ad | 379 | raw_spin_lock(&mpic->fixup_lock); |
1beb6a7d BH |
380 | writeb(0x11 + 2 * fixup->index, fixup->base + 2); |
381 | writel(fixup->data, fixup->base + 4); | |
203041ad | 382 | raw_spin_unlock(&mpic->fixup_lock); |
1beb6a7d | 383 | } |
14cf11af PM |
384 | } |
385 | ||
1beb6a7d | 386 | static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source, |
24a3f2e8 | 387 | bool level) |
1beb6a7d BH |
388 | { |
389 | struct mpic_irq_fixup *fixup = &mpic->fixups[source]; | |
390 | unsigned long flags; | |
391 | u32 tmp; | |
392 | ||
393 | if (fixup->base == NULL) | |
394 | return; | |
395 | ||
24a3f2e8 TG |
396 | DBG("startup_ht_interrupt(0x%x) index: %d\n", |
397 | source, fixup->index); | |
203041ad | 398 | raw_spin_lock_irqsave(&mpic->fixup_lock, flags); |
1beb6a7d BH |
399 | /* Enable and configure */ |
400 | writeb(0x10 + 2 * fixup->index, fixup->base + 2); | |
401 | tmp = readl(fixup->base + 4); | |
402 | tmp &= ~(0x23U); | |
24a3f2e8 | 403 | if (level) |
1beb6a7d BH |
404 | tmp |= 0x22; |
405 | writel(tmp, fixup->base + 4); | |
203041ad | 406 | raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags); |
3669e930 JB |
407 | |
408 | #ifdef CONFIG_PM | |
409 | /* use the lowest bit inverted to the actual HW, | |
410 | * set if this fixup was enabled, clear otherwise */ | |
411 | mpic->save_data[source].fixup_data = tmp | 1; | |
412 | #endif | |
1beb6a7d BH |
413 | } |
414 | ||
24a3f2e8 | 415 | static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source) |
1beb6a7d BH |
416 | { |
417 | struct mpic_irq_fixup *fixup = &mpic->fixups[source]; | |
418 | unsigned long flags; | |
419 | u32 tmp; | |
420 | ||
421 | if (fixup->base == NULL) | |
422 | return; | |
423 | ||
24a3f2e8 | 424 | DBG("shutdown_ht_interrupt(0x%x)\n", source); |
1beb6a7d BH |
425 | |
426 | /* Disable */ | |
203041ad | 427 | raw_spin_lock_irqsave(&mpic->fixup_lock, flags); |
1beb6a7d BH |
428 | writeb(0x10 + 2 * fixup->index, fixup->base + 2); |
429 | tmp = readl(fixup->base + 4); | |
72b13819 | 430 | tmp |= 1; |
1beb6a7d | 431 | writel(tmp, fixup->base + 4); |
203041ad | 432 | raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags); |
3669e930 JB |
433 | |
434 | #ifdef CONFIG_PM | |
435 | /* use the lowest bit inverted to the actual HW, | |
436 | * set if this fixup was enabled, clear otherwise */ | |
437 | mpic->save_data[source].fixup_data = tmp & ~1; | |
438 | #endif | |
1beb6a7d | 439 | } |
14cf11af | 440 | |
812fd1fd ME |
441 | #ifdef CONFIG_PCI_MSI |
442 | static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase, | |
443 | unsigned int devfn) | |
444 | { | |
445 | u8 __iomem *base; | |
446 | u8 pos, flags; | |
447 | u64 addr = 0; | |
448 | ||
449 | for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0; | |
450 | pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) { | |
451 | u8 id = readb(devbase + pos + PCI_CAP_LIST_ID); | |
452 | if (id == PCI_CAP_ID_HT) { | |
453 | id = readb(devbase + pos + 3); | |
454 | if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING) | |
455 | break; | |
456 | } | |
457 | } | |
458 | ||
459 | if (pos == 0) | |
460 | return; | |
461 | ||
462 | base = devbase + pos; | |
463 | ||
464 | flags = readb(base + HT_MSI_FLAGS); | |
465 | if (!(flags & HT_MSI_FLAGS_FIXED)) { | |
466 | addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK; | |
467 | addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32); | |
468 | } | |
469 | ||
fe333321 | 470 | printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%llx\n", |
812fd1fd ME |
471 | PCI_SLOT(devfn), PCI_FUNC(devfn), |
472 | flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr); | |
473 | ||
474 | if (!(flags & HT_MSI_FLAGS_ENABLE)) | |
475 | writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS); | |
476 | } | |
477 | #else | |
478 | static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase, | |
479 | unsigned int devfn) | |
480 | { | |
481 | return; | |
482 | } | |
483 | #endif | |
484 | ||
1beb6a7d BH |
485 | static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase, |
486 | unsigned int devfn, u32 vdid) | |
14cf11af | 487 | { |
c4b22f26 | 488 | int i, irq, n; |
1beb6a7d | 489 | u8 __iomem *base; |
14cf11af | 490 | u32 tmp; |
c4b22f26 | 491 | u8 pos; |
14cf11af | 492 | |
1beb6a7d BH |
493 | for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0; |
494 | pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) { | |
495 | u8 id = readb(devbase + pos + PCI_CAP_LIST_ID); | |
46ff3463 | 496 | if (id == PCI_CAP_ID_HT) { |
c4b22f26 | 497 | id = readb(devbase + pos + 3); |
beb7cc82 | 498 | if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ) |
c4b22f26 SB |
499 | break; |
500 | } | |
14cf11af | 501 | } |
c4b22f26 SB |
502 | if (pos == 0) |
503 | return; | |
504 | ||
1beb6a7d BH |
505 | base = devbase + pos; |
506 | writeb(0x01, base + 2); | |
507 | n = (readl(base + 4) >> 16) & 0xff; | |
14cf11af | 508 | |
1beb6a7d BH |
509 | printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x" |
510 | " has %d irqs\n", | |
511 | devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1); | |
c4b22f26 SB |
512 | |
513 | for (i = 0; i <= n; i++) { | |
1beb6a7d BH |
514 | writeb(0x10 + 2 * i, base + 2); |
515 | tmp = readl(base + 4); | |
14cf11af | 516 | irq = (tmp >> 16) & 0xff; |
1beb6a7d BH |
517 | DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp); |
518 | /* mask it , will be unmasked later */ | |
519 | tmp |= 0x1; | |
520 | writel(tmp, base + 4); | |
521 | mpic->fixups[irq].index = i; | |
522 | mpic->fixups[irq].base = base; | |
523 | /* Apple HT PIC has a non-standard way of doing EOIs */ | |
524 | if ((vdid & 0xffff) == 0x106b) | |
525 | mpic->fixups[irq].applebase = devbase + 0x60; | |
526 | else | |
527 | mpic->fixups[irq].applebase = NULL; | |
528 | writeb(0x11 + 2 * i, base + 2); | |
529 | mpic->fixups[irq].data = readl(base + 4) | 0x80000000; | |
14cf11af PM |
530 | } |
531 | } | |
532 | ||
c4b22f26 | 533 | |
1beb6a7d | 534 | static void __init mpic_scan_ht_pics(struct mpic *mpic) |
14cf11af PM |
535 | { |
536 | unsigned int devfn; | |
537 | u8 __iomem *cfgspace; | |
538 | ||
1beb6a7d | 539 | printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n"); |
14cf11af PM |
540 | |
541 | /* Allocate fixups array */ | |
ea96025a | 542 | mpic->fixups = kzalloc(128 * sizeof(*mpic->fixups), GFP_KERNEL); |
14cf11af | 543 | BUG_ON(mpic->fixups == NULL); |
14cf11af PM |
544 | |
545 | /* Init spinlock */ | |
203041ad | 546 | raw_spin_lock_init(&mpic->fixup_lock); |
14cf11af | 547 | |
c4b22f26 SB |
548 | /* Map U3 config space. We assume all IO-APICs are on the primary bus |
549 | * so we only need to map 64kB. | |
14cf11af | 550 | */ |
c4b22f26 | 551 | cfgspace = ioremap(0xf2000000, 0x10000); |
14cf11af PM |
552 | BUG_ON(cfgspace == NULL); |
553 | ||
1beb6a7d BH |
554 | /* Now we scan all slots. We do a very quick scan, we read the header |
555 | * type, vendor ID and device ID only, that's plenty enough | |
14cf11af | 556 | */ |
c4b22f26 | 557 | for (devfn = 0; devfn < 0x100; devfn++) { |
14cf11af PM |
558 | u8 __iomem *devbase = cfgspace + (devfn << 8); |
559 | u8 hdr_type = readb(devbase + PCI_HEADER_TYPE); | |
560 | u32 l = readl(devbase + PCI_VENDOR_ID); | |
1beb6a7d | 561 | u16 s; |
14cf11af PM |
562 | |
563 | DBG("devfn %x, l: %x\n", devfn, l); | |
564 | ||
565 | /* If no device, skip */ | |
566 | if (l == 0xffffffff || l == 0x00000000 || | |
567 | l == 0x0000ffff || l == 0xffff0000) | |
568 | goto next; | |
1beb6a7d BH |
569 | /* Check if is supports capability lists */ |
570 | s = readw(devbase + PCI_STATUS); | |
571 | if (!(s & PCI_STATUS_CAP_LIST)) | |
572 | goto next; | |
14cf11af | 573 | |
1beb6a7d | 574 | mpic_scan_ht_pic(mpic, devbase, devfn, l); |
812fd1fd | 575 | mpic_scan_ht_msi(mpic, devbase, devfn); |
c4b22f26 | 576 | |
14cf11af PM |
577 | next: |
578 | /* next device, if function 0 */ | |
c4b22f26 | 579 | if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0) |
14cf11af PM |
580 | devfn += 7; |
581 | } | |
582 | } | |
583 | ||
6cfef5b2 | 584 | #else /* CONFIG_MPIC_U3_HT_IRQS */ |
6e99e458 BH |
585 | |
586 | static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) | |
587 | { | |
588 | return 0; | |
589 | } | |
590 | ||
591 | static void __init mpic_scan_ht_pics(struct mpic *mpic) | |
592 | { | |
593 | } | |
594 | ||
6cfef5b2 | 595 | #endif /* CONFIG_MPIC_U3_HT_IRQS */ |
14cf11af | 596 | |
14cf11af | 597 | /* Find an mpic associated with a given linux interrupt */ |
d69a78d7 | 598 | static struct mpic *mpic_find(unsigned int irq) |
14cf11af | 599 | { |
0ebfff14 BH |
600 | if (irq < NUM_ISA_INTERRUPTS) |
601 | return NULL; | |
7df2457d | 602 | |
ec775d0e | 603 | return irq_get_chip_data(irq); |
d69a78d7 | 604 | } |
7df2457d | 605 | |
d69a78d7 TB |
606 | /* Determine if the linux irq is an IPI */ |
607 | static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq) | |
608 | { | |
476eb491 | 609 | unsigned int src = virq_to_hw(irq); |
0ebfff14 | 610 | |
d69a78d7 | 611 | return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]); |
14cf11af PM |
612 | } |
613 | ||
ea94187f SW |
614 | /* Determine if the linux irq is a timer */ |
615 | static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int irq) | |
616 | { | |
617 | unsigned int src = virq_to_hw(irq); | |
618 | ||
619 | return (src >= mpic->timer_vecs[0] && src <= mpic->timer_vecs[7]); | |
620 | } | |
d69a78d7 | 621 | |
14cf11af PM |
622 | /* Convert a cpu mask from logical to physical cpu numbers. */ |
623 | static inline u32 mpic_physmask(u32 cpumask) | |
624 | { | |
625 | int i; | |
626 | u32 mask = 0; | |
627 | ||
ebc04215 | 628 | for (i = 0; i < min(32, NR_CPUS); ++i, cpumask >>= 1) |
14cf11af PM |
629 | mask |= (cpumask & 1) << get_hard_smp_processor_id(i); |
630 | return mask; | |
631 | } | |
632 | ||
633 | #ifdef CONFIG_SMP | |
634 | /* Get the mpic structure from the IPI number */ | |
835c0553 | 635 | static inline struct mpic * mpic_from_ipi(struct irq_data *d) |
14cf11af | 636 | { |
835c0553 | 637 | return irq_data_get_irq_chip_data(d); |
14cf11af PM |
638 | } |
639 | #endif | |
640 | ||
641 | /* Get the mpic structure from the irq number */ | |
642 | static inline struct mpic * mpic_from_irq(unsigned int irq) | |
643 | { | |
ec775d0e | 644 | return irq_get_chip_data(irq); |
835c0553 LB |
645 | } |
646 | ||
647 | /* Get the mpic structure from the irq data */ | |
648 | static inline struct mpic * mpic_from_irq_data(struct irq_data *d) | |
649 | { | |
650 | return irq_data_get_irq_chip_data(d); | |
14cf11af PM |
651 | } |
652 | ||
653 | /* Send an EOI */ | |
654 | static inline void mpic_eoi(struct mpic *mpic) | |
655 | { | |
7233593b ZR |
656 | mpic_cpu_write(MPIC_INFO(CPU_EOI), 0); |
657 | (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI)); | |
14cf11af PM |
658 | } |
659 | ||
14cf11af PM |
660 | /* |
661 | * Linux descriptor level callbacks | |
662 | */ | |
663 | ||
664 | ||
835c0553 | 665 | void mpic_unmask_irq(struct irq_data *d) |
14cf11af PM |
666 | { |
667 | unsigned int loops = 100000; | |
835c0553 | 668 | struct mpic *mpic = mpic_from_irq_data(d); |
476eb491 | 669 | unsigned int src = irqd_to_hwirq(d); |
14cf11af | 670 | |
835c0553 | 671 | DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src); |
14cf11af | 672 | |
7233593b ZR |
673 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), |
674 | mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & | |
e5356640 | 675 | ~MPIC_VECPRI_MASK); |
14cf11af PM |
676 | /* make sure mask gets to controller before we return to user */ |
677 | do { | |
678 | if (!loops--) { | |
8bfc5e36 SW |
679 | printk(KERN_ERR "%s: timeout on hwirq %u\n", |
680 | __func__, src); | |
14cf11af PM |
681 | break; |
682 | } | |
7233593b | 683 | } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK); |
14cf11af PM |
684 | } |
685 | ||
835c0553 | 686 | void mpic_mask_irq(struct irq_data *d) |
14cf11af PM |
687 | { |
688 | unsigned int loops = 100000; | |
835c0553 | 689 | struct mpic *mpic = mpic_from_irq_data(d); |
476eb491 | 690 | unsigned int src = irqd_to_hwirq(d); |
14cf11af | 691 | |
835c0553 | 692 | DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src); |
14cf11af | 693 | |
7233593b ZR |
694 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), |
695 | mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) | | |
e5356640 | 696 | MPIC_VECPRI_MASK); |
14cf11af PM |
697 | |
698 | /* make sure mask gets to controller before we return to user */ | |
699 | do { | |
700 | if (!loops--) { | |
8bfc5e36 SW |
701 | printk(KERN_ERR "%s: timeout on hwirq %u\n", |
702 | __func__, src); | |
14cf11af PM |
703 | break; |
704 | } | |
7233593b | 705 | } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK)); |
14cf11af PM |
706 | } |
707 | ||
835c0553 | 708 | void mpic_end_irq(struct irq_data *d) |
1beb6a7d | 709 | { |
835c0553 | 710 | struct mpic *mpic = mpic_from_irq_data(d); |
b9e5b4e6 BH |
711 | |
712 | #ifdef DEBUG_IRQ | |
835c0553 | 713 | DBG("%s: end_irq: %d\n", mpic->name, d->irq); |
b9e5b4e6 BH |
714 | #endif |
715 | /* We always EOI on end_irq() even for edge interrupts since that | |
716 | * should only lower the priority, the MPIC should have properly | |
717 | * latched another edge interrupt coming in anyway | |
718 | */ | |
719 | ||
720 | mpic_eoi(mpic); | |
721 | } | |
722 | ||
6cfef5b2 | 723 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
b9e5b4e6 | 724 | |
835c0553 | 725 | static void mpic_unmask_ht_irq(struct irq_data *d) |
b9e5b4e6 | 726 | { |
835c0553 | 727 | struct mpic *mpic = mpic_from_irq_data(d); |
476eb491 | 728 | unsigned int src = irqd_to_hwirq(d); |
1beb6a7d | 729 | |
835c0553 | 730 | mpic_unmask_irq(d); |
1beb6a7d | 731 | |
24a3f2e8 | 732 | if (irqd_is_level_type(d)) |
b9e5b4e6 BH |
733 | mpic_ht_end_irq(mpic, src); |
734 | } | |
735 | ||
835c0553 | 736 | static unsigned int mpic_startup_ht_irq(struct irq_data *d) |
b9e5b4e6 | 737 | { |
835c0553 | 738 | struct mpic *mpic = mpic_from_irq_data(d); |
476eb491 | 739 | unsigned int src = irqd_to_hwirq(d); |
1beb6a7d | 740 | |
835c0553 | 741 | mpic_unmask_irq(d); |
24a3f2e8 | 742 | mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d)); |
b9e5b4e6 BH |
743 | |
744 | return 0; | |
1beb6a7d BH |
745 | } |
746 | ||
835c0553 | 747 | static void mpic_shutdown_ht_irq(struct irq_data *d) |
b9e5b4e6 | 748 | { |
835c0553 | 749 | struct mpic *mpic = mpic_from_irq_data(d); |
476eb491 | 750 | unsigned int src = irqd_to_hwirq(d); |
b9e5b4e6 | 751 | |
24a3f2e8 | 752 | mpic_shutdown_ht_interrupt(mpic, src); |
835c0553 | 753 | mpic_mask_irq(d); |
b9e5b4e6 BH |
754 | } |
755 | ||
835c0553 | 756 | static void mpic_end_ht_irq(struct irq_data *d) |
14cf11af | 757 | { |
835c0553 | 758 | struct mpic *mpic = mpic_from_irq_data(d); |
476eb491 | 759 | unsigned int src = irqd_to_hwirq(d); |
14cf11af | 760 | |
1beb6a7d | 761 | #ifdef DEBUG_IRQ |
835c0553 | 762 | DBG("%s: end_irq: %d\n", mpic->name, d->irq); |
1beb6a7d | 763 | #endif |
14cf11af PM |
764 | /* We always EOI on end_irq() even for edge interrupts since that |
765 | * should only lower the priority, the MPIC should have properly | |
766 | * latched another edge interrupt coming in anyway | |
767 | */ | |
768 | ||
24a3f2e8 | 769 | if (irqd_is_level_type(d)) |
b9e5b4e6 | 770 | mpic_ht_end_irq(mpic, src); |
14cf11af PM |
771 | mpic_eoi(mpic); |
772 | } | |
6cfef5b2 | 773 | #endif /* !CONFIG_MPIC_U3_HT_IRQS */ |
b9e5b4e6 | 774 | |
14cf11af PM |
775 | #ifdef CONFIG_SMP |
776 | ||
835c0553 | 777 | static void mpic_unmask_ipi(struct irq_data *d) |
14cf11af | 778 | { |
835c0553 | 779 | struct mpic *mpic = mpic_from_ipi(d); |
476eb491 | 780 | unsigned int src = virq_to_hw(d->irq) - mpic->ipi_vecs[0]; |
14cf11af | 781 | |
835c0553 | 782 | DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src); |
14cf11af PM |
783 | mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK); |
784 | } | |
785 | ||
835c0553 | 786 | static void mpic_mask_ipi(struct irq_data *d) |
14cf11af PM |
787 | { |
788 | /* NEVER disable an IPI... that's just plain wrong! */ | |
789 | } | |
790 | ||
835c0553 | 791 | static void mpic_end_ipi(struct irq_data *d) |
14cf11af | 792 | { |
835c0553 | 793 | struct mpic *mpic = mpic_from_ipi(d); |
14cf11af PM |
794 | |
795 | /* | |
796 | * IPIs are marked IRQ_PER_CPU. This has the side effect of | |
797 | * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from | |
798 | * applying to them. We EOI them late to avoid re-entering. | |
14cf11af PM |
799 | */ |
800 | mpic_eoi(mpic); | |
801 | } | |
802 | ||
803 | #endif /* CONFIG_SMP */ | |
804 | ||
ea94187f SW |
805 | static void mpic_unmask_tm(struct irq_data *d) |
806 | { | |
807 | struct mpic *mpic = mpic_from_irq_data(d); | |
808 | unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0]; | |
809 | ||
77ef4899 | 810 | DBG("%s: enable_tm: %d (tm %d)\n", mpic->name, d->irq, src); |
ea94187f SW |
811 | mpic_tm_write(src, mpic_tm_read(src) & ~MPIC_VECPRI_MASK); |
812 | mpic_tm_read(src); | |
813 | } | |
814 | ||
815 | static void mpic_mask_tm(struct irq_data *d) | |
816 | { | |
817 | struct mpic *mpic = mpic_from_irq_data(d); | |
818 | unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0]; | |
819 | ||
820 | mpic_tm_write(src, mpic_tm_read(src) | MPIC_VECPRI_MASK); | |
821 | mpic_tm_read(src); | |
822 | } | |
823 | ||
835c0553 LB |
824 | int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask, |
825 | bool force) | |
14cf11af | 826 | { |
835c0553 | 827 | struct mpic *mpic = mpic_from_irq_data(d); |
476eb491 | 828 | unsigned int src = irqd_to_hwirq(d); |
14cf11af | 829 | |
3c10c9c4 | 830 | if (mpic->flags & MPIC_SINGLE_DEST_CPU) { |
38e1313f | 831 | int cpuid = irq_choose_cpu(cpumask); |
14cf11af | 832 | |
3c10c9c4 KG |
833 | mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid); |
834 | } else { | |
2a116f3d | 835 | u32 mask = cpumask_bits(cpumask)[0]; |
14cf11af | 836 | |
2a116f3d | 837 | mask &= cpumask_bits(cpu_online_mask)[0]; |
3c10c9c4 KG |
838 | |
839 | mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), | |
2a116f3d | 840 | mpic_physmask(mask)); |
3c10c9c4 | 841 | } |
d5dedd45 YL |
842 | |
843 | return 0; | |
14cf11af PM |
844 | } |
845 | ||
7233593b | 846 | static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type) |
0ebfff14 | 847 | { |
0ebfff14 | 848 | /* Now convert sense value */ |
6e99e458 | 849 | switch(type & IRQ_TYPE_SENSE_MASK) { |
0ebfff14 | 850 | case IRQ_TYPE_EDGE_RISING: |
7233593b ZR |
851 | return MPIC_INFO(VECPRI_SENSE_EDGE) | |
852 | MPIC_INFO(VECPRI_POLARITY_POSITIVE); | |
0ebfff14 | 853 | case IRQ_TYPE_EDGE_FALLING: |
6e99e458 | 854 | case IRQ_TYPE_EDGE_BOTH: |
7233593b ZR |
855 | return MPIC_INFO(VECPRI_SENSE_EDGE) | |
856 | MPIC_INFO(VECPRI_POLARITY_NEGATIVE); | |
0ebfff14 | 857 | case IRQ_TYPE_LEVEL_HIGH: |
7233593b ZR |
858 | return MPIC_INFO(VECPRI_SENSE_LEVEL) | |
859 | MPIC_INFO(VECPRI_POLARITY_POSITIVE); | |
0ebfff14 BH |
860 | case IRQ_TYPE_LEVEL_LOW: |
861 | default: | |
7233593b ZR |
862 | return MPIC_INFO(VECPRI_SENSE_LEVEL) | |
863 | MPIC_INFO(VECPRI_POLARITY_NEGATIVE); | |
0ebfff14 | 864 | } |
6e99e458 BH |
865 | } |
866 | ||
835c0553 | 867 | int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type) |
6e99e458 | 868 | { |
835c0553 | 869 | struct mpic *mpic = mpic_from_irq_data(d); |
476eb491 | 870 | unsigned int src = irqd_to_hwirq(d); |
6e99e458 BH |
871 | unsigned int vecpri, vold, vnew; |
872 | ||
06fe98e6 | 873 | DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n", |
835c0553 | 874 | mpic, d->irq, src, flow_type); |
6e99e458 BH |
875 | |
876 | if (src >= mpic->irq_count) | |
877 | return -EINVAL; | |
878 | ||
879 | if (flow_type == IRQ_TYPE_NONE) | |
880 | if (mpic->senses && src < mpic->senses_count) | |
881 | flow_type = mpic->senses[src]; | |
882 | if (flow_type == IRQ_TYPE_NONE) | |
883 | flow_type = IRQ_TYPE_LEVEL_LOW; | |
884 | ||
24a3f2e8 | 885 | irqd_set_trigger_type(d, flow_type); |
6e99e458 BH |
886 | |
887 | if (mpic_is_ht_interrupt(mpic, src)) | |
888 | vecpri = MPIC_VECPRI_POLARITY_POSITIVE | | |
889 | MPIC_VECPRI_SENSE_EDGE; | |
890 | else | |
7233593b | 891 | vecpri = mpic_type_to_vecpri(mpic, flow_type); |
6e99e458 | 892 | |
7233593b ZR |
893 | vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); |
894 | vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) | | |
895 | MPIC_INFO(VECPRI_SENSE_MASK)); | |
6e99e458 BH |
896 | vnew |= vecpri; |
897 | if (vold != vnew) | |
7233593b | 898 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew); |
6e99e458 | 899 | |
e075cd70 | 900 | return IRQ_SET_MASK_OK_NOCOPY; |
0ebfff14 BH |
901 | } |
902 | ||
38958dd9 OJ |
903 | void mpic_set_vector(unsigned int virq, unsigned int vector) |
904 | { | |
905 | struct mpic *mpic = mpic_from_irq(virq); | |
476eb491 | 906 | unsigned int src = virq_to_hw(virq); |
38958dd9 OJ |
907 | unsigned int vecpri; |
908 | ||
909 | DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n", | |
910 | mpic, virq, src, vector); | |
911 | ||
912 | if (src >= mpic->irq_count) | |
913 | return; | |
914 | ||
915 | vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); | |
916 | vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK); | |
917 | vecpri |= vector; | |
918 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); | |
919 | } | |
920 | ||
dfec2202 MI |
921 | void mpic_set_destination(unsigned int virq, unsigned int cpuid) |
922 | { | |
923 | struct mpic *mpic = mpic_from_irq(virq); | |
476eb491 | 924 | unsigned int src = virq_to_hw(virq); |
dfec2202 MI |
925 | |
926 | DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n", | |
927 | mpic, virq, src, cpuid); | |
928 | ||
929 | if (src >= mpic->irq_count) | |
930 | return; | |
931 | ||
932 | mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid); | |
933 | } | |
934 | ||
b9e5b4e6 | 935 | static struct irq_chip mpic_irq_chip = { |
835c0553 LB |
936 | .irq_mask = mpic_mask_irq, |
937 | .irq_unmask = mpic_unmask_irq, | |
938 | .irq_eoi = mpic_end_irq, | |
939 | .irq_set_type = mpic_set_irq_type, | |
b9e5b4e6 BH |
940 | }; |
941 | ||
942 | #ifdef CONFIG_SMP | |
943 | static struct irq_chip mpic_ipi_chip = { | |
835c0553 LB |
944 | .irq_mask = mpic_mask_ipi, |
945 | .irq_unmask = mpic_unmask_ipi, | |
946 | .irq_eoi = mpic_end_ipi, | |
b9e5b4e6 BH |
947 | }; |
948 | #endif /* CONFIG_SMP */ | |
949 | ||
ea94187f SW |
950 | static struct irq_chip mpic_tm_chip = { |
951 | .irq_mask = mpic_mask_tm, | |
952 | .irq_unmask = mpic_unmask_tm, | |
953 | .irq_eoi = mpic_end_irq, | |
954 | }; | |
955 | ||
6cfef5b2 | 956 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
b9e5b4e6 | 957 | static struct irq_chip mpic_irq_ht_chip = { |
835c0553 LB |
958 | .irq_startup = mpic_startup_ht_irq, |
959 | .irq_shutdown = mpic_shutdown_ht_irq, | |
960 | .irq_mask = mpic_mask_irq, | |
961 | .irq_unmask = mpic_unmask_ht_irq, | |
962 | .irq_eoi = mpic_end_ht_irq, | |
963 | .irq_set_type = mpic_set_irq_type, | |
b9e5b4e6 | 964 | }; |
6cfef5b2 | 965 | #endif /* CONFIG_MPIC_U3_HT_IRQS */ |
b9e5b4e6 | 966 | |
14cf11af | 967 | |
bae1d8f1 | 968 | static int mpic_host_match(struct irq_domain *h, struct device_node *node) |
0ebfff14 | 969 | { |
0ebfff14 | 970 | /* Exact match, unless mpic node is NULL */ |
52964f87 | 971 | return h->of_node == NULL || h->of_node == node; |
0ebfff14 BH |
972 | } |
973 | ||
bae1d8f1 | 974 | static int mpic_host_map(struct irq_domain *h, unsigned int virq, |
6e99e458 | 975 | irq_hw_number_t hw) |
0ebfff14 | 976 | { |
0ebfff14 | 977 | struct mpic *mpic = h->host_data; |
6e99e458 | 978 | struct irq_chip *chip; |
0ebfff14 | 979 | |
06fe98e6 | 980 | DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw); |
0ebfff14 | 981 | |
7df2457d | 982 | if (hw == mpic->spurious_vec) |
0ebfff14 | 983 | return -EINVAL; |
7fd72186 BH |
984 | if (mpic->protected && test_bit(hw, mpic->protected)) |
985 | return -EINVAL; | |
06fe98e6 | 986 | |
0ebfff14 | 987 | #ifdef CONFIG_SMP |
7df2457d | 988 | else if (hw >= mpic->ipi_vecs[0]) { |
be8bec56 | 989 | WARN_ON(mpic->flags & MPIC_SECONDARY); |
0ebfff14 | 990 | |
06fe98e6 | 991 | DBG("mpic: mapping as IPI\n"); |
ec775d0e TG |
992 | irq_set_chip_data(virq, mpic); |
993 | irq_set_chip_and_handler(virq, &mpic->hc_ipi, | |
0ebfff14 BH |
994 | handle_percpu_irq); |
995 | return 0; | |
996 | } | |
997 | #endif /* CONFIG_SMP */ | |
998 | ||
ea94187f | 999 | if (hw >= mpic->timer_vecs[0] && hw <= mpic->timer_vecs[7]) { |
be8bec56 | 1000 | WARN_ON(mpic->flags & MPIC_SECONDARY); |
ea94187f SW |
1001 | |
1002 | DBG("mpic: mapping as timer\n"); | |
1003 | irq_set_chip_data(virq, mpic); | |
1004 | irq_set_chip_and_handler(virq, &mpic->hc_tm, | |
1005 | handle_fasteoi_irq); | |
1006 | return 0; | |
1007 | } | |
1008 | ||
0ebfff14 BH |
1009 | if (hw >= mpic->irq_count) |
1010 | return -EINVAL; | |
1011 | ||
a7de7c74 ME |
1012 | mpic_msi_reserve_hwirq(mpic, hw); |
1013 | ||
6e99e458 | 1014 | /* Default chip */ |
0ebfff14 BH |
1015 | chip = &mpic->hc_irq; |
1016 | ||
6cfef5b2 | 1017 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
0ebfff14 | 1018 | /* Check for HT interrupts, override vecpri */ |
6e99e458 | 1019 | if (mpic_is_ht_interrupt(mpic, hw)) |
0ebfff14 | 1020 | chip = &mpic->hc_ht_irq; |
6cfef5b2 | 1021 | #endif /* CONFIG_MPIC_U3_HT_IRQS */ |
0ebfff14 | 1022 | |
06fe98e6 | 1023 | DBG("mpic: mapping to irq chip @%p\n", chip); |
0ebfff14 | 1024 | |
ec775d0e TG |
1025 | irq_set_chip_data(virq, mpic); |
1026 | irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq); | |
6e99e458 BH |
1027 | |
1028 | /* Set default irq type */ | |
ec775d0e | 1029 | irq_set_irq_type(virq, IRQ_TYPE_NONE); |
6e99e458 | 1030 | |
dfec2202 MI |
1031 | /* If the MPIC was reset, then all vectors have already been |
1032 | * initialized. Otherwise, a per source lazy initialization | |
1033 | * is done here. | |
1034 | */ | |
1035 | if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) { | |
dfec2202 | 1036 | mpic_set_vector(virq, hw); |
d6a2639b | 1037 | mpic_set_destination(virq, mpic_processor_id(mpic)); |
dfec2202 MI |
1038 | mpic_irq_set_priority(virq, 8); |
1039 | } | |
1040 | ||
0ebfff14 BH |
1041 | return 0; |
1042 | } | |
1043 | ||
bae1d8f1 | 1044 | static int mpic_host_xlate(struct irq_domain *h, struct device_node *ct, |
40d50cf7 | 1045 | const u32 *intspec, unsigned int intsize, |
0ebfff14 BH |
1046 | irq_hw_number_t *out_hwirq, unsigned int *out_flags) |
1047 | ||
1048 | { | |
22d168ce | 1049 | struct mpic *mpic = h->host_data; |
0ebfff14 BH |
1050 | static unsigned char map_mpic_senses[4] = { |
1051 | IRQ_TYPE_EDGE_RISING, | |
1052 | IRQ_TYPE_LEVEL_LOW, | |
1053 | IRQ_TYPE_LEVEL_HIGH, | |
1054 | IRQ_TYPE_EDGE_FALLING, | |
1055 | }; | |
1056 | ||
1057 | *out_hwirq = intspec[0]; | |
22d168ce SW |
1058 | if (intsize >= 4 && (mpic->flags & MPIC_FSL)) { |
1059 | /* | |
1060 | * Freescale MPIC with extended intspec: | |
1061 | * First two cells are as usual. Third specifies | |
1062 | * an "interrupt type". Fourth is type-specific data. | |
1063 | * | |
1064 | * See Documentation/devicetree/bindings/powerpc/fsl/mpic.txt | |
1065 | */ | |
1066 | switch (intspec[2]) { | |
1067 | case 0: | |
1068 | case 1: /* no EISR/EIMR support for now, treat as shared IRQ */ | |
1069 | break; | |
1070 | case 2: | |
1071 | if (intspec[0] >= ARRAY_SIZE(mpic->ipi_vecs)) | |
1072 | return -EINVAL; | |
1073 | ||
1074 | *out_hwirq = mpic->ipi_vecs[intspec[0]]; | |
1075 | break; | |
1076 | case 3: | |
1077 | if (intspec[0] >= ARRAY_SIZE(mpic->timer_vecs)) | |
1078 | return -EINVAL; | |
1079 | ||
1080 | *out_hwirq = mpic->timer_vecs[intspec[0]]; | |
1081 | break; | |
1082 | default: | |
1083 | pr_debug("%s: unknown irq type %u\n", | |
1084 | __func__, intspec[2]); | |
1085 | return -EINVAL; | |
1086 | } | |
1087 | ||
1088 | *out_flags = map_mpic_senses[intspec[1] & 3]; | |
1089 | } else if (intsize > 1) { | |
06fe98e6 BH |
1090 | u32 mask = 0x3; |
1091 | ||
1092 | /* Apple invented a new race of encoding on machines with | |
1093 | * an HT APIC. They encode, among others, the index within | |
1094 | * the HT APIC. We don't care about it here since thankfully, | |
1095 | * it appears that they have the APIC already properly | |
1096 | * configured, and thus our current fixup code that reads the | |
1097 | * APIC config works fine. However, we still need to mask out | |
1098 | * bits in the specifier to make sure we only get bit 0 which | |
1099 | * is the level/edge bit (the only sense bit exposed by Apple), | |
1100 | * as their bit 1 means something else. | |
1101 | */ | |
1102 | if (machine_is(powermac)) | |
1103 | mask = 0x1; | |
1104 | *out_flags = map_mpic_senses[intspec[1] & mask]; | |
1105 | } else | |
0ebfff14 BH |
1106 | *out_flags = IRQ_TYPE_NONE; |
1107 | ||
06fe98e6 BH |
1108 | DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n", |
1109 | intsize, intspec[0], intspec[1], *out_hwirq, *out_flags); | |
1110 | ||
0ebfff14 BH |
1111 | return 0; |
1112 | } | |
1113 | ||
09dc34a9 KM |
1114 | /* IRQ handler for a secondary MPIC cascaded from another IRQ controller */ |
1115 | static void mpic_cascade(unsigned int irq, struct irq_desc *desc) | |
1116 | { | |
1117 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
1118 | struct mpic *mpic = irq_desc_get_handler_data(desc); | |
1119 | unsigned int virq; | |
1120 | ||
1121 | BUG_ON(!(mpic->flags & MPIC_SECONDARY)); | |
1122 | ||
1123 | virq = mpic_get_one_irq(mpic); | |
bae1d8f1 | 1124 | if (virq) |
09dc34a9 KM |
1125 | generic_handle_irq(virq); |
1126 | ||
1127 | chip->irq_eoi(&desc->irq_data); | |
1128 | } | |
1129 | ||
bae1d8f1 | 1130 | static struct irq_domain_ops mpic_host_ops = { |
0ebfff14 BH |
1131 | .match = mpic_host_match, |
1132 | .map = mpic_host_map, | |
1133 | .xlate = mpic_host_xlate, | |
1134 | }; | |
1135 | ||
14cf11af PM |
1136 | /* |
1137 | * Exported functions | |
1138 | */ | |
1139 | ||
0ebfff14 | 1140 | struct mpic * __init mpic_alloc(struct device_node *node, |
a959ff56 | 1141 | phys_addr_t phys_addr, |
14cf11af PM |
1142 | unsigned int flags, |
1143 | unsigned int isu_size, | |
14cf11af | 1144 | unsigned int irq_count, |
14cf11af PM |
1145 | const char *name) |
1146 | { | |
5bdb6f2e KM |
1147 | int i, psize, intvec_top; |
1148 | struct mpic *mpic; | |
1149 | u32 greg_feature; | |
1150 | const char *vers; | |
1151 | const u32 *psrc; | |
8bf41568 | 1152 | |
996983b7 KM |
1153 | /* Default MPIC search parameters */ |
1154 | static const struct of_device_id __initconst mpic_device_id[] = { | |
1155 | { .type = "open-pic", }, | |
1156 | { .compatible = "open-pic", }, | |
1157 | {}, | |
1158 | }; | |
1159 | ||
1160 | /* | |
1161 | * If we were not passed a device-tree node, then perform the default | |
1162 | * search for standardized a standardized OpenPIC. | |
1163 | */ | |
1164 | if (node) { | |
1165 | node = of_node_get(node); | |
1166 | } else { | |
1167 | node = of_find_matching_node(NULL, mpic_device_id); | |
1168 | if (!node) | |
1169 | return NULL; | |
1170 | } | |
8bf41568 | 1171 | |
5bdb6f2e KM |
1172 | /* Pick the physical address from the device tree if unspecified */ |
1173 | if (!phys_addr) { | |
8bf41568 KM |
1174 | /* Check if it is DCR-based */ |
1175 | if (of_get_property(node, "dcr-reg", NULL)) { | |
1176 | flags |= MPIC_USES_DCR; | |
1177 | } else { | |
1178 | struct resource r; | |
1179 | if (of_address_to_resource(node, 0, &r)) | |
996983b7 | 1180 | goto err_of_node_put; |
8bf41568 KM |
1181 | phys_addr = r.start; |
1182 | } | |
1183 | } | |
14cf11af | 1184 | |
85355bb2 | 1185 | mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL); |
14cf11af | 1186 | if (mpic == NULL) |
996983b7 | 1187 | goto err_of_node_put; |
85355bb2 | 1188 | |
14cf11af | 1189 | mpic->name = name; |
c51242e7 | 1190 | mpic->node = node; |
e7a98675 | 1191 | mpic->paddr = phys_addr; |
14cf11af | 1192 | |
b9e5b4e6 | 1193 | mpic->hc_irq = mpic_irq_chip; |
b27df672 | 1194 | mpic->hc_irq.name = name; |
be8bec56 | 1195 | if (!(flags & MPIC_SECONDARY)) |
835c0553 | 1196 | mpic->hc_irq.irq_set_affinity = mpic_set_affinity; |
6cfef5b2 | 1197 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
b9e5b4e6 | 1198 | mpic->hc_ht_irq = mpic_irq_ht_chip; |
b27df672 | 1199 | mpic->hc_ht_irq.name = name; |
be8bec56 | 1200 | if (!(flags & MPIC_SECONDARY)) |
835c0553 | 1201 | mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity; |
6cfef5b2 | 1202 | #endif /* CONFIG_MPIC_U3_HT_IRQS */ |
fbf0274e | 1203 | |
14cf11af | 1204 | #ifdef CONFIG_SMP |
b9e5b4e6 | 1205 | mpic->hc_ipi = mpic_ipi_chip; |
b27df672 | 1206 | mpic->hc_ipi.name = name; |
14cf11af PM |
1207 | #endif /* CONFIG_SMP */ |
1208 | ||
ea94187f SW |
1209 | mpic->hc_tm = mpic_tm_chip; |
1210 | mpic->hc_tm.name = name; | |
1211 | ||
14cf11af PM |
1212 | mpic->flags = flags; |
1213 | mpic->isu_size = isu_size; | |
14cf11af | 1214 | mpic->irq_count = irq_count; |
14cf11af | 1215 | mpic->num_sources = 0; /* so far */ |
14cf11af | 1216 | |
7df2457d OJ |
1217 | if (flags & MPIC_LARGE_VECTORS) |
1218 | intvec_top = 2047; | |
1219 | else | |
1220 | intvec_top = 255; | |
1221 | ||
ea94187f SW |
1222 | mpic->timer_vecs[0] = intvec_top - 12; |
1223 | mpic->timer_vecs[1] = intvec_top - 11; | |
1224 | mpic->timer_vecs[2] = intvec_top - 10; | |
1225 | mpic->timer_vecs[3] = intvec_top - 9; | |
1226 | mpic->timer_vecs[4] = intvec_top - 8; | |
1227 | mpic->timer_vecs[5] = intvec_top - 7; | |
1228 | mpic->timer_vecs[6] = intvec_top - 6; | |
1229 | mpic->timer_vecs[7] = intvec_top - 5; | |
7df2457d OJ |
1230 | mpic->ipi_vecs[0] = intvec_top - 4; |
1231 | mpic->ipi_vecs[1] = intvec_top - 3; | |
1232 | mpic->ipi_vecs[2] = intvec_top - 2; | |
1233 | mpic->ipi_vecs[3] = intvec_top - 1; | |
1234 | mpic->spurious_vec = intvec_top; | |
1235 | ||
a959ff56 | 1236 | /* Check for "big-endian" in device-tree */ |
c51242e7 | 1237 | if (of_get_property(mpic->node, "big-endian", NULL) != NULL) |
a959ff56 | 1238 | mpic->flags |= MPIC_BIG_ENDIAN; |
c51242e7 | 1239 | if (of_device_is_compatible(mpic->node, "fsl,mpic")) |
22d168ce | 1240 | mpic->flags |= MPIC_FSL; |
a959ff56 | 1241 | |
7fd72186 | 1242 | /* Look for protected sources */ |
c51242e7 | 1243 | psrc = of_get_property(mpic->node, "protected-sources", &psize); |
5bdb6f2e KM |
1244 | if (psrc) { |
1245 | /* Allocate a bitmap with one bit per interrupt */ | |
1246 | unsigned int mapsize = BITS_TO_LONGS(intvec_top + 1); | |
1247 | mpic->protected = kzalloc(mapsize*sizeof(long), GFP_KERNEL); | |
1248 | BUG_ON(mpic->protected == NULL); | |
1249 | for (i = 0; i < psize/sizeof(u32); i++) { | |
1250 | if (psrc[i] > intvec_top) | |
1251 | continue; | |
1252 | __set_bit(psrc[i], mpic->protected); | |
7fd72186 BH |
1253 | } |
1254 | } | |
a959ff56 | 1255 | |
7233593b ZR |
1256 | #ifdef CONFIG_MPIC_WEIRD |
1257 | mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)]; | |
1258 | #endif | |
1259 | ||
fbf0274e | 1260 | /* default register type */ |
8bf41568 KM |
1261 | if (flags & MPIC_BIG_ENDIAN) |
1262 | mpic->reg_type = mpic_access_mmio_be; | |
1263 | else | |
1264 | mpic->reg_type = mpic_access_mmio_le; | |
a959ff56 | 1265 | |
8bf41568 KM |
1266 | /* |
1267 | * An MPIC with a "dcr-reg" property must be accessed that way, but | |
1268 | * only if the kernel includes DCR support. | |
1269 | */ | |
fbf0274e | 1270 | #ifdef CONFIG_PPC_DCR |
8bf41568 | 1271 | if (flags & MPIC_USES_DCR) |
fbf0274e | 1272 | mpic->reg_type = mpic_access_dcr; |
fbf0274e | 1273 | #else |
8bf41568 KM |
1274 | BUG_ON(flags & MPIC_USES_DCR); |
1275 | #endif | |
a959ff56 | 1276 | |
14cf11af | 1277 | /* Map the global registers */ |
c51242e7 KM |
1278 | mpic_map(mpic, mpic->paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000); |
1279 | mpic_map(mpic, mpic->paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000); | |
14cf11af PM |
1280 | |
1281 | /* Reset */ | |
dfec2202 MI |
1282 | |
1283 | /* When using a device-node, reset requests are only honored if the MPIC | |
1284 | * is allowed to reset. | |
1285 | */ | |
c51242e7 | 1286 | if (of_get_property(mpic->node, "pic-no-reset", NULL)) |
dfec2202 MI |
1287 | mpic->flags |= MPIC_NO_RESET; |
1288 | ||
1289 | if ((flags & MPIC_WANTS_RESET) && !(mpic->flags & MPIC_NO_RESET)) { | |
1290 | printk(KERN_DEBUG "mpic: Resetting\n"); | |
7233593b ZR |
1291 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), |
1292 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) | |
14cf11af | 1293 | | MPIC_GREG_GCONF_RESET); |
7233593b | 1294 | while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) |
14cf11af PM |
1295 | & MPIC_GREG_GCONF_RESET) |
1296 | mb(); | |
1297 | } | |
1298 | ||
d91e4ea7 KG |
1299 | /* CoreInt */ |
1300 | if (flags & MPIC_ENABLE_COREINT) | |
1301 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), | |
1302 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) | |
1303 | | MPIC_GREG_GCONF_COREINT); | |
1304 | ||
f365355e OJ |
1305 | if (flags & MPIC_ENABLE_MCK) |
1306 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), | |
1307 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) | |
1308 | | MPIC_GREG_GCONF_MCK); | |
1309 | ||
14b92470 TT |
1310 | /* |
1311 | * Read feature register. For non-ISU MPICs, num sources as well. On | |
1312 | * ISU MPICs, sources are counted as ISUs are added | |
14cf11af | 1313 | */ |
d9d1063d | 1314 | greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0)); |
5073e7ee | 1315 | if (isu_size == 0) { |
475ca391 KG |
1316 | if (flags & MPIC_BROKEN_FRR_NIRQS) |
1317 | mpic->num_sources = mpic->irq_count; | |
1318 | else | |
1319 | mpic->num_sources = | |
1320 | ((greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK) | |
1321 | >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1; | |
5073e7ee | 1322 | } |
14cf11af | 1323 | |
14b92470 TT |
1324 | /* |
1325 | * The MPIC driver will crash if there are more cores than we | |
1326 | * can initialize, so we may as well catch that problem here. | |
1327 | */ | |
1328 | BUG_ON(num_possible_cpus() > MPIC_MAX_CPUS); | |
1329 | ||
14cf11af | 1330 | /* Map the per-CPU registers */ |
14b92470 TT |
1331 | for_each_possible_cpu(i) { |
1332 | unsigned int cpu = get_hard_smp_processor_id(i); | |
1333 | ||
c51242e7 | 1334 | mpic_map(mpic, mpic->paddr, &mpic->cpuregs[cpu], |
14b92470 | 1335 | MPIC_INFO(CPU_BASE) + cpu * MPIC_INFO(CPU_STRIDE), |
fbf0274e | 1336 | 0x1000); |
14cf11af PM |
1337 | } |
1338 | ||
1339 | /* Initialize main ISU if none provided */ | |
1340 | if (mpic->isu_size == 0) { | |
1341 | mpic->isu_size = mpic->num_sources; | |
c51242e7 | 1342 | mpic_map(mpic, mpic->paddr, &mpic->isus[0], |
fbf0274e | 1343 | MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); |
14cf11af PM |
1344 | } |
1345 | mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1); | |
1346 | mpic->isu_mask = (1 << mpic->isu_shift) - 1; | |
1347 | ||
bae1d8f1 | 1348 | mpic->irqhost = irq_alloc_host(mpic->node, IRQ_DOMAIN_MAP_LINEAR, |
31207dab KG |
1349 | isu_size ? isu_size : mpic->num_sources, |
1350 | &mpic_host_ops, | |
1351 | flags & MPIC_LARGE_VECTORS ? 2048 : 256); | |
996983b7 KM |
1352 | |
1353 | /* | |
1354 | * FIXME: The code leaks the MPIC object and mappings here; this | |
1355 | * is very unlikely to fail but it ought to be fixed anyways. | |
1356 | */ | |
31207dab KG |
1357 | if (mpic->irqhost == NULL) |
1358 | return NULL; | |
1359 | ||
1360 | mpic->irqhost->host_data = mpic; | |
1361 | ||
14cf11af | 1362 | /* Display version */ |
d9d1063d | 1363 | switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) { |
14cf11af PM |
1364 | case 1: |
1365 | vers = "1.0"; | |
1366 | break; | |
1367 | case 2: | |
1368 | vers = "1.2"; | |
1369 | break; | |
1370 | case 3: | |
1371 | vers = "1.3"; | |
1372 | break; | |
1373 | default: | |
1374 | vers = "<unknown>"; | |
1375 | break; | |
1376 | } | |
a959ff56 BH |
1377 | printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx," |
1378 | " max %d CPUs\n", | |
e7a98675 | 1379 | name, vers, (unsigned long long)mpic->paddr, num_possible_cpus()); |
a959ff56 BH |
1380 | printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n", |
1381 | mpic->isu_size, mpic->isu_shift, mpic->isu_mask); | |
14cf11af PM |
1382 | |
1383 | mpic->next = mpics; | |
1384 | mpics = mpic; | |
1385 | ||
be8bec56 | 1386 | if (!(flags & MPIC_SECONDARY)) { |
14cf11af | 1387 | mpic_primary = mpic; |
0ebfff14 BH |
1388 | irq_set_default_host(mpic->irqhost); |
1389 | } | |
14cf11af PM |
1390 | |
1391 | return mpic; | |
996983b7 KM |
1392 | |
1393 | err_of_node_put: | |
1394 | of_node_put(node); | |
1395 | return NULL; | |
14cf11af PM |
1396 | } |
1397 | ||
1398 | void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num, | |
a959ff56 | 1399 | phys_addr_t paddr) |
14cf11af PM |
1400 | { |
1401 | unsigned int isu_first = isu_num * mpic->isu_size; | |
1402 | ||
1403 | BUG_ON(isu_num >= MPIC_MAX_ISU); | |
1404 | ||
c51242e7 | 1405 | mpic_map(mpic, |
5a2642f6 | 1406 | paddr, &mpic->isus[isu_num], 0, |
fbf0274e | 1407 | MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); |
5a2642f6 | 1408 | |
14cf11af PM |
1409 | if ((isu_first + mpic->isu_size) > mpic->num_sources) |
1410 | mpic->num_sources = isu_first + mpic->isu_size; | |
1411 | } | |
1412 | ||
0ebfff14 BH |
1413 | void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count) |
1414 | { | |
1415 | mpic->senses = senses; | |
1416 | mpic->senses_count = count; | |
1417 | } | |
1418 | ||
14cf11af PM |
1419 | void __init mpic_init(struct mpic *mpic) |
1420 | { | |
09dc34a9 | 1421 | int i, cpu; |
14cf11af PM |
1422 | |
1423 | BUG_ON(mpic->num_sources == 0); | |
1424 | ||
1425 | printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources); | |
1426 | ||
1427 | /* Set current processor priority to max */ | |
7233593b | 1428 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf); |
14cf11af | 1429 | |
ea94187f | 1430 | /* Initialize timers to our reserved vectors and mask them for now */ |
14cf11af PM |
1431 | for (i = 0; i < 4; i++) { |
1432 | mpic_write(mpic->tmregs, | |
7233593b | 1433 | i * MPIC_INFO(TIMER_STRIDE) + |
ea94187f SW |
1434 | MPIC_INFO(TIMER_DESTINATION), |
1435 | 1 << hard_smp_processor_id()); | |
14cf11af | 1436 | mpic_write(mpic->tmregs, |
7233593b ZR |
1437 | i * MPIC_INFO(TIMER_STRIDE) + |
1438 | MPIC_INFO(TIMER_VECTOR_PRI), | |
14cf11af | 1439 | MPIC_VECPRI_MASK | |
ea94187f | 1440 | (9 << MPIC_VECPRI_PRIORITY_SHIFT) | |
7df2457d | 1441 | (mpic->timer_vecs[0] + i)); |
14cf11af PM |
1442 | } |
1443 | ||
1444 | /* Initialize IPIs to our reserved vectors and mark them disabled for now */ | |
1445 | mpic_test_broken_ipi(mpic); | |
1446 | for (i = 0; i < 4; i++) { | |
1447 | mpic_ipi_write(i, | |
1448 | MPIC_VECPRI_MASK | | |
1449 | (10 << MPIC_VECPRI_PRIORITY_SHIFT) | | |
7df2457d | 1450 | (mpic->ipi_vecs[0] + i)); |
14cf11af PM |
1451 | } |
1452 | ||
1453 | /* Initialize interrupt sources */ | |
1454 | if (mpic->irq_count == 0) | |
1455 | mpic->irq_count = mpic->num_sources; | |
1456 | ||
1beb6a7d | 1457 | /* Do the HT PIC fixups on U3 broken mpic */ |
14cf11af | 1458 | DBG("MPIC flags: %x\n", mpic->flags); |
be8bec56 | 1459 | if ((mpic->flags & MPIC_U3_HT_IRQS) && !(mpic->flags & MPIC_SECONDARY)) { |
3669e930 | 1460 | mpic_scan_ht_pics(mpic); |
05af7bd2 ME |
1461 | mpic_u3msi_init(mpic); |
1462 | } | |
14cf11af | 1463 | |
38958dd9 OJ |
1464 | mpic_pasemi_msi_init(mpic); |
1465 | ||
d6a2639b | 1466 | cpu = mpic_processor_id(mpic); |
cc353c30 | 1467 | |
dfec2202 MI |
1468 | if (!(mpic->flags & MPIC_NO_RESET)) { |
1469 | for (i = 0; i < mpic->num_sources; i++) { | |
1470 | /* start with vector = source number, and masked */ | |
1471 | u32 vecpri = MPIC_VECPRI_MASK | i | | |
1472 | (8 << MPIC_VECPRI_PRIORITY_SHIFT); | |
14cf11af | 1473 | |
dfec2202 MI |
1474 | /* check if protected */ |
1475 | if (mpic->protected && test_bit(i, mpic->protected)) | |
1476 | continue; | |
1477 | /* init hw */ | |
1478 | mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); | |
1479 | mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu); | |
1480 | } | |
14cf11af PM |
1481 | } |
1482 | ||
7df2457d OJ |
1483 | /* Init spurious vector */ |
1484 | mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec); | |
14cf11af | 1485 | |
7233593b ZR |
1486 | /* Disable 8259 passthrough, if supported */ |
1487 | if (!(mpic->flags & MPIC_NO_PTHROU_DIS)) | |
1488 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), | |
1489 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) | |
1490 | | MPIC_GREG_GCONF_8259_PTHROU_DIS); | |
14cf11af | 1491 | |
d87bf3be OJ |
1492 | if (mpic->flags & MPIC_NO_BIAS) |
1493 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), | |
1494 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) | |
1495 | | MPIC_GREG_GCONF_NO_BIAS); | |
1496 | ||
14cf11af | 1497 | /* Set current processor priority to 0 */ |
7233593b | 1498 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0); |
3669e930 JB |
1499 | |
1500 | #ifdef CONFIG_PM | |
1501 | /* allocate memory to save mpic state */ | |
ea96025a AV |
1502 | mpic->save_data = kmalloc(mpic->num_sources * sizeof(*mpic->save_data), |
1503 | GFP_KERNEL); | |
3669e930 JB |
1504 | BUG_ON(mpic->save_data == NULL); |
1505 | #endif | |
09dc34a9 KM |
1506 | |
1507 | /* Check if this MPIC is chained from a parent interrupt controller */ | |
1508 | if (mpic->flags & MPIC_SECONDARY) { | |
1509 | int virq = irq_of_parse_and_map(mpic->node, 0); | |
1510 | if (virq != NO_IRQ) { | |
1511 | printk(KERN_INFO "%s: hooking up to IRQ %d\n", | |
1512 | mpic->node->full_name, virq); | |
1513 | irq_set_handler_data(virq, mpic); | |
1514 | irq_set_chained_handler(virq, &mpic_cascade); | |
1515 | } | |
1516 | } | |
14cf11af PM |
1517 | } |
1518 | ||
868ea0c9 MG |
1519 | void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio) |
1520 | { | |
1521 | u32 v; | |
1522 | ||
1523 | v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1); | |
1524 | v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK; | |
1525 | v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio); | |
1526 | mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v); | |
1527 | } | |
14cf11af | 1528 | |
868ea0c9 MG |
1529 | void __init mpic_set_serial_int(struct mpic *mpic, int enable) |
1530 | { | |
ba1826e5 | 1531 | unsigned long flags; |
868ea0c9 MG |
1532 | u32 v; |
1533 | ||
203041ad | 1534 | raw_spin_lock_irqsave(&mpic_lock, flags); |
868ea0c9 MG |
1535 | v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1); |
1536 | if (enable) | |
1537 | v |= MPIC_GREG_GLOBAL_CONF_1_SIE; | |
1538 | else | |
1539 | v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE; | |
1540 | mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v); | |
203041ad | 1541 | raw_spin_unlock_irqrestore(&mpic_lock, flags); |
868ea0c9 | 1542 | } |
14cf11af PM |
1543 | |
1544 | void mpic_irq_set_priority(unsigned int irq, unsigned int pri) | |
1545 | { | |
d69a78d7 | 1546 | struct mpic *mpic = mpic_find(irq); |
476eb491 | 1547 | unsigned int src = virq_to_hw(irq); |
14cf11af PM |
1548 | unsigned long flags; |
1549 | u32 reg; | |
1550 | ||
06a901c5 SR |
1551 | if (!mpic) |
1552 | return; | |
1553 | ||
203041ad | 1554 | raw_spin_lock_irqsave(&mpic_lock, flags); |
d69a78d7 | 1555 | if (mpic_is_ipi(mpic, irq)) { |
7df2457d | 1556 | reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) & |
e5356640 | 1557 | ~MPIC_VECPRI_PRIORITY_MASK; |
7df2457d | 1558 | mpic_ipi_write(src - mpic->ipi_vecs[0], |
14cf11af | 1559 | reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); |
ea94187f SW |
1560 | } else if (mpic_is_tm(mpic, irq)) { |
1561 | reg = mpic_tm_read(src - mpic->timer_vecs[0]) & | |
1562 | ~MPIC_VECPRI_PRIORITY_MASK; | |
1563 | mpic_tm_write(src - mpic->timer_vecs[0], | |
1564 | reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); | |
14cf11af | 1565 | } else { |
7233593b | 1566 | reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
e5356640 | 1567 | & ~MPIC_VECPRI_PRIORITY_MASK; |
7233593b | 1568 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), |
14cf11af PM |
1569 | reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); |
1570 | } | |
203041ad | 1571 | raw_spin_unlock_irqrestore(&mpic_lock, flags); |
14cf11af PM |
1572 | } |
1573 | ||
14cf11af PM |
1574 | void mpic_setup_this_cpu(void) |
1575 | { | |
1576 | #ifdef CONFIG_SMP | |
1577 | struct mpic *mpic = mpic_primary; | |
1578 | unsigned long flags; | |
1579 | u32 msk = 1 << hard_smp_processor_id(); | |
1580 | unsigned int i; | |
1581 | ||
1582 | BUG_ON(mpic == NULL); | |
1583 | ||
1584 | DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); | |
1585 | ||
203041ad | 1586 | raw_spin_lock_irqsave(&mpic_lock, flags); |
14cf11af PM |
1587 | |
1588 | /* let the mpic know we want intrs. default affinity is 0xffffffff | |
1589 | * until changed via /proc. That's how it's done on x86. If we want | |
1590 | * it differently, then we should make sure we also change the default | |
a53da52f | 1591 | * values of irq_desc[].affinity in irq.c. |
14cf11af PM |
1592 | */ |
1593 | if (distribute_irqs) { | |
1594 | for (i = 0; i < mpic->num_sources ; i++) | |
7233593b ZR |
1595 | mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), |
1596 | mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk); | |
14cf11af PM |
1597 | } |
1598 | ||
1599 | /* Set current processor priority to 0 */ | |
7233593b | 1600 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0); |
14cf11af | 1601 | |
203041ad | 1602 | raw_spin_unlock_irqrestore(&mpic_lock, flags); |
14cf11af PM |
1603 | #endif /* CONFIG_SMP */ |
1604 | } | |
1605 | ||
1606 | int mpic_cpu_get_priority(void) | |
1607 | { | |
1608 | struct mpic *mpic = mpic_primary; | |
1609 | ||
7233593b | 1610 | return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI)); |
14cf11af PM |
1611 | } |
1612 | ||
1613 | void mpic_cpu_set_priority(int prio) | |
1614 | { | |
1615 | struct mpic *mpic = mpic_primary; | |
1616 | ||
1617 | prio &= MPIC_CPU_TASKPRI_MASK; | |
7233593b | 1618 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio); |
14cf11af PM |
1619 | } |
1620 | ||
14cf11af PM |
1621 | void mpic_teardown_this_cpu(int secondary) |
1622 | { | |
1623 | struct mpic *mpic = mpic_primary; | |
1624 | unsigned long flags; | |
1625 | u32 msk = 1 << hard_smp_processor_id(); | |
1626 | unsigned int i; | |
1627 | ||
1628 | BUG_ON(mpic == NULL); | |
1629 | ||
1630 | DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); | |
203041ad | 1631 | raw_spin_lock_irqsave(&mpic_lock, flags); |
14cf11af PM |
1632 | |
1633 | /* let the mpic know we don't want intrs. */ | |
1634 | for (i = 0; i < mpic->num_sources ; i++) | |
7233593b ZR |
1635 | mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), |
1636 | mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk); | |
14cf11af PM |
1637 | |
1638 | /* Set current processor priority to max */ | |
7233593b | 1639 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf); |
7132799b VB |
1640 | /* We need to EOI the IPI since not all platforms reset the MPIC |
1641 | * on boot and new interrupts wouldn't get delivered otherwise. | |
1642 | */ | |
1643 | mpic_eoi(mpic); | |
14cf11af | 1644 | |
203041ad | 1645 | raw_spin_unlock_irqrestore(&mpic_lock, flags); |
14cf11af PM |
1646 | } |
1647 | ||
1648 | ||
f365355e | 1649 | static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg) |
14cf11af | 1650 | { |
0ebfff14 | 1651 | u32 src; |
14cf11af | 1652 | |
f365355e | 1653 | src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK); |
1beb6a7d | 1654 | #ifdef DEBUG_LOW |
f365355e | 1655 | DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src); |
1beb6a7d | 1656 | #endif |
5cddd2e3 JB |
1657 | if (unlikely(src == mpic->spurious_vec)) { |
1658 | if (mpic->flags & MPIC_SPV_EOI) | |
1659 | mpic_eoi(mpic); | |
0ebfff14 | 1660 | return NO_IRQ; |
5cddd2e3 | 1661 | } |
7fd72186 | 1662 | if (unlikely(mpic->protected && test_bit(src, mpic->protected))) { |
76462232 CD |
1663 | printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n", |
1664 | mpic->name, (int)src); | |
7fd72186 BH |
1665 | mpic_eoi(mpic); |
1666 | return NO_IRQ; | |
1667 | } | |
1668 | ||
0ebfff14 | 1669 | return irq_linear_revmap(mpic->irqhost, src); |
14cf11af PM |
1670 | } |
1671 | ||
f365355e OJ |
1672 | unsigned int mpic_get_one_irq(struct mpic *mpic) |
1673 | { | |
1674 | return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK)); | |
1675 | } | |
1676 | ||
35a84c2f | 1677 | unsigned int mpic_get_irq(void) |
14cf11af PM |
1678 | { |
1679 | struct mpic *mpic = mpic_primary; | |
1680 | ||
1681 | BUG_ON(mpic == NULL); | |
1682 | ||
35a84c2f | 1683 | return mpic_get_one_irq(mpic); |
14cf11af PM |
1684 | } |
1685 | ||
d91e4ea7 KG |
1686 | unsigned int mpic_get_coreint_irq(void) |
1687 | { | |
1688 | #ifdef CONFIG_BOOKE | |
1689 | struct mpic *mpic = mpic_primary; | |
1690 | u32 src; | |
1691 | ||
1692 | BUG_ON(mpic == NULL); | |
1693 | ||
1694 | src = mfspr(SPRN_EPR); | |
1695 | ||
1696 | if (unlikely(src == mpic->spurious_vec)) { | |
1697 | if (mpic->flags & MPIC_SPV_EOI) | |
1698 | mpic_eoi(mpic); | |
1699 | return NO_IRQ; | |
1700 | } | |
1701 | if (unlikely(mpic->protected && test_bit(src, mpic->protected))) { | |
76462232 CD |
1702 | printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n", |
1703 | mpic->name, (int)src); | |
d91e4ea7 KG |
1704 | return NO_IRQ; |
1705 | } | |
1706 | ||
1707 | return irq_linear_revmap(mpic->irqhost, src); | |
1708 | #else | |
1709 | return NO_IRQ; | |
1710 | #endif | |
1711 | } | |
1712 | ||
f365355e OJ |
1713 | unsigned int mpic_get_mcirq(void) |
1714 | { | |
1715 | struct mpic *mpic = mpic_primary; | |
1716 | ||
1717 | BUG_ON(mpic == NULL); | |
1718 | ||
1719 | return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK)); | |
1720 | } | |
14cf11af PM |
1721 | |
1722 | #ifdef CONFIG_SMP | |
1723 | void mpic_request_ipis(void) | |
1724 | { | |
1725 | struct mpic *mpic = mpic_primary; | |
78608dd3 | 1726 | int i; |
14cf11af | 1727 | BUG_ON(mpic == NULL); |
14cf11af | 1728 | |
8354be9c | 1729 | printk(KERN_INFO "mpic: requesting IPIs...\n"); |
0ebfff14 BH |
1730 | |
1731 | for (i = 0; i < 4; i++) { | |
1732 | unsigned int vipi = irq_create_mapping(mpic->irqhost, | |
7df2457d | 1733 | mpic->ipi_vecs[0] + i); |
0ebfff14 | 1734 | if (vipi == NO_IRQ) { |
78608dd3 MM |
1735 | printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]); |
1736 | continue; | |
d16f1b64 | 1737 | } |
78608dd3 | 1738 | smp_request_message_ipi(vipi, i); |
0ebfff14 | 1739 | } |
14cf11af | 1740 | } |
a9c59264 | 1741 | |
3caba98f | 1742 | void smp_mpic_message_pass(int cpu, int msg) |
2ef613cb BH |
1743 | { |
1744 | struct mpic *mpic = mpic_primary; | |
3caba98f | 1745 | u32 physmask; |
2ef613cb BH |
1746 | |
1747 | BUG_ON(mpic == NULL); | |
1748 | ||
a9c59264 PM |
1749 | /* make sure we're sending something that translates to an IPI */ |
1750 | if ((unsigned int)msg > 3) { | |
1751 | printk("SMP %d: smp_message_pass: unknown msg %d\n", | |
1752 | smp_processor_id(), msg); | |
1753 | return; | |
1754 | } | |
3caba98f MM |
1755 | |
1756 | #ifdef DEBUG_IPI | |
1757 | DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, msg); | |
1758 | #endif | |
1759 | ||
1760 | physmask = 1 << get_hard_smp_processor_id(cpu); | |
1761 | ||
1762 | mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) + | |
1763 | msg * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE), physmask); | |
a9c59264 | 1764 | } |
775aeff4 ME |
1765 | |
1766 | int __init smp_mpic_probe(void) | |
1767 | { | |
1768 | int nr_cpus; | |
1769 | ||
1770 | DBG("smp_mpic_probe()...\n"); | |
1771 | ||
2ef613cb | 1772 | nr_cpus = cpumask_weight(cpu_possible_mask); |
775aeff4 ME |
1773 | |
1774 | DBG("nr_cpus: %d\n", nr_cpus); | |
1775 | ||
1776 | if (nr_cpus > 1) | |
1777 | mpic_request_ipis(); | |
1778 | ||
1779 | return nr_cpus; | |
1780 | } | |
1781 | ||
1782 | void __devinit smp_mpic_setup_cpu(int cpu) | |
1783 | { | |
1784 | mpic_setup_this_cpu(); | |
1785 | } | |
66953ebe MM |
1786 | |
1787 | void mpic_reset_core(int cpu) | |
1788 | { | |
1789 | struct mpic *mpic = mpic_primary; | |
1790 | u32 pir; | |
1791 | int cpuid = get_hard_smp_processor_id(cpu); | |
44f16fcf | 1792 | int i; |
66953ebe MM |
1793 | |
1794 | /* Set target bit for core reset */ | |
1795 | pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT)); | |
1796 | pir |= (1 << cpuid); | |
1797 | mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir); | |
1798 | mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT)); | |
1799 | ||
1800 | /* Restore target bit after reset complete */ | |
1801 | pir &= ~(1 << cpuid); | |
1802 | mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir); | |
1803 | mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT)); | |
44f16fcf MM |
1804 | |
1805 | /* Perform 15 EOI on each reset core to clear pending interrupts. | |
1806 | * This is required for FSL CoreNet based devices */ | |
1807 | if (mpic->flags & MPIC_FSL) { | |
1808 | for (i = 0; i < 15; i++) { | |
1809 | _mpic_write(mpic->reg_type, &mpic->cpuregs[cpuid], | |
1810 | MPIC_CPU_EOI, 0); | |
1811 | } | |
1812 | } | |
66953ebe | 1813 | } |
14cf11af | 1814 | #endif /* CONFIG_SMP */ |
3669e930 JB |
1815 | |
1816 | #ifdef CONFIG_PM | |
f5a592f7 | 1817 | static void mpic_suspend_one(struct mpic *mpic) |
3669e930 | 1818 | { |
3669e930 JB |
1819 | int i; |
1820 | ||
1821 | for (i = 0; i < mpic->num_sources; i++) { | |
1822 | mpic->save_data[i].vecprio = | |
1823 | mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI)); | |
1824 | mpic->save_data[i].dest = | |
1825 | mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)); | |
1826 | } | |
f5a592f7 RW |
1827 | } |
1828 | ||
1829 | static int mpic_suspend(void) | |
1830 | { | |
1831 | struct mpic *mpic = mpics; | |
1832 | ||
1833 | while (mpic) { | |
1834 | mpic_suspend_one(mpic); | |
1835 | mpic = mpic->next; | |
1836 | } | |
3669e930 JB |
1837 | |
1838 | return 0; | |
1839 | } | |
1840 | ||
f5a592f7 | 1841 | static void mpic_resume_one(struct mpic *mpic) |
3669e930 | 1842 | { |
3669e930 JB |
1843 | int i; |
1844 | ||
1845 | for (i = 0; i < mpic->num_sources; i++) { | |
1846 | mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), | |
1847 | mpic->save_data[i].vecprio); | |
1848 | mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), | |
1849 | mpic->save_data[i].dest); | |
1850 | ||
1851 | #ifdef CONFIG_MPIC_U3_HT_IRQS | |
7c9d9360 | 1852 | if (mpic->fixups) { |
3669e930 JB |
1853 | struct mpic_irq_fixup *fixup = &mpic->fixups[i]; |
1854 | ||
1855 | if (fixup->base) { | |
1856 | /* we use the lowest bit in an inverted meaning */ | |
1857 | if ((mpic->save_data[i].fixup_data & 1) == 0) | |
1858 | continue; | |
1859 | ||
1860 | /* Enable and configure */ | |
1861 | writeb(0x10 + 2 * fixup->index, fixup->base + 2); | |
1862 | ||
1863 | writel(mpic->save_data[i].fixup_data & ~1, | |
1864 | fixup->base + 4); | |
1865 | } | |
1866 | } | |
1867 | #endif | |
1868 | } /* end for loop */ | |
f5a592f7 | 1869 | } |
3669e930 | 1870 | |
f5a592f7 RW |
1871 | static void mpic_resume(void) |
1872 | { | |
1873 | struct mpic *mpic = mpics; | |
1874 | ||
1875 | while (mpic) { | |
1876 | mpic_resume_one(mpic); | |
1877 | mpic = mpic->next; | |
1878 | } | |
3669e930 | 1879 | } |
3669e930 | 1880 | |
f5a592f7 | 1881 | static struct syscore_ops mpic_syscore_ops = { |
3669e930 JB |
1882 | .resume = mpic_resume, |
1883 | .suspend = mpic_suspend, | |
3669e930 JB |
1884 | }; |
1885 | ||
1886 | static int mpic_init_sys(void) | |
1887 | { | |
f5a592f7 RW |
1888 | register_syscore_ops(&mpic_syscore_ops); |
1889 | return 0; | |
3669e930 JB |
1890 | } |
1891 | ||
1892 | device_initcall(mpic_init_sys); | |
f5a592f7 | 1893 | #endif |