Commit | Line | Data |
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14cf11af PM |
1 | /* |
2 | * arch/powerpc/kernel/mpic.c | |
3 | * | |
4 | * Driver for interrupt controllers following the OpenPIC standard, the | |
5 | * common implementation beeing IBM's MPIC. This driver also can deal | |
6 | * with various broken implementations of this HW. | |
7 | * | |
8 | * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp. | |
9 | * | |
10 | * This file is subject to the terms and conditions of the GNU General Public | |
11 | * License. See the file COPYING in the main directory of this archive | |
12 | * for more details. | |
13 | */ | |
14 | ||
15 | #undef DEBUG | |
1beb6a7d BH |
16 | #undef DEBUG_IPI |
17 | #undef DEBUG_IRQ | |
18 | #undef DEBUG_LOW | |
14cf11af | 19 | |
14cf11af PM |
20 | #include <linux/types.h> |
21 | #include <linux/kernel.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/irq.h> | |
24 | #include <linux/smp.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/bootmem.h> | |
27 | #include <linux/spinlock.h> | |
28 | #include <linux/pci.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
14cf11af PM |
30 | |
31 | #include <asm/ptrace.h> | |
32 | #include <asm/signal.h> | |
33 | #include <asm/io.h> | |
34 | #include <asm/pgtable.h> | |
35 | #include <asm/irq.h> | |
36 | #include <asm/machdep.h> | |
37 | #include <asm/mpic.h> | |
38 | #include <asm/smp.h> | |
39 | ||
a7de7c74 ME |
40 | #include "mpic.h" |
41 | ||
14cf11af PM |
42 | #ifdef DEBUG |
43 | #define DBG(fmt...) printk(fmt) | |
44 | #else | |
45 | #define DBG(fmt...) | |
46 | #endif | |
47 | ||
48 | static struct mpic *mpics; | |
49 | static struct mpic *mpic_primary; | |
203041ad | 50 | static DEFINE_RAW_SPINLOCK(mpic_lock); |
14cf11af | 51 | |
c0c0d996 | 52 | #ifdef CONFIG_PPC32 /* XXX for now */ |
e40c7f02 AW |
53 | #ifdef CONFIG_IRQ_ALL_CPUS |
54 | #define distribute_irqs (1) | |
55 | #else | |
56 | #define distribute_irqs (0) | |
57 | #endif | |
c0c0d996 | 58 | #endif |
14cf11af | 59 | |
7233593b ZR |
60 | #ifdef CONFIG_MPIC_WEIRD |
61 | static u32 mpic_infos[][MPIC_IDX_END] = { | |
62 | [0] = { /* Original OpenPIC compatible MPIC */ | |
63 | MPIC_GREG_BASE, | |
64 | MPIC_GREG_FEATURE_0, | |
65 | MPIC_GREG_GLOBAL_CONF_0, | |
66 | MPIC_GREG_VENDOR_ID, | |
67 | MPIC_GREG_IPI_VECTOR_PRI_0, | |
68 | MPIC_GREG_IPI_STRIDE, | |
69 | MPIC_GREG_SPURIOUS, | |
70 | MPIC_GREG_TIMER_FREQ, | |
71 | ||
72 | MPIC_TIMER_BASE, | |
73 | MPIC_TIMER_STRIDE, | |
74 | MPIC_TIMER_CURRENT_CNT, | |
75 | MPIC_TIMER_BASE_CNT, | |
76 | MPIC_TIMER_VECTOR_PRI, | |
77 | MPIC_TIMER_DESTINATION, | |
78 | ||
79 | MPIC_CPU_BASE, | |
80 | MPIC_CPU_STRIDE, | |
81 | MPIC_CPU_IPI_DISPATCH_0, | |
82 | MPIC_CPU_IPI_DISPATCH_STRIDE, | |
83 | MPIC_CPU_CURRENT_TASK_PRI, | |
84 | MPIC_CPU_WHOAMI, | |
85 | MPIC_CPU_INTACK, | |
86 | MPIC_CPU_EOI, | |
f365355e | 87 | MPIC_CPU_MCACK, |
7233593b ZR |
88 | |
89 | MPIC_IRQ_BASE, | |
90 | MPIC_IRQ_STRIDE, | |
91 | MPIC_IRQ_VECTOR_PRI, | |
92 | MPIC_VECPRI_VECTOR_MASK, | |
93 | MPIC_VECPRI_POLARITY_POSITIVE, | |
94 | MPIC_VECPRI_POLARITY_NEGATIVE, | |
95 | MPIC_VECPRI_SENSE_LEVEL, | |
96 | MPIC_VECPRI_SENSE_EDGE, | |
97 | MPIC_VECPRI_POLARITY_MASK, | |
98 | MPIC_VECPRI_SENSE_MASK, | |
99 | MPIC_IRQ_DESTINATION | |
100 | }, | |
101 | [1] = { /* Tsi108/109 PIC */ | |
102 | TSI108_GREG_BASE, | |
103 | TSI108_GREG_FEATURE_0, | |
104 | TSI108_GREG_GLOBAL_CONF_0, | |
105 | TSI108_GREG_VENDOR_ID, | |
106 | TSI108_GREG_IPI_VECTOR_PRI_0, | |
107 | TSI108_GREG_IPI_STRIDE, | |
108 | TSI108_GREG_SPURIOUS, | |
109 | TSI108_GREG_TIMER_FREQ, | |
110 | ||
111 | TSI108_TIMER_BASE, | |
112 | TSI108_TIMER_STRIDE, | |
113 | TSI108_TIMER_CURRENT_CNT, | |
114 | TSI108_TIMER_BASE_CNT, | |
115 | TSI108_TIMER_VECTOR_PRI, | |
116 | TSI108_TIMER_DESTINATION, | |
117 | ||
118 | TSI108_CPU_BASE, | |
119 | TSI108_CPU_STRIDE, | |
120 | TSI108_CPU_IPI_DISPATCH_0, | |
121 | TSI108_CPU_IPI_DISPATCH_STRIDE, | |
122 | TSI108_CPU_CURRENT_TASK_PRI, | |
123 | TSI108_CPU_WHOAMI, | |
124 | TSI108_CPU_INTACK, | |
125 | TSI108_CPU_EOI, | |
f365355e | 126 | TSI108_CPU_MCACK, |
7233593b ZR |
127 | |
128 | TSI108_IRQ_BASE, | |
129 | TSI108_IRQ_STRIDE, | |
130 | TSI108_IRQ_VECTOR_PRI, | |
131 | TSI108_VECPRI_VECTOR_MASK, | |
132 | TSI108_VECPRI_POLARITY_POSITIVE, | |
133 | TSI108_VECPRI_POLARITY_NEGATIVE, | |
134 | TSI108_VECPRI_SENSE_LEVEL, | |
135 | TSI108_VECPRI_SENSE_EDGE, | |
136 | TSI108_VECPRI_POLARITY_MASK, | |
137 | TSI108_VECPRI_SENSE_MASK, | |
138 | TSI108_IRQ_DESTINATION | |
139 | }, | |
140 | }; | |
141 | ||
142 | #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name] | |
143 | ||
144 | #else /* CONFIG_MPIC_WEIRD */ | |
145 | ||
146 | #define MPIC_INFO(name) MPIC_##name | |
147 | ||
148 | #endif /* CONFIG_MPIC_WEIRD */ | |
149 | ||
14cf11af PM |
150 | /* |
151 | * Register accessor functions | |
152 | */ | |
153 | ||
154 | ||
fbf0274e BH |
155 | static inline u32 _mpic_read(enum mpic_reg_type type, |
156 | struct mpic_reg_bank *rb, | |
157 | unsigned int reg) | |
14cf11af | 158 | { |
fbf0274e BH |
159 | switch(type) { |
160 | #ifdef CONFIG_PPC_DCR | |
161 | case mpic_access_dcr: | |
83f34df4 | 162 | return dcr_read(rb->dhost, reg); |
fbf0274e BH |
163 | #endif |
164 | case mpic_access_mmio_be: | |
165 | return in_be32(rb->base + (reg >> 2)); | |
166 | case mpic_access_mmio_le: | |
167 | default: | |
168 | return in_le32(rb->base + (reg >> 2)); | |
169 | } | |
14cf11af PM |
170 | } |
171 | ||
fbf0274e BH |
172 | static inline void _mpic_write(enum mpic_reg_type type, |
173 | struct mpic_reg_bank *rb, | |
174 | unsigned int reg, u32 value) | |
14cf11af | 175 | { |
fbf0274e BH |
176 | switch(type) { |
177 | #ifdef CONFIG_PPC_DCR | |
178 | case mpic_access_dcr: | |
d9d1063d JB |
179 | dcr_write(rb->dhost, reg, value); |
180 | break; | |
fbf0274e BH |
181 | #endif |
182 | case mpic_access_mmio_be: | |
d9d1063d JB |
183 | out_be32(rb->base + (reg >> 2), value); |
184 | break; | |
fbf0274e BH |
185 | case mpic_access_mmio_le: |
186 | default: | |
d9d1063d JB |
187 | out_le32(rb->base + (reg >> 2), value); |
188 | break; | |
fbf0274e | 189 | } |
14cf11af PM |
190 | } |
191 | ||
192 | static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi) | |
193 | { | |
fbf0274e | 194 | enum mpic_reg_type type = mpic->reg_type; |
7233593b ZR |
195 | unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) + |
196 | (ipi * MPIC_INFO(GREG_IPI_STRIDE)); | |
14cf11af | 197 | |
fbf0274e BH |
198 | if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le) |
199 | type = mpic_access_mmio_be; | |
200 | return _mpic_read(type, &mpic->gregs, offset); | |
14cf11af PM |
201 | } |
202 | ||
203 | static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value) | |
204 | { | |
7233593b ZR |
205 | unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) + |
206 | (ipi * MPIC_INFO(GREG_IPI_STRIDE)); | |
14cf11af | 207 | |
fbf0274e | 208 | _mpic_write(mpic->reg_type, &mpic->gregs, offset, value); |
14cf11af PM |
209 | } |
210 | ||
211 | static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg) | |
212 | { | |
213 | unsigned int cpu = 0; | |
214 | ||
215 | if (mpic->flags & MPIC_PRIMARY) | |
216 | cpu = hard_smp_processor_id(); | |
fbf0274e | 217 | return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg); |
14cf11af PM |
218 | } |
219 | ||
220 | static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value) | |
221 | { | |
222 | unsigned int cpu = 0; | |
223 | ||
224 | if (mpic->flags & MPIC_PRIMARY) | |
225 | cpu = hard_smp_processor_id(); | |
226 | ||
fbf0274e | 227 | _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value); |
14cf11af PM |
228 | } |
229 | ||
230 | static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg) | |
231 | { | |
232 | unsigned int isu = src_no >> mpic->isu_shift; | |
233 | unsigned int idx = src_no & mpic->isu_mask; | |
11a6b292 | 234 | unsigned int val; |
14cf11af | 235 | |
11a6b292 ME |
236 | val = _mpic_read(mpic->reg_type, &mpic->isus[isu], |
237 | reg + (idx * MPIC_INFO(IRQ_STRIDE))); | |
0d72ba93 OJ |
238 | #ifdef CONFIG_MPIC_BROKEN_REGREAD |
239 | if (reg == 0) | |
11a6b292 ME |
240 | val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) | |
241 | mpic->isu_reg0_shadow[src_no]; | |
0d72ba93 | 242 | #endif |
11a6b292 | 243 | return val; |
14cf11af PM |
244 | } |
245 | ||
246 | static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no, | |
247 | unsigned int reg, u32 value) | |
248 | { | |
249 | unsigned int isu = src_no >> mpic->isu_shift; | |
250 | unsigned int idx = src_no & mpic->isu_mask; | |
251 | ||
fbf0274e | 252 | _mpic_write(mpic->reg_type, &mpic->isus[isu], |
7233593b | 253 | reg + (idx * MPIC_INFO(IRQ_STRIDE)), value); |
0d72ba93 OJ |
254 | |
255 | #ifdef CONFIG_MPIC_BROKEN_REGREAD | |
256 | if (reg == 0) | |
11a6b292 ME |
257 | mpic->isu_reg0_shadow[src_no] = |
258 | value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY); | |
0d72ba93 | 259 | #endif |
14cf11af PM |
260 | } |
261 | ||
fbf0274e BH |
262 | #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r)) |
263 | #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v)) | |
14cf11af PM |
264 | #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i)) |
265 | #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v)) | |
266 | #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i)) | |
267 | #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v)) | |
268 | #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r)) | |
269 | #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v)) | |
270 | ||
271 | ||
272 | /* | |
273 | * Low level utility functions | |
274 | */ | |
275 | ||
276 | ||
c51a3fdc | 277 | static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr, |
fbf0274e BH |
278 | struct mpic_reg_bank *rb, unsigned int offset, |
279 | unsigned int size) | |
280 | { | |
281 | rb->base = ioremap(phys_addr + offset, size); | |
282 | BUG_ON(rb->base == NULL); | |
283 | } | |
284 | ||
285 | #ifdef CONFIG_PPC_DCR | |
5a2642f6 BH |
286 | static void _mpic_map_dcr(struct mpic *mpic, struct device_node *node, |
287 | struct mpic_reg_bank *rb, | |
fbf0274e BH |
288 | unsigned int offset, unsigned int size) |
289 | { | |
0411a5e2 ME |
290 | const u32 *dbasep; |
291 | ||
5a2642f6 | 292 | dbasep = of_get_property(node, "dcr-reg", NULL); |
0411a5e2 | 293 | |
5a2642f6 | 294 | rb->dhost = dcr_map(node, *dbasep + offset, size); |
fbf0274e BH |
295 | BUG_ON(!DCR_MAP_OK(rb->dhost)); |
296 | } | |
297 | ||
5a2642f6 BH |
298 | static inline void mpic_map(struct mpic *mpic, struct device_node *node, |
299 | phys_addr_t phys_addr, struct mpic_reg_bank *rb, | |
300 | unsigned int offset, unsigned int size) | |
fbf0274e BH |
301 | { |
302 | if (mpic->flags & MPIC_USES_DCR) | |
5a2642f6 | 303 | _mpic_map_dcr(mpic, node, rb, offset, size); |
fbf0274e BH |
304 | else |
305 | _mpic_map_mmio(mpic, phys_addr, rb, offset, size); | |
306 | } | |
307 | #else /* CONFIG_PPC_DCR */ | |
5a2642f6 | 308 | #define mpic_map(m,n,p,b,o,s) _mpic_map_mmio(m,p,b,o,s) |
fbf0274e BH |
309 | #endif /* !CONFIG_PPC_DCR */ |
310 | ||
311 | ||
14cf11af PM |
312 | |
313 | /* Check if we have one of those nice broken MPICs with a flipped endian on | |
314 | * reads from IPI registers | |
315 | */ | |
316 | static void __init mpic_test_broken_ipi(struct mpic *mpic) | |
317 | { | |
318 | u32 r; | |
319 | ||
7233593b ZR |
320 | mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK); |
321 | r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0)); | |
14cf11af PM |
322 | |
323 | if (r == le32_to_cpu(MPIC_VECPRI_MASK)) { | |
324 | printk(KERN_INFO "mpic: Detected reversed IPI registers\n"); | |
325 | mpic->flags |= MPIC_BROKEN_IPI; | |
326 | } | |
327 | } | |
328 | ||
6cfef5b2 | 329 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
14cf11af PM |
330 | |
331 | /* Test if an interrupt is sourced from HyperTransport (used on broken U3s) | |
332 | * to force the edge setting on the MPIC and do the ack workaround. | |
333 | */ | |
1beb6a7d | 334 | static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) |
14cf11af | 335 | { |
1beb6a7d | 336 | if (source >= 128 || !mpic->fixups) |
14cf11af | 337 | return 0; |
1beb6a7d | 338 | return mpic->fixups[source].base != NULL; |
14cf11af PM |
339 | } |
340 | ||
c4b22f26 | 341 | |
1beb6a7d | 342 | static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source) |
14cf11af | 343 | { |
1beb6a7d | 344 | struct mpic_irq_fixup *fixup = &mpic->fixups[source]; |
14cf11af | 345 | |
1beb6a7d BH |
346 | if (fixup->applebase) { |
347 | unsigned int soff = (fixup->index >> 3) & ~3; | |
348 | unsigned int mask = 1U << (fixup->index & 0x1f); | |
349 | writel(mask, fixup->applebase + soff); | |
350 | } else { | |
203041ad | 351 | raw_spin_lock(&mpic->fixup_lock); |
1beb6a7d BH |
352 | writeb(0x11 + 2 * fixup->index, fixup->base + 2); |
353 | writel(fixup->data, fixup->base + 4); | |
203041ad | 354 | raw_spin_unlock(&mpic->fixup_lock); |
1beb6a7d | 355 | } |
14cf11af PM |
356 | } |
357 | ||
1beb6a7d BH |
358 | static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source, |
359 | unsigned int irqflags) | |
360 | { | |
361 | struct mpic_irq_fixup *fixup = &mpic->fixups[source]; | |
362 | unsigned long flags; | |
363 | u32 tmp; | |
364 | ||
365 | if (fixup->base == NULL) | |
366 | return; | |
367 | ||
06fe98e6 | 368 | DBG("startup_ht_interrupt(0x%x, 0x%x) index: %d\n", |
1beb6a7d | 369 | source, irqflags, fixup->index); |
203041ad | 370 | raw_spin_lock_irqsave(&mpic->fixup_lock, flags); |
1beb6a7d BH |
371 | /* Enable and configure */ |
372 | writeb(0x10 + 2 * fixup->index, fixup->base + 2); | |
373 | tmp = readl(fixup->base + 4); | |
374 | tmp &= ~(0x23U); | |
375 | if (irqflags & IRQ_LEVEL) | |
376 | tmp |= 0x22; | |
377 | writel(tmp, fixup->base + 4); | |
203041ad | 378 | raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags); |
3669e930 JB |
379 | |
380 | #ifdef CONFIG_PM | |
381 | /* use the lowest bit inverted to the actual HW, | |
382 | * set if this fixup was enabled, clear otherwise */ | |
383 | mpic->save_data[source].fixup_data = tmp | 1; | |
384 | #endif | |
1beb6a7d BH |
385 | } |
386 | ||
387 | static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source, | |
388 | unsigned int irqflags) | |
389 | { | |
390 | struct mpic_irq_fixup *fixup = &mpic->fixups[source]; | |
391 | unsigned long flags; | |
392 | u32 tmp; | |
393 | ||
394 | if (fixup->base == NULL) | |
395 | return; | |
396 | ||
06fe98e6 | 397 | DBG("shutdown_ht_interrupt(0x%x, 0x%x)\n", source, irqflags); |
1beb6a7d BH |
398 | |
399 | /* Disable */ | |
203041ad | 400 | raw_spin_lock_irqsave(&mpic->fixup_lock, flags); |
1beb6a7d BH |
401 | writeb(0x10 + 2 * fixup->index, fixup->base + 2); |
402 | tmp = readl(fixup->base + 4); | |
72b13819 | 403 | tmp |= 1; |
1beb6a7d | 404 | writel(tmp, fixup->base + 4); |
203041ad | 405 | raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags); |
3669e930 JB |
406 | |
407 | #ifdef CONFIG_PM | |
408 | /* use the lowest bit inverted to the actual HW, | |
409 | * set if this fixup was enabled, clear otherwise */ | |
410 | mpic->save_data[source].fixup_data = tmp & ~1; | |
411 | #endif | |
1beb6a7d | 412 | } |
14cf11af | 413 | |
812fd1fd ME |
414 | #ifdef CONFIG_PCI_MSI |
415 | static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase, | |
416 | unsigned int devfn) | |
417 | { | |
418 | u8 __iomem *base; | |
419 | u8 pos, flags; | |
420 | u64 addr = 0; | |
421 | ||
422 | for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0; | |
423 | pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) { | |
424 | u8 id = readb(devbase + pos + PCI_CAP_LIST_ID); | |
425 | if (id == PCI_CAP_ID_HT) { | |
426 | id = readb(devbase + pos + 3); | |
427 | if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING) | |
428 | break; | |
429 | } | |
430 | } | |
431 | ||
432 | if (pos == 0) | |
433 | return; | |
434 | ||
435 | base = devbase + pos; | |
436 | ||
437 | flags = readb(base + HT_MSI_FLAGS); | |
438 | if (!(flags & HT_MSI_FLAGS_FIXED)) { | |
439 | addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK; | |
440 | addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32); | |
441 | } | |
442 | ||
fe333321 | 443 | printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%llx\n", |
812fd1fd ME |
444 | PCI_SLOT(devfn), PCI_FUNC(devfn), |
445 | flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr); | |
446 | ||
447 | if (!(flags & HT_MSI_FLAGS_ENABLE)) | |
448 | writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS); | |
449 | } | |
450 | #else | |
451 | static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase, | |
452 | unsigned int devfn) | |
453 | { | |
454 | return; | |
455 | } | |
456 | #endif | |
457 | ||
1beb6a7d BH |
458 | static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase, |
459 | unsigned int devfn, u32 vdid) | |
14cf11af | 460 | { |
c4b22f26 | 461 | int i, irq, n; |
1beb6a7d | 462 | u8 __iomem *base; |
14cf11af | 463 | u32 tmp; |
c4b22f26 | 464 | u8 pos; |
14cf11af | 465 | |
1beb6a7d BH |
466 | for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0; |
467 | pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) { | |
468 | u8 id = readb(devbase + pos + PCI_CAP_LIST_ID); | |
46ff3463 | 469 | if (id == PCI_CAP_ID_HT) { |
c4b22f26 | 470 | id = readb(devbase + pos + 3); |
beb7cc82 | 471 | if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ) |
c4b22f26 SB |
472 | break; |
473 | } | |
14cf11af | 474 | } |
c4b22f26 SB |
475 | if (pos == 0) |
476 | return; | |
477 | ||
1beb6a7d BH |
478 | base = devbase + pos; |
479 | writeb(0x01, base + 2); | |
480 | n = (readl(base + 4) >> 16) & 0xff; | |
14cf11af | 481 | |
1beb6a7d BH |
482 | printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x" |
483 | " has %d irqs\n", | |
484 | devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1); | |
c4b22f26 SB |
485 | |
486 | for (i = 0; i <= n; i++) { | |
1beb6a7d BH |
487 | writeb(0x10 + 2 * i, base + 2); |
488 | tmp = readl(base + 4); | |
14cf11af | 489 | irq = (tmp >> 16) & 0xff; |
1beb6a7d BH |
490 | DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp); |
491 | /* mask it , will be unmasked later */ | |
492 | tmp |= 0x1; | |
493 | writel(tmp, base + 4); | |
494 | mpic->fixups[irq].index = i; | |
495 | mpic->fixups[irq].base = base; | |
496 | /* Apple HT PIC has a non-standard way of doing EOIs */ | |
497 | if ((vdid & 0xffff) == 0x106b) | |
498 | mpic->fixups[irq].applebase = devbase + 0x60; | |
499 | else | |
500 | mpic->fixups[irq].applebase = NULL; | |
501 | writeb(0x11 + 2 * i, base + 2); | |
502 | mpic->fixups[irq].data = readl(base + 4) | 0x80000000; | |
14cf11af PM |
503 | } |
504 | } | |
505 | ||
c4b22f26 | 506 | |
1beb6a7d | 507 | static void __init mpic_scan_ht_pics(struct mpic *mpic) |
14cf11af PM |
508 | { |
509 | unsigned int devfn; | |
510 | u8 __iomem *cfgspace; | |
511 | ||
1beb6a7d | 512 | printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n"); |
14cf11af PM |
513 | |
514 | /* Allocate fixups array */ | |
ea96025a | 515 | mpic->fixups = kzalloc(128 * sizeof(*mpic->fixups), GFP_KERNEL); |
14cf11af | 516 | BUG_ON(mpic->fixups == NULL); |
14cf11af PM |
517 | |
518 | /* Init spinlock */ | |
203041ad | 519 | raw_spin_lock_init(&mpic->fixup_lock); |
14cf11af | 520 | |
c4b22f26 SB |
521 | /* Map U3 config space. We assume all IO-APICs are on the primary bus |
522 | * so we only need to map 64kB. | |
14cf11af | 523 | */ |
c4b22f26 | 524 | cfgspace = ioremap(0xf2000000, 0x10000); |
14cf11af PM |
525 | BUG_ON(cfgspace == NULL); |
526 | ||
1beb6a7d BH |
527 | /* Now we scan all slots. We do a very quick scan, we read the header |
528 | * type, vendor ID and device ID only, that's plenty enough | |
14cf11af | 529 | */ |
c4b22f26 | 530 | for (devfn = 0; devfn < 0x100; devfn++) { |
14cf11af PM |
531 | u8 __iomem *devbase = cfgspace + (devfn << 8); |
532 | u8 hdr_type = readb(devbase + PCI_HEADER_TYPE); | |
533 | u32 l = readl(devbase + PCI_VENDOR_ID); | |
1beb6a7d | 534 | u16 s; |
14cf11af PM |
535 | |
536 | DBG("devfn %x, l: %x\n", devfn, l); | |
537 | ||
538 | /* If no device, skip */ | |
539 | if (l == 0xffffffff || l == 0x00000000 || | |
540 | l == 0x0000ffff || l == 0xffff0000) | |
541 | goto next; | |
1beb6a7d BH |
542 | /* Check if is supports capability lists */ |
543 | s = readw(devbase + PCI_STATUS); | |
544 | if (!(s & PCI_STATUS_CAP_LIST)) | |
545 | goto next; | |
14cf11af | 546 | |
1beb6a7d | 547 | mpic_scan_ht_pic(mpic, devbase, devfn, l); |
812fd1fd | 548 | mpic_scan_ht_msi(mpic, devbase, devfn); |
c4b22f26 | 549 | |
14cf11af PM |
550 | next: |
551 | /* next device, if function 0 */ | |
c4b22f26 | 552 | if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0) |
14cf11af PM |
553 | devfn += 7; |
554 | } | |
555 | } | |
556 | ||
6cfef5b2 | 557 | #else /* CONFIG_MPIC_U3_HT_IRQS */ |
6e99e458 BH |
558 | |
559 | static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) | |
560 | { | |
561 | return 0; | |
562 | } | |
563 | ||
564 | static void __init mpic_scan_ht_pics(struct mpic *mpic) | |
565 | { | |
566 | } | |
567 | ||
6cfef5b2 | 568 | #endif /* CONFIG_MPIC_U3_HT_IRQS */ |
14cf11af | 569 | |
3c10c9c4 | 570 | #ifdef CONFIG_SMP |
2ef613cb | 571 | static int irq_choose_cpu(const struct cpumask *mask) |
3c10c9c4 | 572 | { |
3c10c9c4 KG |
573 | int cpuid; |
574 | ||
38e1313f | 575 | if (cpumask_equal(mask, cpu_all_mask)) { |
2ef613cb | 576 | static int irq_rover = 0; |
203041ad | 577 | static DEFINE_RAW_SPINLOCK(irq_rover_lock); |
3c10c9c4 KG |
578 | unsigned long flags; |
579 | ||
580 | /* Round-robin distribution... */ | |
581 | do_round_robin: | |
203041ad | 582 | raw_spin_lock_irqsave(&irq_rover_lock, flags); |
3c10c9c4 | 583 | |
2ef613cb BH |
584 | irq_rover = cpumask_next(irq_rover, cpu_online_mask); |
585 | if (irq_rover >= nr_cpu_ids) | |
586 | irq_rover = cpumask_first(cpu_online_mask); | |
587 | ||
3c10c9c4 | 588 | cpuid = irq_rover; |
3c10c9c4 | 589 | |
203041ad | 590 | raw_spin_unlock_irqrestore(&irq_rover_lock, flags); |
3c10c9c4 | 591 | } else { |
38e1313f YL |
592 | cpuid = cpumask_first_and(mask, cpu_online_mask); |
593 | if (cpuid >= nr_cpu_ids) | |
3c10c9c4 | 594 | goto do_round_robin; |
3c10c9c4 KG |
595 | } |
596 | ||
7a0d7940 | 597 | return get_hard_smp_processor_id(cpuid); |
3c10c9c4 KG |
598 | } |
599 | #else | |
2ef613cb | 600 | static int irq_choose_cpu(const struct cpumask *mask) |
3c10c9c4 KG |
601 | { |
602 | return hard_smp_processor_id(); | |
603 | } | |
604 | #endif | |
14cf11af | 605 | |
0ebfff14 BH |
606 | #define mpic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq) |
607 | ||
14cf11af | 608 | /* Find an mpic associated with a given linux interrupt */ |
d69a78d7 | 609 | static struct mpic *mpic_find(unsigned int irq) |
14cf11af | 610 | { |
0ebfff14 BH |
611 | if (irq < NUM_ISA_INTERRUPTS) |
612 | return NULL; | |
7df2457d | 613 | |
835c0553 | 614 | return get_irq_chip_data(irq); |
d69a78d7 | 615 | } |
7df2457d | 616 | |
d69a78d7 TB |
617 | /* Determine if the linux irq is an IPI */ |
618 | static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq) | |
619 | { | |
620 | unsigned int src = mpic_irq_to_hw(irq); | |
0ebfff14 | 621 | |
d69a78d7 | 622 | return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]); |
14cf11af PM |
623 | } |
624 | ||
d69a78d7 | 625 | |
14cf11af PM |
626 | /* Convert a cpu mask from logical to physical cpu numbers. */ |
627 | static inline u32 mpic_physmask(u32 cpumask) | |
628 | { | |
629 | int i; | |
630 | u32 mask = 0; | |
631 | ||
632 | for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1) | |
633 | mask |= (cpumask & 1) << get_hard_smp_processor_id(i); | |
634 | return mask; | |
635 | } | |
636 | ||
637 | #ifdef CONFIG_SMP | |
638 | /* Get the mpic structure from the IPI number */ | |
835c0553 | 639 | static inline struct mpic * mpic_from_ipi(struct irq_data *d) |
14cf11af | 640 | { |
835c0553 | 641 | return irq_data_get_irq_chip_data(d); |
14cf11af PM |
642 | } |
643 | #endif | |
644 | ||
645 | /* Get the mpic structure from the irq number */ | |
646 | static inline struct mpic * mpic_from_irq(unsigned int irq) | |
647 | { | |
835c0553 LB |
648 | return get_irq_chip_data(irq); |
649 | } | |
650 | ||
651 | /* Get the mpic structure from the irq data */ | |
652 | static inline struct mpic * mpic_from_irq_data(struct irq_data *d) | |
653 | { | |
654 | return irq_data_get_irq_chip_data(d); | |
14cf11af PM |
655 | } |
656 | ||
657 | /* Send an EOI */ | |
658 | static inline void mpic_eoi(struct mpic *mpic) | |
659 | { | |
7233593b ZR |
660 | mpic_cpu_write(MPIC_INFO(CPU_EOI), 0); |
661 | (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI)); | |
14cf11af PM |
662 | } |
663 | ||
14cf11af PM |
664 | /* |
665 | * Linux descriptor level callbacks | |
666 | */ | |
667 | ||
668 | ||
835c0553 | 669 | void mpic_unmask_irq(struct irq_data *d) |
14cf11af PM |
670 | { |
671 | unsigned int loops = 100000; | |
835c0553 LB |
672 | struct mpic *mpic = mpic_from_irq_data(d); |
673 | unsigned int src = mpic_irq_to_hw(d->irq); | |
14cf11af | 674 | |
835c0553 | 675 | DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src); |
14cf11af | 676 | |
7233593b ZR |
677 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), |
678 | mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & | |
e5356640 | 679 | ~MPIC_VECPRI_MASK); |
14cf11af PM |
680 | /* make sure mask gets to controller before we return to user */ |
681 | do { | |
682 | if (!loops--) { | |
8bfc5e36 SW |
683 | printk(KERN_ERR "%s: timeout on hwirq %u\n", |
684 | __func__, src); | |
14cf11af PM |
685 | break; |
686 | } | |
7233593b | 687 | } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK); |
14cf11af PM |
688 | } |
689 | ||
835c0553 | 690 | void mpic_mask_irq(struct irq_data *d) |
14cf11af PM |
691 | { |
692 | unsigned int loops = 100000; | |
835c0553 LB |
693 | struct mpic *mpic = mpic_from_irq_data(d); |
694 | unsigned int src = mpic_irq_to_hw(d->irq); | |
14cf11af | 695 | |
835c0553 | 696 | DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src); |
14cf11af | 697 | |
7233593b ZR |
698 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), |
699 | mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) | | |
e5356640 | 700 | MPIC_VECPRI_MASK); |
14cf11af PM |
701 | |
702 | /* make sure mask gets to controller before we return to user */ | |
703 | do { | |
704 | if (!loops--) { | |
8bfc5e36 SW |
705 | printk(KERN_ERR "%s: timeout on hwirq %u\n", |
706 | __func__, src); | |
14cf11af PM |
707 | break; |
708 | } | |
7233593b | 709 | } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK)); |
14cf11af PM |
710 | } |
711 | ||
835c0553 | 712 | void mpic_end_irq(struct irq_data *d) |
1beb6a7d | 713 | { |
835c0553 | 714 | struct mpic *mpic = mpic_from_irq_data(d); |
b9e5b4e6 BH |
715 | |
716 | #ifdef DEBUG_IRQ | |
835c0553 | 717 | DBG("%s: end_irq: %d\n", mpic->name, d->irq); |
b9e5b4e6 BH |
718 | #endif |
719 | /* We always EOI on end_irq() even for edge interrupts since that | |
720 | * should only lower the priority, the MPIC should have properly | |
721 | * latched another edge interrupt coming in anyway | |
722 | */ | |
723 | ||
724 | mpic_eoi(mpic); | |
725 | } | |
726 | ||
6cfef5b2 | 727 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
b9e5b4e6 | 728 | |
835c0553 | 729 | static void mpic_unmask_ht_irq(struct irq_data *d) |
b9e5b4e6 | 730 | { |
835c0553 LB |
731 | struct mpic *mpic = mpic_from_irq_data(d); |
732 | unsigned int src = mpic_irq_to_hw(d->irq); | |
1beb6a7d | 733 | |
835c0553 | 734 | mpic_unmask_irq(d); |
1beb6a7d | 735 | |
835c0553 | 736 | if (irq_to_desc(d->irq)->status & IRQ_LEVEL) |
b9e5b4e6 BH |
737 | mpic_ht_end_irq(mpic, src); |
738 | } | |
739 | ||
835c0553 | 740 | static unsigned int mpic_startup_ht_irq(struct irq_data *d) |
b9e5b4e6 | 741 | { |
835c0553 LB |
742 | struct mpic *mpic = mpic_from_irq_data(d); |
743 | unsigned int src = mpic_irq_to_hw(d->irq); | |
1beb6a7d | 744 | |
835c0553 LB |
745 | mpic_unmask_irq(d); |
746 | mpic_startup_ht_interrupt(mpic, src, irq_to_desc(d->irq)->status); | |
b9e5b4e6 BH |
747 | |
748 | return 0; | |
1beb6a7d BH |
749 | } |
750 | ||
835c0553 | 751 | static void mpic_shutdown_ht_irq(struct irq_data *d) |
b9e5b4e6 | 752 | { |
835c0553 LB |
753 | struct mpic *mpic = mpic_from_irq_data(d); |
754 | unsigned int src = mpic_irq_to_hw(d->irq); | |
b9e5b4e6 | 755 | |
835c0553 LB |
756 | mpic_shutdown_ht_interrupt(mpic, src, irq_to_desc(d->irq)->status); |
757 | mpic_mask_irq(d); | |
b9e5b4e6 BH |
758 | } |
759 | ||
835c0553 | 760 | static void mpic_end_ht_irq(struct irq_data *d) |
14cf11af | 761 | { |
835c0553 LB |
762 | struct mpic *mpic = mpic_from_irq_data(d); |
763 | unsigned int src = mpic_irq_to_hw(d->irq); | |
14cf11af | 764 | |
1beb6a7d | 765 | #ifdef DEBUG_IRQ |
835c0553 | 766 | DBG("%s: end_irq: %d\n", mpic->name, d->irq); |
1beb6a7d | 767 | #endif |
14cf11af PM |
768 | /* We always EOI on end_irq() even for edge interrupts since that |
769 | * should only lower the priority, the MPIC should have properly | |
770 | * latched another edge interrupt coming in anyway | |
771 | */ | |
772 | ||
835c0553 | 773 | if (irq_to_desc(d->irq)->status & IRQ_LEVEL) |
b9e5b4e6 | 774 | mpic_ht_end_irq(mpic, src); |
14cf11af PM |
775 | mpic_eoi(mpic); |
776 | } | |
6cfef5b2 | 777 | #endif /* !CONFIG_MPIC_U3_HT_IRQS */ |
b9e5b4e6 | 778 | |
14cf11af PM |
779 | #ifdef CONFIG_SMP |
780 | ||
835c0553 | 781 | static void mpic_unmask_ipi(struct irq_data *d) |
14cf11af | 782 | { |
835c0553 LB |
783 | struct mpic *mpic = mpic_from_ipi(d); |
784 | unsigned int src = mpic_irq_to_hw(d->irq) - mpic->ipi_vecs[0]; | |
14cf11af | 785 | |
835c0553 | 786 | DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src); |
14cf11af PM |
787 | mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK); |
788 | } | |
789 | ||
835c0553 | 790 | static void mpic_mask_ipi(struct irq_data *d) |
14cf11af PM |
791 | { |
792 | /* NEVER disable an IPI... that's just plain wrong! */ | |
793 | } | |
794 | ||
835c0553 | 795 | static void mpic_end_ipi(struct irq_data *d) |
14cf11af | 796 | { |
835c0553 | 797 | struct mpic *mpic = mpic_from_ipi(d); |
14cf11af PM |
798 | |
799 | /* | |
800 | * IPIs are marked IRQ_PER_CPU. This has the side effect of | |
801 | * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from | |
802 | * applying to them. We EOI them late to avoid re-entering. | |
6714465e | 803 | * We mark IPI's with IRQF_DISABLED as they must run with |
14cf11af PM |
804 | * irqs disabled. |
805 | */ | |
806 | mpic_eoi(mpic); | |
807 | } | |
808 | ||
809 | #endif /* CONFIG_SMP */ | |
810 | ||
835c0553 LB |
811 | int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask, |
812 | bool force) | |
14cf11af | 813 | { |
835c0553 LB |
814 | struct mpic *mpic = mpic_from_irq_data(d); |
815 | unsigned int src = mpic_irq_to_hw(d->irq); | |
14cf11af | 816 | |
3c10c9c4 | 817 | if (mpic->flags & MPIC_SINGLE_DEST_CPU) { |
38e1313f | 818 | int cpuid = irq_choose_cpu(cpumask); |
14cf11af | 819 | |
3c10c9c4 KG |
820 | mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid); |
821 | } else { | |
2ef613cb | 822 | cpumask_var_t tmp; |
14cf11af | 823 | |
2ef613cb BH |
824 | alloc_cpumask_var(&tmp, GFP_KERNEL); |
825 | ||
826 | cpumask_and(tmp, cpumask, cpu_online_mask); | |
3c10c9c4 KG |
827 | |
828 | mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), | |
2ef613cb BH |
829 | mpic_physmask(cpumask_bits(tmp)[0])); |
830 | ||
831 | free_cpumask_var(tmp); | |
3c10c9c4 | 832 | } |
d5dedd45 YL |
833 | |
834 | return 0; | |
14cf11af PM |
835 | } |
836 | ||
7233593b | 837 | static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type) |
0ebfff14 | 838 | { |
0ebfff14 | 839 | /* Now convert sense value */ |
6e99e458 | 840 | switch(type & IRQ_TYPE_SENSE_MASK) { |
0ebfff14 | 841 | case IRQ_TYPE_EDGE_RISING: |
7233593b ZR |
842 | return MPIC_INFO(VECPRI_SENSE_EDGE) | |
843 | MPIC_INFO(VECPRI_POLARITY_POSITIVE); | |
0ebfff14 | 844 | case IRQ_TYPE_EDGE_FALLING: |
6e99e458 | 845 | case IRQ_TYPE_EDGE_BOTH: |
7233593b ZR |
846 | return MPIC_INFO(VECPRI_SENSE_EDGE) | |
847 | MPIC_INFO(VECPRI_POLARITY_NEGATIVE); | |
0ebfff14 | 848 | case IRQ_TYPE_LEVEL_HIGH: |
7233593b ZR |
849 | return MPIC_INFO(VECPRI_SENSE_LEVEL) | |
850 | MPIC_INFO(VECPRI_POLARITY_POSITIVE); | |
0ebfff14 BH |
851 | case IRQ_TYPE_LEVEL_LOW: |
852 | default: | |
7233593b ZR |
853 | return MPIC_INFO(VECPRI_SENSE_LEVEL) | |
854 | MPIC_INFO(VECPRI_POLARITY_NEGATIVE); | |
0ebfff14 | 855 | } |
6e99e458 BH |
856 | } |
857 | ||
835c0553 | 858 | int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type) |
6e99e458 | 859 | { |
835c0553 LB |
860 | struct mpic *mpic = mpic_from_irq_data(d); |
861 | unsigned int src = mpic_irq_to_hw(d->irq); | |
862 | struct irq_desc *desc = irq_to_desc(d->irq); | |
6e99e458 BH |
863 | unsigned int vecpri, vold, vnew; |
864 | ||
06fe98e6 | 865 | DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n", |
835c0553 | 866 | mpic, d->irq, src, flow_type); |
6e99e458 BH |
867 | |
868 | if (src >= mpic->irq_count) | |
869 | return -EINVAL; | |
870 | ||
871 | if (flow_type == IRQ_TYPE_NONE) | |
872 | if (mpic->senses && src < mpic->senses_count) | |
873 | flow_type = mpic->senses[src]; | |
874 | if (flow_type == IRQ_TYPE_NONE) | |
875 | flow_type = IRQ_TYPE_LEVEL_LOW; | |
876 | ||
877 | desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); | |
878 | desc->status |= flow_type & IRQ_TYPE_SENSE_MASK; | |
879 | if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) | |
880 | desc->status |= IRQ_LEVEL; | |
881 | ||
882 | if (mpic_is_ht_interrupt(mpic, src)) | |
883 | vecpri = MPIC_VECPRI_POLARITY_POSITIVE | | |
884 | MPIC_VECPRI_SENSE_EDGE; | |
885 | else | |
7233593b | 886 | vecpri = mpic_type_to_vecpri(mpic, flow_type); |
6e99e458 | 887 | |
7233593b ZR |
888 | vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); |
889 | vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) | | |
890 | MPIC_INFO(VECPRI_SENSE_MASK)); | |
6e99e458 BH |
891 | vnew |= vecpri; |
892 | if (vold != vnew) | |
7233593b | 893 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew); |
6e99e458 BH |
894 | |
895 | return 0; | |
0ebfff14 BH |
896 | } |
897 | ||
38958dd9 OJ |
898 | void mpic_set_vector(unsigned int virq, unsigned int vector) |
899 | { | |
900 | struct mpic *mpic = mpic_from_irq(virq); | |
901 | unsigned int src = mpic_irq_to_hw(virq); | |
902 | unsigned int vecpri; | |
903 | ||
904 | DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n", | |
905 | mpic, virq, src, vector); | |
906 | ||
907 | if (src >= mpic->irq_count) | |
908 | return; | |
909 | ||
910 | vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); | |
911 | vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK); | |
912 | vecpri |= vector; | |
913 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); | |
914 | } | |
915 | ||
b9e5b4e6 | 916 | static struct irq_chip mpic_irq_chip = { |
835c0553 LB |
917 | .irq_mask = mpic_mask_irq, |
918 | .irq_unmask = mpic_unmask_irq, | |
919 | .irq_eoi = mpic_end_irq, | |
920 | .irq_set_type = mpic_set_irq_type, | |
b9e5b4e6 BH |
921 | }; |
922 | ||
923 | #ifdef CONFIG_SMP | |
924 | static struct irq_chip mpic_ipi_chip = { | |
835c0553 LB |
925 | .irq_mask = mpic_mask_ipi, |
926 | .irq_unmask = mpic_unmask_ipi, | |
927 | .irq_eoi = mpic_end_ipi, | |
b9e5b4e6 BH |
928 | }; |
929 | #endif /* CONFIG_SMP */ | |
930 | ||
6cfef5b2 | 931 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
b9e5b4e6 | 932 | static struct irq_chip mpic_irq_ht_chip = { |
835c0553 LB |
933 | .irq_startup = mpic_startup_ht_irq, |
934 | .irq_shutdown = mpic_shutdown_ht_irq, | |
935 | .irq_mask = mpic_mask_irq, | |
936 | .irq_unmask = mpic_unmask_ht_irq, | |
937 | .irq_eoi = mpic_end_ht_irq, | |
938 | .irq_set_type = mpic_set_irq_type, | |
b9e5b4e6 | 939 | }; |
6cfef5b2 | 940 | #endif /* CONFIG_MPIC_U3_HT_IRQS */ |
b9e5b4e6 | 941 | |
14cf11af | 942 | |
0ebfff14 BH |
943 | static int mpic_host_match(struct irq_host *h, struct device_node *node) |
944 | { | |
0ebfff14 | 945 | /* Exact match, unless mpic node is NULL */ |
52964f87 | 946 | return h->of_node == NULL || h->of_node == node; |
0ebfff14 BH |
947 | } |
948 | ||
949 | static int mpic_host_map(struct irq_host *h, unsigned int virq, | |
6e99e458 | 950 | irq_hw_number_t hw) |
0ebfff14 | 951 | { |
0ebfff14 | 952 | struct mpic *mpic = h->host_data; |
6e99e458 | 953 | struct irq_chip *chip; |
0ebfff14 | 954 | |
06fe98e6 | 955 | DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw); |
0ebfff14 | 956 | |
7df2457d | 957 | if (hw == mpic->spurious_vec) |
0ebfff14 | 958 | return -EINVAL; |
7fd72186 BH |
959 | if (mpic->protected && test_bit(hw, mpic->protected)) |
960 | return -EINVAL; | |
06fe98e6 | 961 | |
0ebfff14 | 962 | #ifdef CONFIG_SMP |
7df2457d | 963 | else if (hw >= mpic->ipi_vecs[0]) { |
0ebfff14 BH |
964 | WARN_ON(!(mpic->flags & MPIC_PRIMARY)); |
965 | ||
06fe98e6 | 966 | DBG("mpic: mapping as IPI\n"); |
0ebfff14 BH |
967 | set_irq_chip_data(virq, mpic); |
968 | set_irq_chip_and_handler(virq, &mpic->hc_ipi, | |
969 | handle_percpu_irq); | |
970 | return 0; | |
971 | } | |
972 | #endif /* CONFIG_SMP */ | |
973 | ||
974 | if (hw >= mpic->irq_count) | |
975 | return -EINVAL; | |
976 | ||
a7de7c74 ME |
977 | mpic_msi_reserve_hwirq(mpic, hw); |
978 | ||
6e99e458 | 979 | /* Default chip */ |
0ebfff14 BH |
980 | chip = &mpic->hc_irq; |
981 | ||
6cfef5b2 | 982 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
0ebfff14 | 983 | /* Check for HT interrupts, override vecpri */ |
6e99e458 | 984 | if (mpic_is_ht_interrupt(mpic, hw)) |
0ebfff14 | 985 | chip = &mpic->hc_ht_irq; |
6cfef5b2 | 986 | #endif /* CONFIG_MPIC_U3_HT_IRQS */ |
0ebfff14 | 987 | |
06fe98e6 | 988 | DBG("mpic: mapping to irq chip @%p\n", chip); |
0ebfff14 BH |
989 | |
990 | set_irq_chip_data(virq, mpic); | |
991 | set_irq_chip_and_handler(virq, chip, handle_fasteoi_irq); | |
6e99e458 BH |
992 | |
993 | /* Set default irq type */ | |
994 | set_irq_type(virq, IRQ_TYPE_NONE); | |
995 | ||
0ebfff14 BH |
996 | return 0; |
997 | } | |
998 | ||
999 | static int mpic_host_xlate(struct irq_host *h, struct device_node *ct, | |
40d50cf7 | 1000 | const u32 *intspec, unsigned int intsize, |
0ebfff14 BH |
1001 | irq_hw_number_t *out_hwirq, unsigned int *out_flags) |
1002 | ||
1003 | { | |
1004 | static unsigned char map_mpic_senses[4] = { | |
1005 | IRQ_TYPE_EDGE_RISING, | |
1006 | IRQ_TYPE_LEVEL_LOW, | |
1007 | IRQ_TYPE_LEVEL_HIGH, | |
1008 | IRQ_TYPE_EDGE_FALLING, | |
1009 | }; | |
1010 | ||
1011 | *out_hwirq = intspec[0]; | |
06fe98e6 BH |
1012 | if (intsize > 1) { |
1013 | u32 mask = 0x3; | |
1014 | ||
1015 | /* Apple invented a new race of encoding on machines with | |
1016 | * an HT APIC. They encode, among others, the index within | |
1017 | * the HT APIC. We don't care about it here since thankfully, | |
1018 | * it appears that they have the APIC already properly | |
1019 | * configured, and thus our current fixup code that reads the | |
1020 | * APIC config works fine. However, we still need to mask out | |
1021 | * bits in the specifier to make sure we only get bit 0 which | |
1022 | * is the level/edge bit (the only sense bit exposed by Apple), | |
1023 | * as their bit 1 means something else. | |
1024 | */ | |
1025 | if (machine_is(powermac)) | |
1026 | mask = 0x1; | |
1027 | *out_flags = map_mpic_senses[intspec[1] & mask]; | |
1028 | } else | |
0ebfff14 BH |
1029 | *out_flags = IRQ_TYPE_NONE; |
1030 | ||
06fe98e6 BH |
1031 | DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n", |
1032 | intsize, intspec[0], intspec[1], *out_hwirq, *out_flags); | |
1033 | ||
0ebfff14 BH |
1034 | return 0; |
1035 | } | |
1036 | ||
1037 | static struct irq_host_ops mpic_host_ops = { | |
1038 | .match = mpic_host_match, | |
1039 | .map = mpic_host_map, | |
1040 | .xlate = mpic_host_xlate, | |
1041 | }; | |
1042 | ||
14cf11af PM |
1043 | /* |
1044 | * Exported functions | |
1045 | */ | |
1046 | ||
0ebfff14 | 1047 | struct mpic * __init mpic_alloc(struct device_node *node, |
a959ff56 | 1048 | phys_addr_t phys_addr, |
14cf11af PM |
1049 | unsigned int flags, |
1050 | unsigned int isu_size, | |
14cf11af | 1051 | unsigned int irq_count, |
14cf11af PM |
1052 | const char *name) |
1053 | { | |
1054 | struct mpic *mpic; | |
d9d1063d | 1055 | u32 greg_feature; |
14cf11af PM |
1056 | const char *vers; |
1057 | int i; | |
7df2457d | 1058 | int intvec_top; |
a959ff56 | 1059 | u64 paddr = phys_addr; |
14cf11af | 1060 | |
85355bb2 | 1061 | mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL); |
14cf11af PM |
1062 | if (mpic == NULL) |
1063 | return NULL; | |
85355bb2 | 1064 | |
14cf11af PM |
1065 | mpic->name = name; |
1066 | ||
b9e5b4e6 | 1067 | mpic->hc_irq = mpic_irq_chip; |
b27df672 | 1068 | mpic->hc_irq.name = name; |
14cf11af | 1069 | if (flags & MPIC_PRIMARY) |
835c0553 | 1070 | mpic->hc_irq.irq_set_affinity = mpic_set_affinity; |
6cfef5b2 | 1071 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
b9e5b4e6 | 1072 | mpic->hc_ht_irq = mpic_irq_ht_chip; |
b27df672 | 1073 | mpic->hc_ht_irq.name = name; |
b9e5b4e6 | 1074 | if (flags & MPIC_PRIMARY) |
835c0553 | 1075 | mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity; |
6cfef5b2 | 1076 | #endif /* CONFIG_MPIC_U3_HT_IRQS */ |
fbf0274e | 1077 | |
14cf11af | 1078 | #ifdef CONFIG_SMP |
b9e5b4e6 | 1079 | mpic->hc_ipi = mpic_ipi_chip; |
b27df672 | 1080 | mpic->hc_ipi.name = name; |
14cf11af PM |
1081 | #endif /* CONFIG_SMP */ |
1082 | ||
1083 | mpic->flags = flags; | |
1084 | mpic->isu_size = isu_size; | |
14cf11af | 1085 | mpic->irq_count = irq_count; |
14cf11af | 1086 | mpic->num_sources = 0; /* so far */ |
14cf11af | 1087 | |
7df2457d OJ |
1088 | if (flags & MPIC_LARGE_VECTORS) |
1089 | intvec_top = 2047; | |
1090 | else | |
1091 | intvec_top = 255; | |
1092 | ||
1093 | mpic->timer_vecs[0] = intvec_top - 8; | |
1094 | mpic->timer_vecs[1] = intvec_top - 7; | |
1095 | mpic->timer_vecs[2] = intvec_top - 6; | |
1096 | mpic->timer_vecs[3] = intvec_top - 5; | |
1097 | mpic->ipi_vecs[0] = intvec_top - 4; | |
1098 | mpic->ipi_vecs[1] = intvec_top - 3; | |
1099 | mpic->ipi_vecs[2] = intvec_top - 2; | |
1100 | mpic->ipi_vecs[3] = intvec_top - 1; | |
1101 | mpic->spurious_vec = intvec_top; | |
1102 | ||
a959ff56 | 1103 | /* Check for "big-endian" in device-tree */ |
e2eb6392 | 1104 | if (node && of_get_property(node, "big-endian", NULL) != NULL) |
a959ff56 BH |
1105 | mpic->flags |= MPIC_BIG_ENDIAN; |
1106 | ||
7fd72186 BH |
1107 | /* Look for protected sources */ |
1108 | if (node) { | |
d9d1063d JB |
1109 | int psize; |
1110 | unsigned int bits, mapsize; | |
7fd72186 BH |
1111 | const u32 *psrc = |
1112 | of_get_property(node, "protected-sources", &psize); | |
1113 | if (psrc) { | |
1114 | psize /= 4; | |
1115 | bits = intvec_top + 1; | |
1116 | mapsize = BITS_TO_LONGS(bits) * sizeof(unsigned long); | |
ea96025a | 1117 | mpic->protected = kzalloc(mapsize, GFP_KERNEL); |
7fd72186 | 1118 | BUG_ON(mpic->protected == NULL); |
7fd72186 BH |
1119 | for (i = 0; i < psize; i++) { |
1120 | if (psrc[i] > intvec_top) | |
1121 | continue; | |
1122 | __set_bit(psrc[i], mpic->protected); | |
1123 | } | |
1124 | } | |
1125 | } | |
a959ff56 | 1126 | |
7233593b ZR |
1127 | #ifdef CONFIG_MPIC_WEIRD |
1128 | mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)]; | |
1129 | #endif | |
1130 | ||
fbf0274e BH |
1131 | /* default register type */ |
1132 | mpic->reg_type = (flags & MPIC_BIG_ENDIAN) ? | |
1133 | mpic_access_mmio_be : mpic_access_mmio_le; | |
1134 | ||
a959ff56 BH |
1135 | /* If no physical address is passed in, a device-node is mandatory */ |
1136 | BUG_ON(paddr == 0 && node == NULL); | |
1137 | ||
1138 | /* If no physical address passed in, check if it's dcr based */ | |
0411a5e2 | 1139 | if (paddr == 0 && of_get_property(node, "dcr-reg", NULL) != NULL) { |
fbf0274e | 1140 | #ifdef CONFIG_PPC_DCR |
0411a5e2 | 1141 | mpic->flags |= MPIC_USES_DCR; |
fbf0274e | 1142 | mpic->reg_type = mpic_access_dcr; |
fbf0274e | 1143 | #else |
0411a5e2 | 1144 | BUG(); |
fbf0274e | 1145 | #endif /* CONFIG_PPC_DCR */ |
0411a5e2 | 1146 | } |
fbf0274e | 1147 | |
a959ff56 BH |
1148 | /* If the MPIC is not DCR based, and no physical address was passed |
1149 | * in, try to obtain one | |
1150 | */ | |
1151 | if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) { | |
d9d1063d | 1152 | const u32 *reg = of_get_property(node, "reg", NULL); |
a959ff56 BH |
1153 | BUG_ON(reg == NULL); |
1154 | paddr = of_translate_address(node, reg); | |
1155 | BUG_ON(paddr == OF_BAD_ADDR); | |
1156 | } | |
1157 | ||
14cf11af | 1158 | /* Map the global registers */ |
5a2642f6 BH |
1159 | mpic_map(mpic, node, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000); |
1160 | mpic_map(mpic, node, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000); | |
14cf11af PM |
1161 | |
1162 | /* Reset */ | |
1163 | if (flags & MPIC_WANTS_RESET) { | |
7233593b ZR |
1164 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), |
1165 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) | |
14cf11af | 1166 | | MPIC_GREG_GCONF_RESET); |
7233593b | 1167 | while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) |
14cf11af PM |
1168 | & MPIC_GREG_GCONF_RESET) |
1169 | mb(); | |
1170 | } | |
1171 | ||
d91e4ea7 KG |
1172 | /* CoreInt */ |
1173 | if (flags & MPIC_ENABLE_COREINT) | |
1174 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), | |
1175 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) | |
1176 | | MPIC_GREG_GCONF_COREINT); | |
1177 | ||
f365355e OJ |
1178 | if (flags & MPIC_ENABLE_MCK) |
1179 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), | |
1180 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) | |
1181 | | MPIC_GREG_GCONF_MCK); | |
1182 | ||
14cf11af PM |
1183 | /* Read feature register, calculate num CPUs and, for non-ISU |
1184 | * MPICs, num sources as well. On ISU MPICs, sources are counted | |
1185 | * as ISUs are added | |
1186 | */ | |
d9d1063d JB |
1187 | greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0)); |
1188 | mpic->num_cpus = ((greg_feature & MPIC_GREG_FEATURE_LAST_CPU_MASK) | |
14cf11af | 1189 | >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1; |
5073e7ee | 1190 | if (isu_size == 0) { |
475ca391 KG |
1191 | if (flags & MPIC_BROKEN_FRR_NIRQS) |
1192 | mpic->num_sources = mpic->irq_count; | |
1193 | else | |
1194 | mpic->num_sources = | |
1195 | ((greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK) | |
1196 | >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1; | |
5073e7ee | 1197 | } |
14cf11af PM |
1198 | |
1199 | /* Map the per-CPU registers */ | |
1200 | for (i = 0; i < mpic->num_cpus; i++) { | |
5a2642f6 | 1201 | mpic_map(mpic, node, paddr, &mpic->cpuregs[i], |
fbf0274e BH |
1202 | MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE), |
1203 | 0x1000); | |
14cf11af PM |
1204 | } |
1205 | ||
1206 | /* Initialize main ISU if none provided */ | |
1207 | if (mpic->isu_size == 0) { | |
1208 | mpic->isu_size = mpic->num_sources; | |
5a2642f6 | 1209 | mpic_map(mpic, node, paddr, &mpic->isus[0], |
fbf0274e | 1210 | MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); |
14cf11af PM |
1211 | } |
1212 | mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1); | |
1213 | mpic->isu_mask = (1 << mpic->isu_shift) - 1; | |
1214 | ||
31207dab KG |
1215 | mpic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR, |
1216 | isu_size ? isu_size : mpic->num_sources, | |
1217 | &mpic_host_ops, | |
1218 | flags & MPIC_LARGE_VECTORS ? 2048 : 256); | |
1219 | if (mpic->irqhost == NULL) | |
1220 | return NULL; | |
1221 | ||
1222 | mpic->irqhost->host_data = mpic; | |
1223 | ||
14cf11af | 1224 | /* Display version */ |
d9d1063d | 1225 | switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) { |
14cf11af PM |
1226 | case 1: |
1227 | vers = "1.0"; | |
1228 | break; | |
1229 | case 2: | |
1230 | vers = "1.2"; | |
1231 | break; | |
1232 | case 3: | |
1233 | vers = "1.3"; | |
1234 | break; | |
1235 | default: | |
1236 | vers = "<unknown>"; | |
1237 | break; | |
1238 | } | |
a959ff56 BH |
1239 | printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx," |
1240 | " max %d CPUs\n", | |
1241 | name, vers, (unsigned long long)paddr, mpic->num_cpus); | |
1242 | printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n", | |
1243 | mpic->isu_size, mpic->isu_shift, mpic->isu_mask); | |
14cf11af PM |
1244 | |
1245 | mpic->next = mpics; | |
1246 | mpics = mpic; | |
1247 | ||
0ebfff14 | 1248 | if (flags & MPIC_PRIMARY) { |
14cf11af | 1249 | mpic_primary = mpic; |
0ebfff14 BH |
1250 | irq_set_default_host(mpic->irqhost); |
1251 | } | |
14cf11af PM |
1252 | |
1253 | return mpic; | |
1254 | } | |
1255 | ||
1256 | void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num, | |
a959ff56 | 1257 | phys_addr_t paddr) |
14cf11af PM |
1258 | { |
1259 | unsigned int isu_first = isu_num * mpic->isu_size; | |
1260 | ||
1261 | BUG_ON(isu_num >= MPIC_MAX_ISU); | |
1262 | ||
5a2642f6 BH |
1263 | mpic_map(mpic, mpic->irqhost->of_node, |
1264 | paddr, &mpic->isus[isu_num], 0, | |
fbf0274e | 1265 | MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); |
5a2642f6 | 1266 | |
14cf11af PM |
1267 | if ((isu_first + mpic->isu_size) > mpic->num_sources) |
1268 | mpic->num_sources = isu_first + mpic->isu_size; | |
1269 | } | |
1270 | ||
0ebfff14 BH |
1271 | void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count) |
1272 | { | |
1273 | mpic->senses = senses; | |
1274 | mpic->senses_count = count; | |
1275 | } | |
1276 | ||
14cf11af PM |
1277 | void __init mpic_init(struct mpic *mpic) |
1278 | { | |
1279 | int i; | |
cc353c30 | 1280 | int cpu; |
14cf11af PM |
1281 | |
1282 | BUG_ON(mpic->num_sources == 0); | |
1283 | ||
1284 | printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources); | |
1285 | ||
1286 | /* Set current processor priority to max */ | |
7233593b | 1287 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf); |
14cf11af PM |
1288 | |
1289 | /* Initialize timers: just disable them all */ | |
1290 | for (i = 0; i < 4; i++) { | |
1291 | mpic_write(mpic->tmregs, | |
7233593b ZR |
1292 | i * MPIC_INFO(TIMER_STRIDE) + |
1293 | MPIC_INFO(TIMER_DESTINATION), 0); | |
14cf11af | 1294 | mpic_write(mpic->tmregs, |
7233593b ZR |
1295 | i * MPIC_INFO(TIMER_STRIDE) + |
1296 | MPIC_INFO(TIMER_VECTOR_PRI), | |
14cf11af | 1297 | MPIC_VECPRI_MASK | |
7df2457d | 1298 | (mpic->timer_vecs[0] + i)); |
14cf11af PM |
1299 | } |
1300 | ||
1301 | /* Initialize IPIs to our reserved vectors and mark them disabled for now */ | |
1302 | mpic_test_broken_ipi(mpic); | |
1303 | for (i = 0; i < 4; i++) { | |
1304 | mpic_ipi_write(i, | |
1305 | MPIC_VECPRI_MASK | | |
1306 | (10 << MPIC_VECPRI_PRIORITY_SHIFT) | | |
7df2457d | 1307 | (mpic->ipi_vecs[0] + i)); |
14cf11af PM |
1308 | } |
1309 | ||
1310 | /* Initialize interrupt sources */ | |
1311 | if (mpic->irq_count == 0) | |
1312 | mpic->irq_count = mpic->num_sources; | |
1313 | ||
1beb6a7d | 1314 | /* Do the HT PIC fixups on U3 broken mpic */ |
14cf11af | 1315 | DBG("MPIC flags: %x\n", mpic->flags); |
05af7bd2 | 1316 | if ((mpic->flags & MPIC_U3_HT_IRQS) && (mpic->flags & MPIC_PRIMARY)) { |
3669e930 | 1317 | mpic_scan_ht_pics(mpic); |
05af7bd2 ME |
1318 | mpic_u3msi_init(mpic); |
1319 | } | |
14cf11af | 1320 | |
38958dd9 OJ |
1321 | mpic_pasemi_msi_init(mpic); |
1322 | ||
cc353c30 AB |
1323 | if (mpic->flags & MPIC_PRIMARY) |
1324 | cpu = hard_smp_processor_id(); | |
1325 | else | |
1326 | cpu = 0; | |
1327 | ||
14cf11af PM |
1328 | for (i = 0; i < mpic->num_sources; i++) { |
1329 | /* start with vector = source number, and masked */ | |
6e99e458 BH |
1330 | u32 vecpri = MPIC_VECPRI_MASK | i | |
1331 | (8 << MPIC_VECPRI_PRIORITY_SHIFT); | |
14cf11af | 1332 | |
7fd72186 BH |
1333 | /* check if protected */ |
1334 | if (mpic->protected && test_bit(i, mpic->protected)) | |
1335 | continue; | |
14cf11af | 1336 | /* init hw */ |
7233593b | 1337 | mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); |
cc353c30 | 1338 | mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu); |
14cf11af PM |
1339 | } |
1340 | ||
7df2457d OJ |
1341 | /* Init spurious vector */ |
1342 | mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec); | |
14cf11af | 1343 | |
7233593b ZR |
1344 | /* Disable 8259 passthrough, if supported */ |
1345 | if (!(mpic->flags & MPIC_NO_PTHROU_DIS)) | |
1346 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), | |
1347 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) | |
1348 | | MPIC_GREG_GCONF_8259_PTHROU_DIS); | |
14cf11af | 1349 | |
d87bf3be OJ |
1350 | if (mpic->flags & MPIC_NO_BIAS) |
1351 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), | |
1352 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) | |
1353 | | MPIC_GREG_GCONF_NO_BIAS); | |
1354 | ||
14cf11af | 1355 | /* Set current processor priority to 0 */ |
7233593b | 1356 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0); |
3669e930 JB |
1357 | |
1358 | #ifdef CONFIG_PM | |
1359 | /* allocate memory to save mpic state */ | |
ea96025a AV |
1360 | mpic->save_data = kmalloc(mpic->num_sources * sizeof(*mpic->save_data), |
1361 | GFP_KERNEL); | |
3669e930 JB |
1362 | BUG_ON(mpic->save_data == NULL); |
1363 | #endif | |
14cf11af PM |
1364 | } |
1365 | ||
868ea0c9 MG |
1366 | void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio) |
1367 | { | |
1368 | u32 v; | |
1369 | ||
1370 | v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1); | |
1371 | v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK; | |
1372 | v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio); | |
1373 | mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v); | |
1374 | } | |
14cf11af | 1375 | |
868ea0c9 MG |
1376 | void __init mpic_set_serial_int(struct mpic *mpic, int enable) |
1377 | { | |
ba1826e5 | 1378 | unsigned long flags; |
868ea0c9 MG |
1379 | u32 v; |
1380 | ||
203041ad | 1381 | raw_spin_lock_irqsave(&mpic_lock, flags); |
868ea0c9 MG |
1382 | v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1); |
1383 | if (enable) | |
1384 | v |= MPIC_GREG_GLOBAL_CONF_1_SIE; | |
1385 | else | |
1386 | v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE; | |
1387 | mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v); | |
203041ad | 1388 | raw_spin_unlock_irqrestore(&mpic_lock, flags); |
868ea0c9 | 1389 | } |
14cf11af PM |
1390 | |
1391 | void mpic_irq_set_priority(unsigned int irq, unsigned int pri) | |
1392 | { | |
d69a78d7 | 1393 | struct mpic *mpic = mpic_find(irq); |
0ebfff14 | 1394 | unsigned int src = mpic_irq_to_hw(irq); |
14cf11af PM |
1395 | unsigned long flags; |
1396 | u32 reg; | |
1397 | ||
06a901c5 SR |
1398 | if (!mpic) |
1399 | return; | |
1400 | ||
203041ad | 1401 | raw_spin_lock_irqsave(&mpic_lock, flags); |
d69a78d7 | 1402 | if (mpic_is_ipi(mpic, irq)) { |
7df2457d | 1403 | reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) & |
e5356640 | 1404 | ~MPIC_VECPRI_PRIORITY_MASK; |
7df2457d | 1405 | mpic_ipi_write(src - mpic->ipi_vecs[0], |
14cf11af PM |
1406 | reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); |
1407 | } else { | |
7233593b | 1408 | reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
e5356640 | 1409 | & ~MPIC_VECPRI_PRIORITY_MASK; |
7233593b | 1410 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), |
14cf11af PM |
1411 | reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); |
1412 | } | |
203041ad | 1413 | raw_spin_unlock_irqrestore(&mpic_lock, flags); |
14cf11af PM |
1414 | } |
1415 | ||
14cf11af PM |
1416 | void mpic_setup_this_cpu(void) |
1417 | { | |
1418 | #ifdef CONFIG_SMP | |
1419 | struct mpic *mpic = mpic_primary; | |
1420 | unsigned long flags; | |
1421 | u32 msk = 1 << hard_smp_processor_id(); | |
1422 | unsigned int i; | |
1423 | ||
1424 | BUG_ON(mpic == NULL); | |
1425 | ||
1426 | DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); | |
1427 | ||
203041ad | 1428 | raw_spin_lock_irqsave(&mpic_lock, flags); |
14cf11af PM |
1429 | |
1430 | /* let the mpic know we want intrs. default affinity is 0xffffffff | |
1431 | * until changed via /proc. That's how it's done on x86. If we want | |
1432 | * it differently, then we should make sure we also change the default | |
a53da52f | 1433 | * values of irq_desc[].affinity in irq.c. |
14cf11af PM |
1434 | */ |
1435 | if (distribute_irqs) { | |
1436 | for (i = 0; i < mpic->num_sources ; i++) | |
7233593b ZR |
1437 | mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), |
1438 | mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk); | |
14cf11af PM |
1439 | } |
1440 | ||
1441 | /* Set current processor priority to 0 */ | |
7233593b | 1442 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0); |
14cf11af | 1443 | |
203041ad | 1444 | raw_spin_unlock_irqrestore(&mpic_lock, flags); |
14cf11af PM |
1445 | #endif /* CONFIG_SMP */ |
1446 | } | |
1447 | ||
1448 | int mpic_cpu_get_priority(void) | |
1449 | { | |
1450 | struct mpic *mpic = mpic_primary; | |
1451 | ||
7233593b | 1452 | return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI)); |
14cf11af PM |
1453 | } |
1454 | ||
1455 | void mpic_cpu_set_priority(int prio) | |
1456 | { | |
1457 | struct mpic *mpic = mpic_primary; | |
1458 | ||
1459 | prio &= MPIC_CPU_TASKPRI_MASK; | |
7233593b | 1460 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio); |
14cf11af PM |
1461 | } |
1462 | ||
14cf11af PM |
1463 | void mpic_teardown_this_cpu(int secondary) |
1464 | { | |
1465 | struct mpic *mpic = mpic_primary; | |
1466 | unsigned long flags; | |
1467 | u32 msk = 1 << hard_smp_processor_id(); | |
1468 | unsigned int i; | |
1469 | ||
1470 | BUG_ON(mpic == NULL); | |
1471 | ||
1472 | DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); | |
203041ad | 1473 | raw_spin_lock_irqsave(&mpic_lock, flags); |
14cf11af PM |
1474 | |
1475 | /* let the mpic know we don't want intrs. */ | |
1476 | for (i = 0; i < mpic->num_sources ; i++) | |
7233593b ZR |
1477 | mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), |
1478 | mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk); | |
14cf11af PM |
1479 | |
1480 | /* Set current processor priority to max */ | |
7233593b | 1481 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf); |
7132799b VB |
1482 | /* We need to EOI the IPI since not all platforms reset the MPIC |
1483 | * on boot and new interrupts wouldn't get delivered otherwise. | |
1484 | */ | |
1485 | mpic_eoi(mpic); | |
14cf11af | 1486 | |
203041ad | 1487 | raw_spin_unlock_irqrestore(&mpic_lock, flags); |
14cf11af PM |
1488 | } |
1489 | ||
1490 | ||
f365355e | 1491 | static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg) |
14cf11af | 1492 | { |
0ebfff14 | 1493 | u32 src; |
14cf11af | 1494 | |
f365355e | 1495 | src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK); |
1beb6a7d | 1496 | #ifdef DEBUG_LOW |
f365355e | 1497 | DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src); |
1beb6a7d | 1498 | #endif |
5cddd2e3 JB |
1499 | if (unlikely(src == mpic->spurious_vec)) { |
1500 | if (mpic->flags & MPIC_SPV_EOI) | |
1501 | mpic_eoi(mpic); | |
0ebfff14 | 1502 | return NO_IRQ; |
5cddd2e3 | 1503 | } |
7fd72186 BH |
1504 | if (unlikely(mpic->protected && test_bit(src, mpic->protected))) { |
1505 | if (printk_ratelimit()) | |
1506 | printk(KERN_WARNING "%s: Got protected source %d !\n", | |
1507 | mpic->name, (int)src); | |
1508 | mpic_eoi(mpic); | |
1509 | return NO_IRQ; | |
1510 | } | |
1511 | ||
0ebfff14 | 1512 | return irq_linear_revmap(mpic->irqhost, src); |
14cf11af PM |
1513 | } |
1514 | ||
f365355e OJ |
1515 | unsigned int mpic_get_one_irq(struct mpic *mpic) |
1516 | { | |
1517 | return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK)); | |
1518 | } | |
1519 | ||
35a84c2f | 1520 | unsigned int mpic_get_irq(void) |
14cf11af PM |
1521 | { |
1522 | struct mpic *mpic = mpic_primary; | |
1523 | ||
1524 | BUG_ON(mpic == NULL); | |
1525 | ||
35a84c2f | 1526 | return mpic_get_one_irq(mpic); |
14cf11af PM |
1527 | } |
1528 | ||
d91e4ea7 KG |
1529 | unsigned int mpic_get_coreint_irq(void) |
1530 | { | |
1531 | #ifdef CONFIG_BOOKE | |
1532 | struct mpic *mpic = mpic_primary; | |
1533 | u32 src; | |
1534 | ||
1535 | BUG_ON(mpic == NULL); | |
1536 | ||
1537 | src = mfspr(SPRN_EPR); | |
1538 | ||
1539 | if (unlikely(src == mpic->spurious_vec)) { | |
1540 | if (mpic->flags & MPIC_SPV_EOI) | |
1541 | mpic_eoi(mpic); | |
1542 | return NO_IRQ; | |
1543 | } | |
1544 | if (unlikely(mpic->protected && test_bit(src, mpic->protected))) { | |
1545 | if (printk_ratelimit()) | |
1546 | printk(KERN_WARNING "%s: Got protected source %d !\n", | |
1547 | mpic->name, (int)src); | |
1548 | return NO_IRQ; | |
1549 | } | |
1550 | ||
1551 | return irq_linear_revmap(mpic->irqhost, src); | |
1552 | #else | |
1553 | return NO_IRQ; | |
1554 | #endif | |
1555 | } | |
1556 | ||
f365355e OJ |
1557 | unsigned int mpic_get_mcirq(void) |
1558 | { | |
1559 | struct mpic *mpic = mpic_primary; | |
1560 | ||
1561 | BUG_ON(mpic == NULL); | |
1562 | ||
1563 | return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK)); | |
1564 | } | |
14cf11af PM |
1565 | |
1566 | #ifdef CONFIG_SMP | |
1567 | void mpic_request_ipis(void) | |
1568 | { | |
1569 | struct mpic *mpic = mpic_primary; | |
78608dd3 | 1570 | int i; |
14cf11af | 1571 | BUG_ON(mpic == NULL); |
14cf11af | 1572 | |
8354be9c | 1573 | printk(KERN_INFO "mpic: requesting IPIs...\n"); |
0ebfff14 BH |
1574 | |
1575 | for (i = 0; i < 4; i++) { | |
1576 | unsigned int vipi = irq_create_mapping(mpic->irqhost, | |
7df2457d | 1577 | mpic->ipi_vecs[0] + i); |
0ebfff14 | 1578 | if (vipi == NO_IRQ) { |
78608dd3 MM |
1579 | printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]); |
1580 | continue; | |
d16f1b64 | 1581 | } |
78608dd3 | 1582 | smp_request_message_ipi(vipi, i); |
0ebfff14 | 1583 | } |
14cf11af | 1584 | } |
a9c59264 | 1585 | |
2ef613cb BH |
1586 | static void mpic_send_ipi(unsigned int ipi_no, const struct cpumask *cpu_mask) |
1587 | { | |
1588 | struct mpic *mpic = mpic_primary; | |
1589 | ||
1590 | BUG_ON(mpic == NULL); | |
1591 | ||
1592 | #ifdef DEBUG_IPI | |
1593 | DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no); | |
1594 | #endif | |
1595 | ||
1596 | mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) + | |
1597 | ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE), | |
1598 | mpic_physmask(cpumask_bits(cpu_mask)[0])); | |
1599 | } | |
1600 | ||
a9c59264 PM |
1601 | void smp_mpic_message_pass(int target, int msg) |
1602 | { | |
2ef613cb BH |
1603 | cpumask_var_t tmp; |
1604 | ||
a9c59264 PM |
1605 | /* make sure we're sending something that translates to an IPI */ |
1606 | if ((unsigned int)msg > 3) { | |
1607 | printk("SMP %d: smp_message_pass: unknown msg %d\n", | |
1608 | smp_processor_id(), msg); | |
1609 | return; | |
1610 | } | |
1611 | switch (target) { | |
1612 | case MSG_ALL: | |
2ef613cb | 1613 | mpic_send_ipi(msg, cpu_online_mask); |
a9c59264 PM |
1614 | break; |
1615 | case MSG_ALL_BUT_SELF: | |
2ef613cb BH |
1616 | alloc_cpumask_var(&tmp, GFP_NOWAIT); |
1617 | cpumask_andnot(tmp, cpu_online_mask, | |
1618 | cpumask_of(smp_processor_id())); | |
1619 | mpic_send_ipi(msg, tmp); | |
1620 | free_cpumask_var(tmp); | |
a9c59264 PM |
1621 | break; |
1622 | default: | |
2ef613cb | 1623 | mpic_send_ipi(msg, cpumask_of(target)); |
a9c59264 PM |
1624 | break; |
1625 | } | |
1626 | } | |
775aeff4 ME |
1627 | |
1628 | int __init smp_mpic_probe(void) | |
1629 | { | |
1630 | int nr_cpus; | |
1631 | ||
1632 | DBG("smp_mpic_probe()...\n"); | |
1633 | ||
2ef613cb | 1634 | nr_cpus = cpumask_weight(cpu_possible_mask); |
775aeff4 ME |
1635 | |
1636 | DBG("nr_cpus: %d\n", nr_cpus); | |
1637 | ||
1638 | if (nr_cpus > 1) | |
1639 | mpic_request_ipis(); | |
1640 | ||
1641 | return nr_cpus; | |
1642 | } | |
1643 | ||
1644 | void __devinit smp_mpic_setup_cpu(int cpu) | |
1645 | { | |
1646 | mpic_setup_this_cpu(); | |
1647 | } | |
66953ebe MM |
1648 | |
1649 | void mpic_reset_core(int cpu) | |
1650 | { | |
1651 | struct mpic *mpic = mpic_primary; | |
1652 | u32 pir; | |
1653 | int cpuid = get_hard_smp_processor_id(cpu); | |
1654 | ||
1655 | /* Set target bit for core reset */ | |
1656 | pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT)); | |
1657 | pir |= (1 << cpuid); | |
1658 | mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir); | |
1659 | mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT)); | |
1660 | ||
1661 | /* Restore target bit after reset complete */ | |
1662 | pir &= ~(1 << cpuid); | |
1663 | mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir); | |
1664 | mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT)); | |
1665 | } | |
14cf11af | 1666 | #endif /* CONFIG_SMP */ |
3669e930 JB |
1667 | |
1668 | #ifdef CONFIG_PM | |
1669 | static int mpic_suspend(struct sys_device *dev, pm_message_t state) | |
1670 | { | |
1671 | struct mpic *mpic = container_of(dev, struct mpic, sysdev); | |
1672 | int i; | |
1673 | ||
1674 | for (i = 0; i < mpic->num_sources; i++) { | |
1675 | mpic->save_data[i].vecprio = | |
1676 | mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI)); | |
1677 | mpic->save_data[i].dest = | |
1678 | mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)); | |
1679 | } | |
1680 | ||
1681 | return 0; | |
1682 | } | |
1683 | ||
1684 | static int mpic_resume(struct sys_device *dev) | |
1685 | { | |
1686 | struct mpic *mpic = container_of(dev, struct mpic, sysdev); | |
1687 | int i; | |
1688 | ||
1689 | for (i = 0; i < mpic->num_sources; i++) { | |
1690 | mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), | |
1691 | mpic->save_data[i].vecprio); | |
1692 | mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), | |
1693 | mpic->save_data[i].dest); | |
1694 | ||
1695 | #ifdef CONFIG_MPIC_U3_HT_IRQS | |
7c9d9360 | 1696 | if (mpic->fixups) { |
3669e930 JB |
1697 | struct mpic_irq_fixup *fixup = &mpic->fixups[i]; |
1698 | ||
1699 | if (fixup->base) { | |
1700 | /* we use the lowest bit in an inverted meaning */ | |
1701 | if ((mpic->save_data[i].fixup_data & 1) == 0) | |
1702 | continue; | |
1703 | ||
1704 | /* Enable and configure */ | |
1705 | writeb(0x10 + 2 * fixup->index, fixup->base + 2); | |
1706 | ||
1707 | writel(mpic->save_data[i].fixup_data & ~1, | |
1708 | fixup->base + 4); | |
1709 | } | |
1710 | } | |
1711 | #endif | |
1712 | } /* end for loop */ | |
1713 | ||
1714 | return 0; | |
1715 | } | |
1716 | #endif | |
1717 | ||
1718 | static struct sysdev_class mpic_sysclass = { | |
1719 | #ifdef CONFIG_PM | |
1720 | .resume = mpic_resume, | |
1721 | .suspend = mpic_suspend, | |
1722 | #endif | |
af5ca3f4 | 1723 | .name = "mpic", |
3669e930 JB |
1724 | }; |
1725 | ||
1726 | static int mpic_init_sys(void) | |
1727 | { | |
1728 | struct mpic *mpic = mpics; | |
1729 | int error, id = 0; | |
1730 | ||
1731 | error = sysdev_class_register(&mpic_sysclass); | |
1732 | ||
1733 | while (mpic && !error) { | |
1734 | mpic->sysdev.cls = &mpic_sysclass; | |
1735 | mpic->sysdev.id = id++; | |
1736 | error = sysdev_register(&mpic->sysdev); | |
1737 | mpic = mpic->next; | |
1738 | } | |
1739 | return error; | |
1740 | } | |
1741 | ||
1742 | device_initcall(mpic_init_sys); |