projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[PATCH] powerpc: Detect prefetchable windows in pci_process_bridge_OF_ranges
[deliverable/linux.git] / arch / powerpc / sysdev / mpic.c
CommitLineData
14cf11af
PM		 1/*
2 * arch/powerpc/kernel/mpic.c
3 *
4 * Driver for interrupt controllers following the OpenPIC standard, the
5 * common implementation beeing IBM's MPIC. This driver also can deal
6 * with various broken implementations of this HW.
7 *
8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file COPYING in the main directory of this archive
12 * for more details.
13 */
14
15#undef DEBUG
16
17#include <linux/config.h>
18#include <linux/types.h>
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/irq.h>
22#include <linux/smp.h>
23#include <linux/interrupt.h>
24#include <linux/bootmem.h>
25#include <linux/spinlock.h>
26#include <linux/pci.h>
27
28#include <asm/ptrace.h>
29#include <asm/signal.h>
30#include <asm/io.h>
31#include <asm/pgtable.h>
32#include <asm/irq.h>
33#include <asm/machdep.h>
34#include <asm/mpic.h>
35#include <asm/smp.h>
36
37#ifdef DEBUG
38#define DBG(fmt...) printk(fmt)
39#else
40#define DBG(fmt...)
41#endif
42
43static struct mpic *mpics;
44static struct mpic *mpic_primary;
45static DEFINE_SPINLOCK(mpic_lock);
46
c0c0d996 47#ifdef CONFIG_PPC32 /* XXX for now */
e40c7f02
AW		 48#ifdef CONFIG_IRQ_ALL_CPUS
49#define distribute_irqs (1)
50#else
51#define distribute_irqs (0)
52#endif
c0c0d996 53#endif
14cf11af
PM		 54
55/*
56 * Register accessor functions
57 */
58
59
60static inline u32 _mpic_read(unsigned int be, volatile u32 __iomem *base,
61 unsigned int reg)
62{
63 if (be)
64 return in_be32(base + (reg >> 2));
65 else
66 return in_le32(base + (reg >> 2));
67}
68
69static inline void _mpic_write(unsigned int be, volatile u32 __iomem *base,
70 unsigned int reg, u32 value)
71{
72 if (be)
73 out_be32(base + (reg >> 2), value);
74 else
75 out_le32(base + (reg >> 2), value);
76}
77
78static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
79{
80 unsigned int be = (mpic->flags & MPIC_BIG_ENDIAN) != 0;
81 unsigned int offset = MPIC_GREG_IPI_VECTOR_PRI_0 + (ipi * 0x10);
82
83 if (mpic->flags & MPIC_BROKEN_IPI)
84 be = !be;
85 return _mpic_read(be, mpic->gregs, offset);
86}
87
88static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
89{
90 unsigned int offset = MPIC_GREG_IPI_VECTOR_PRI_0 + (ipi * 0x10);
91
92 _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->gregs, offset, value);
93}
94
95static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
96{
97 unsigned int cpu = 0;
98
99 if (mpic->flags & MPIC_PRIMARY)
100 cpu = hard_smp_processor_id();
101
102 return _mpic_read(mpic->flags & MPIC_BIG_ENDIAN, mpic->cpuregs[cpu], reg);
103}
104
105static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
106{
107 unsigned int cpu = 0;
108
109 if (mpic->flags & MPIC_PRIMARY)
110 cpu = hard_smp_processor_id();
111
112 _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->cpuregs[cpu], reg, value);
113}
114
115static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
116{
117 unsigned int isu = src_no >> mpic->isu_shift;
118 unsigned int idx = src_no & mpic->isu_mask;
119
120 return _mpic_read(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu],
121 reg + (idx * MPIC_IRQ_STRIDE));
122}
123
124static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
125 unsigned int reg, u32 value)
126{
127 unsigned int isu = src_no >> mpic->isu_shift;
128 unsigned int idx = src_no & mpic->isu_mask;
129
130 _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu],
131 reg + (idx * MPIC_IRQ_STRIDE), value);
132}
133
134#define mpic_read(b,r) _mpic_read(mpic->flags & MPIC_BIG_ENDIAN,(b),(r))
135#define mpic_write(b,r,v) _mpic_write(mpic->flags & MPIC_BIG_ENDIAN,(b),(r),(v))
136#define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))
137#define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))
138#define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))
139#define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))
140#define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))
141#define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v))
142
143
144/*
145 * Low level utility functions
146 */
147
148
149
150/* Check if we have one of those nice broken MPICs with a flipped endian on
151 * reads from IPI registers
152 */
153static void __init mpic_test_broken_ipi(struct mpic *mpic)
154{
155 u32 r;
156
157 mpic_write(mpic->gregs, MPIC_GREG_IPI_VECTOR_PRI_0, MPIC_VECPRI_MASK);
158 r = mpic_read(mpic->gregs, MPIC_GREG_IPI_VECTOR_PRI_0);
159
160 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
161 printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
162 mpic->flags |= MPIC_BROKEN_IPI;
163 }
164}
165
166#ifdef CONFIG_MPIC_BROKEN_U3
167
168/* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
169 * to force the edge setting on the MPIC and do the ack workaround.
170 */
171static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source_no)
172{
173 if (source_no >= 128 || !mpic->fixups)
174 return 0;
175 return mpic->fixups[source_no].base != NULL;
176}
177
c4b22f26 178
14cf11af
PM		 179static inline void mpic_apic_end_irq(struct mpic *mpic, unsigned int source_no)
180{
181 struct mpic_irq_fixup *fixup = &mpic->fixups[source_no];
14cf11af
PM		 182
183 spin_lock(&mpic->fixup_lock);
c4b22f26
SB		 184 writeb(0x11 + 2 * fixup->irq, fixup->base + 2);
185 writel(fixup->data, fixup->base + 4);
14cf11af
PM		 186 spin_unlock(&mpic->fixup_lock);
187}
188
189
c4b22f26 190static void __init mpic_scan_ioapic(struct mpic *mpic, u8 __iomem *devbase)
14cf11af 191{
c4b22f26 192 int i, irq, n;
14cf11af 193 u32 tmp;
c4b22f26 194 u8 pos;
14cf11af 195
c4b22f26
SB		 196 for (pos = readb(devbase + 0x34); pos; pos = readb(devbase + pos + 1)) {
197 u8 id = readb(devbase + pos);
14cf11af 198
c4b22f26
SB		 199 if (id == 0x08) {
200 id = readb(devbase + pos + 3);
201 if (id == 0x80)
202 break;
203 }
14cf11af 204 }
c4b22f26
SB		 205 if (pos == 0)
206 return;
207
208 printk(KERN_INFO "mpic: - Workarounds @ %p, pos = 0x%02x\n", devbase, pos);
14cf11af 209
c4b22f26 210 devbase += pos;
14cf11af 211
c4b22f26
SB		 212 writeb(0x01, devbase + 2);
213 n = (readl(devbase + 4) >> 16) & 0xff;
214
215 for (i = 0; i <= n; i++) {
216 writeb(0x10 + 2 * i, devbase + 2);
217 tmp = readl(devbase + 4);
218 if ((tmp & 0x21) != 0x20)
14cf11af
PM		 219 continue;
220 irq = (tmp >> 16) & 0xff;
221 mpic->fixups[irq].irq = i;
c4b22f26
SB		 222 mpic->fixups[irq].base = devbase;
223 writeb(0x11 + 2 * i, devbase + 2);
224 mpic->fixups[irq].data = readl(devbase + 4) | 0x80000000;
14cf11af
PM		 225 }
226}
227
c4b22f26 228
14cf11af
PM		 229static void __init mpic_scan_ioapics(struct mpic *mpic)
230{
231 unsigned int devfn;
232 u8 __iomem *cfgspace;
233
234 printk(KERN_INFO "mpic: Setting up IO-APICs workarounds for U3\n");
235
236 /* Allocate fixups array */
237 mpic->fixups = alloc_bootmem(128 * sizeof(struct mpic_irq_fixup));
238 BUG_ON(mpic->fixups == NULL);
239 memset(mpic->fixups, 0, 128 * sizeof(struct mpic_irq_fixup));
240
241 /* Init spinlock */
242 spin_lock_init(&mpic->fixup_lock);
243
c4b22f26
SB		 244 /* Map U3 config space. We assume all IO-APICs are on the primary bus
245 * so we only need to map 64kB.
14cf11af 246 */
c4b22f26 247 cfgspace = ioremap(0xf2000000, 0x10000);
14cf11af
PM		 248 BUG_ON(cfgspace == NULL);
249
250 /* Now we scan all slots. We do a very quick scan, we read the header type,
251 * vendor ID and device ID only, that's plenty enough
252 */
c4b22f26 253 for (devfn = 0; devfn < 0x100; devfn++) {
14cf11af
PM		 254 u8 __iomem *devbase = cfgspace + (devfn << 8);
255 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
256 u32 l = readl(devbase + PCI_VENDOR_ID);
14cf11af
PM		 257
258 DBG("devfn %x, l: %x\n", devfn, l);
259
260 /* If no device, skip */
261 if (l == 0xffffffff || l == 0x00000000 ||
262 l == 0x0000ffff || l == 0xffff0000)
263 goto next;
264
c4b22f26
SB		 265 mpic_scan_ioapic(mpic, devbase);
266
14cf11af
PM		 267 next:
268 /* next device, if function 0 */
c4b22f26 269 if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
14cf11af
PM		 270 devfn += 7;
271 }
272}
273
274#endif /* CONFIG_MPIC_BROKEN_U3 */
275
276
277/* Find an mpic associated with a given linux interrupt */
278static struct mpic *mpic_find(unsigned int irq, unsigned int *is_ipi)
279{
280 struct mpic *mpic = mpics;
281
282 while(mpic) {
283 /* search IPIs first since they may override the main interrupts */
284 if (irq >= mpic->ipi_offset && irq < (mpic->ipi_offset + 4)) {
285 if (is_ipi)
286 *is_ipi = 1;
287 return mpic;
288 }
289 if (irq >= mpic->irq_offset &&
290 irq < (mpic->irq_offset + mpic->irq_count)) {
291 if (is_ipi)
292 *is_ipi = 0;
293 return mpic;
294 }
295 mpic = mpic -> next;
296 }
297 return NULL;
298}
299
300/* Convert a cpu mask from logical to physical cpu numbers. */
301static inline u32 mpic_physmask(u32 cpumask)
302{
303 int i;
304 u32 mask = 0;
305
306 for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1)
307 mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
308 return mask;
309}
310
311#ifdef CONFIG_SMP
312/* Get the mpic structure from the IPI number */
313static inline struct mpic * mpic_from_ipi(unsigned int ipi)
314{
315 return container_of(irq_desc[ipi].handler, struct mpic, hc_ipi);
316}
317#endif
318
319/* Get the mpic structure from the irq number */
320static inline struct mpic * mpic_from_irq(unsigned int irq)
321{
322 return container_of(irq_desc[irq].handler, struct mpic, hc_irq);
323}
324
325/* Send an EOI */
326static inline void mpic_eoi(struct mpic *mpic)
327{
328 mpic_cpu_write(MPIC_CPU_EOI, 0);
329 (void)mpic_cpu_read(MPIC_CPU_WHOAMI);
330}
331
332#ifdef CONFIG_SMP
333static irqreturn_t mpic_ipi_action(int irq, void *dev_id, struct pt_regs *regs)
334{
335 struct mpic *mpic = dev_id;
336
337 smp_message_recv(irq - mpic->ipi_offset, regs);
338 return IRQ_HANDLED;
339}
340#endif /* CONFIG_SMP */
341
342/*
343 * Linux descriptor level callbacks
344 */
345
346
347static void mpic_enable_irq(unsigned int irq)
348{
349 unsigned int loops = 100000;
350 struct mpic *mpic = mpic_from_irq(irq);
351 unsigned int src = irq - mpic->irq_offset;
352
bd561c79 353 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src);
14cf11af
PM		 354
355 mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI,
e5356640
BH		 356 mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) &
357 ~MPIC_VECPRI_MASK);
14cf11af
PM		 358
359 /* make sure mask gets to controller before we return to user */
360 do {
361 if (!loops--) {
362 printk(KERN_ERR "mpic_enable_irq timeout\n");
363 break;
364 }
365 } while(mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & MPIC_VECPRI_MASK);
366}
367
368static void mpic_disable_irq(unsigned int irq)
369{
370 unsigned int loops = 100000;
371 struct mpic *mpic = mpic_from_irq(irq);
372 unsigned int src = irq - mpic->irq_offset;
373
374 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src);
375
376 mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI,
e5356640
BH		 377 mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) |
378 MPIC_VECPRI_MASK);
14cf11af
PM		 379
380 /* make sure mask gets to controller before we return to user */
381 do {
382 if (!loops--) {
383 printk(KERN_ERR "mpic_enable_irq timeout\n");
384 break;
385 }
386 } while(!(mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & MPIC_VECPRI_MASK));
387}
388
389static void mpic_end_irq(unsigned int irq)
390{
391 struct mpic *mpic = mpic_from_irq(irq);
392
393 DBG("%s: end_irq: %d\n", mpic->name, irq);
394
395 /* We always EOI on end_irq() even for edge interrupts since that
396 * should only lower the priority, the MPIC should have properly
397 * latched another edge interrupt coming in anyway
398 */
399
400#ifdef CONFIG_MPIC_BROKEN_U3
401 if (mpic->flags & MPIC_BROKEN_U3) {
402 unsigned int src = irq - mpic->irq_offset;
403 if (mpic_is_ht_interrupt(mpic, src))
404 mpic_apic_end_irq(mpic, src);
405 }
406#endif /* CONFIG_MPIC_BROKEN_U3 */
407
408 mpic_eoi(mpic);
409}
410
411#ifdef CONFIG_SMP
412
413static void mpic_enable_ipi(unsigned int irq)
414{
415 struct mpic *mpic = mpic_from_ipi(irq);
416 unsigned int src = irq - mpic->ipi_offset;
417
418 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, irq, src);
419 mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
420}
421
422static void mpic_disable_ipi(unsigned int irq)
423{
424 /* NEVER disable an IPI... that's just plain wrong! */
425}
426
427static void mpic_end_ipi(unsigned int irq)
428{
429 struct mpic *mpic = mpic_from_ipi(irq);
430
431 /*
432 * IPIs are marked IRQ_PER_CPU. This has the side effect of
433 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
434 * applying to them. We EOI them late to avoid re-entering.
435 * We mark IPI's with SA_INTERRUPT as they must run with
436 * irqs disabled.
437 */
438 mpic_eoi(mpic);
439}
440
441#endif /* CONFIG_SMP */
442
443static void mpic_set_affinity(unsigned int irq, cpumask_t cpumask)
444{
445 struct mpic *mpic = mpic_from_irq(irq);
446
447 cpumask_t tmp;
448
449 cpus_and(tmp, cpumask, cpu_online_map);
450
451 mpic_irq_write(irq - mpic->irq_offset, MPIC_IRQ_DESTINATION,
452 mpic_physmask(cpus_addr(tmp)[0]));
453}
454
455
456/*
457 * Exported functions
458 */
459
460
461struct mpic * __init mpic_alloc(unsigned long phys_addr,
462 unsigned int flags,
463 unsigned int isu_size,
464 unsigned int irq_offset,
465 unsigned int irq_count,
466 unsigned int ipi_offset,
467 unsigned char *senses,
468 unsigned int senses_count,
469 const char *name)
470{
471 struct mpic *mpic;
472 u32 reg;
473 const char *vers;
474 int i;
475
476 mpic = alloc_bootmem(sizeof(struct mpic));
477 if (mpic == NULL)
478 return NULL;
479
480
481 memset(mpic, 0, sizeof(struct mpic));
482 mpic->name = name;
483
484 mpic->hc_irq.typename = name;
485 mpic->hc_irq.enable = mpic_enable_irq;
486 mpic->hc_irq.disable = mpic_disable_irq;
487 mpic->hc_irq.end = mpic_end_irq;
488 if (flags & MPIC_PRIMARY)
489 mpic->hc_irq.set_affinity = mpic_set_affinity;
490#ifdef CONFIG_SMP
491 mpic->hc_ipi.typename = name;
492 mpic->hc_ipi.enable = mpic_enable_ipi;
493 mpic->hc_ipi.disable = mpic_disable_ipi;
494 mpic->hc_ipi.end = mpic_end_ipi;
495#endif /* CONFIG_SMP */
496
497 mpic->flags = flags;
498 mpic->isu_size = isu_size;
499 mpic->irq_offset = irq_offset;
500 mpic->irq_count = irq_count;
501 mpic->ipi_offset = ipi_offset;
502 mpic->num_sources = 0; /* so far */
503 mpic->senses = senses;
504 mpic->senses_count = senses_count;
505
506 /* Map the global registers */
507 mpic->gregs = ioremap(phys_addr + MPIC_GREG_BASE, 0x1000);
bd561c79 508 mpic->tmregs = mpic->gregs + ((MPIC_TIMER_BASE - MPIC_GREG_BASE) >> 2);
14cf11af
PM		 509 BUG_ON(mpic->gregs == NULL);
510
511 /* Reset */
512 if (flags & MPIC_WANTS_RESET) {
513 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0,
514 mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0)
515 | MPIC_GREG_GCONF_RESET);
516 while( mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0)
517 & MPIC_GREG_GCONF_RESET)
518 mb();
519 }
520
521 /* Read feature register, calculate num CPUs and, for non-ISU
522 * MPICs, num sources as well. On ISU MPICs, sources are counted
523 * as ISUs are added
524 */
525 reg = mpic_read(mpic->gregs, MPIC_GREG_FEATURE_0);
526 mpic->num_cpus = ((reg & MPIC_GREG_FEATURE_LAST_CPU_MASK)
527 >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;
528 if (isu_size == 0)
529 mpic->num_sources = ((reg & MPIC_GREG_FEATURE_LAST_SRC_MASK)
530 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;
531
532 /* Map the per-CPU registers */
533 for (i = 0; i < mpic->num_cpus; i++) {
534 mpic->cpuregs[i] = ioremap(phys_addr + MPIC_CPU_BASE +
535 i * MPIC_CPU_STRIDE, 0x1000);
536 BUG_ON(mpic->cpuregs[i] == NULL);
537 }
538
539 /* Initialize main ISU if none provided */
540 if (mpic->isu_size == 0) {
541 mpic->isu_size = mpic->num_sources;
542 mpic->isus[0] = ioremap(phys_addr + MPIC_IRQ_BASE,
543 MPIC_IRQ_STRIDE * mpic->isu_size);
544 BUG_ON(mpic->isus[0] == NULL);
545 }
546 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
547 mpic->isu_mask = (1 << mpic->isu_shift) - 1;
548
549 /* Display version */
550 switch (reg & MPIC_GREG_FEATURE_VERSION_MASK) {
551 case 1:
552 vers = "1.0";
553 break;
554 case 2:
555 vers = "1.2";
556 break;
557 case 3:
558 vers = "1.3";
559 break;
560 default:
561 vers = "<unknown>";
562 break;
563 }
564 printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %lx, max %d CPUs\n",
565 name, vers, phys_addr, mpic->num_cpus);
566 printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n", mpic->isu_size,
567 mpic->isu_shift, mpic->isu_mask);
568
569 mpic->next = mpics;
570 mpics = mpic;
571
572 if (flags & MPIC_PRIMARY)
573 mpic_primary = mpic;
574
575 return mpic;
576}
577
578void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
579 unsigned long phys_addr)
580{
581 unsigned int isu_first = isu_num * mpic->isu_size;
582
583 BUG_ON(isu_num >= MPIC_MAX_ISU);
584
585 mpic->isus[isu_num] = ioremap(phys_addr, MPIC_IRQ_STRIDE * mpic->isu_size);
586 if ((isu_first + mpic->isu_size) > mpic->num_sources)
587 mpic->num_sources = isu_first + mpic->isu_size;
588}
589
590void __init mpic_setup_cascade(unsigned int irq, mpic_cascade_t handler,
591 void *data)
592{
593 struct mpic *mpic = mpic_find(irq, NULL);
594 unsigned long flags;
595
596 /* Synchronization here is a bit dodgy, so don't try to replace cascade
597 * interrupts on the fly too often ... but normally it's set up at boot.
598 */
599 spin_lock_irqsave(&mpic_lock, flags);
600 if (mpic->cascade)
601 mpic_disable_irq(mpic->cascade_vec + mpic->irq_offset);
602 mpic->cascade = NULL;
603 wmb();
604 mpic->cascade_vec = irq - mpic->irq_offset;
605 mpic->cascade_data = data;
606 wmb();
607 mpic->cascade = handler;
608 mpic_enable_irq(irq);
609 spin_unlock_irqrestore(&mpic_lock, flags);
610}
611
612void __init mpic_init(struct mpic *mpic)
613{
614 int i;
615
616 BUG_ON(mpic->num_sources == 0);
617
618 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
619
620 /* Set current processor priority to max */
621 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0xf);
622
623 /* Initialize timers: just disable them all */
624 for (i = 0; i < 4; i++) {
625 mpic_write(mpic->tmregs,
626 i * MPIC_TIMER_STRIDE + MPIC_TIMER_DESTINATION, 0);
627 mpic_write(mpic->tmregs,
628 i * MPIC_TIMER_STRIDE + MPIC_TIMER_VECTOR_PRI,
629 MPIC_VECPRI_MASK |
630 (MPIC_VEC_TIMER_0 + i));
631 }
632
633 /* Initialize IPIs to our reserved vectors and mark them disabled for now */
634 mpic_test_broken_ipi(mpic);
635 for (i = 0; i < 4; i++) {
636 mpic_ipi_write(i,
637 MPIC_VECPRI_MASK |
638 (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
639 (MPIC_VEC_IPI_0 + i));
640#ifdef CONFIG_SMP
641 if (!(mpic->flags & MPIC_PRIMARY))
642 continue;
643 irq_desc[mpic->ipi_offset+i].status |= IRQ_PER_CPU;
644 irq_desc[mpic->ipi_offset+i].handler = &mpic->hc_ipi;
14cf11af
PM		 645#endif /* CONFIG_SMP */
646 }
647
648 /* Initialize interrupt sources */
649 if (mpic->irq_count == 0)
650 mpic->irq_count = mpic->num_sources;
651
652#ifdef CONFIG_MPIC_BROKEN_U3
653 /* Do the ioapic fixups on U3 broken mpic */
654 DBG("MPIC flags: %x\n", mpic->flags);
655 if ((mpic->flags & MPIC_BROKEN_U3) && (mpic->flags & MPIC_PRIMARY))
656 mpic_scan_ioapics(mpic);
657#endif /* CONFIG_MPIC_BROKEN_U3 */
658
659 for (i = 0; i < mpic->num_sources; i++) {
660 /* start with vector = source number, and masked */
661 u32 vecpri = MPIC_VECPRI_MASK | i | (8 << MPIC_VECPRI_PRIORITY_SHIFT);
662 int level = 0;
663
664 /* if it's an IPI, we skip it */
665 if ((mpic->irq_offset + i) >= (mpic->ipi_offset + i) &&
666 (mpic->irq_offset + i) < (mpic->ipi_offset + i + 4))
667 continue;
668
669 /* do senses munging */
670 if (mpic->senses && i < mpic->senses_count) {
671 if (mpic->senses[i] & IRQ_SENSE_LEVEL)
672 vecpri |= MPIC_VECPRI_SENSE_LEVEL;
673 if (mpic->senses[i] & IRQ_POLARITY_POSITIVE)
674 vecpri |= MPIC_VECPRI_POLARITY_POSITIVE;
675 } else
676 vecpri |= MPIC_VECPRI_SENSE_LEVEL;
677
678 /* remember if it was a level interrupts */
679 level = (vecpri & MPIC_VECPRI_SENSE_LEVEL);
680
681 /* deal with broken U3 */
682 if (mpic->flags & MPIC_BROKEN_U3) {
683#ifdef CONFIG_MPIC_BROKEN_U3
684 if (mpic_is_ht_interrupt(mpic, i)) {
685 vecpri &= ~(MPIC_VECPRI_SENSE_MASK |
686 MPIC_VECPRI_POLARITY_MASK);
687 vecpri |= MPIC_VECPRI_POLARITY_POSITIVE;
688 }
689#else
690 printk(KERN_ERR "mpic: BROKEN_U3 set, but CONFIG doesn't match\n");
691#endif
692 }
693
694 DBG("setup source %d, vecpri: %08x, level: %d\n", i, vecpri,
695 (level != 0));
696
697 /* init hw */
698 mpic_irq_write(i, MPIC_IRQ_VECTOR_PRI, vecpri);
699 mpic_irq_write(i, MPIC_IRQ_DESTINATION,
700 1 << hard_smp_processor_id());
701
702 /* init linux descriptors */
703 if (i < mpic->irq_count) {
704 irq_desc[mpic->irq_offset+i].status = level ? IRQ_LEVEL : 0;
705 irq_desc[mpic->irq_offset+i].handler = &mpic->hc_irq;
706 }
707 }
708
709 /* Init spurrious vector */
710 mpic_write(mpic->gregs, MPIC_GREG_SPURIOUS, MPIC_VEC_SPURRIOUS);
711
712 /* Disable 8259 passthrough */
713 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0,
714 mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0)
715 | MPIC_GREG_GCONF_8259_PTHROU_DIS);
716
717 /* Set current processor priority to 0 */
718 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0);
719}
720
721
722
723void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
724{
725 int is_ipi;
726 struct mpic *mpic = mpic_find(irq, &is_ipi);
727 unsigned long flags;
728 u32 reg;
729
730 spin_lock_irqsave(&mpic_lock, flags);
731 if (is_ipi) {
e5356640
BH		 732 reg = mpic_ipi_read(irq - mpic->ipi_offset) &
733 ~MPIC_VECPRI_PRIORITY_MASK;
14cf11af
PM		 734 mpic_ipi_write(irq - mpic->ipi_offset,
735 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
736 } else {
e5356640
BH		 737 reg = mpic_irq_read(irq - mpic->irq_offset,MPIC_IRQ_VECTOR_PRI)
738 & ~MPIC_VECPRI_PRIORITY_MASK;
14cf11af
PM		 739 mpic_irq_write(irq - mpic->irq_offset, MPIC_IRQ_VECTOR_PRI,
740 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
741 }
742 spin_unlock_irqrestore(&mpic_lock, flags);
743}
744
745unsigned int mpic_irq_get_priority(unsigned int irq)
746{
747 int is_ipi;
748 struct mpic *mpic = mpic_find(irq, &is_ipi);
749 unsigned long flags;
750 u32 reg;
751
752 spin_lock_irqsave(&mpic_lock, flags);
753 if (is_ipi)
754 reg = mpic_ipi_read(irq - mpic->ipi_offset);
755 else
756 reg = mpic_irq_read(irq - mpic->irq_offset, MPIC_IRQ_VECTOR_PRI);
757 spin_unlock_irqrestore(&mpic_lock, flags);
758 return (reg & MPIC_VECPRI_PRIORITY_MASK) >> MPIC_VECPRI_PRIORITY_SHIFT;
759}
760
761void mpic_setup_this_cpu(void)
762{
763#ifdef CONFIG_SMP
764 struct mpic *mpic = mpic_primary;
765 unsigned long flags;
766 u32 msk = 1 << hard_smp_processor_id();
767 unsigned int i;
768
769 BUG_ON(mpic == NULL);
770
771 DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
772
773 spin_lock_irqsave(&mpic_lock, flags);
774
775 /* let the mpic know we want intrs. default affinity is 0xffffffff
776 * until changed via /proc. That's how it's done on x86. If we want
777 * it differently, then we should make sure we also change the default
778 * values of irq_affinity in irq.c.
779 */
780 if (distribute_irqs) {
781 for (i = 0; i < mpic->num_sources ; i++)
782 mpic_irq_write(i, MPIC_IRQ_DESTINATION,
783 mpic_irq_read(i, MPIC_IRQ_DESTINATION) | msk);
784 }
785
786 /* Set current processor priority to 0 */
787 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0);
788
789 spin_unlock_irqrestore(&mpic_lock, flags);
790#endif /* CONFIG_SMP */
791}
792
793int mpic_cpu_get_priority(void)
794{
795 struct mpic *mpic = mpic_primary;
796
797 return mpic_cpu_read(MPIC_CPU_CURRENT_TASK_PRI);
798}
799
800void mpic_cpu_set_priority(int prio)
801{
802 struct mpic *mpic = mpic_primary;
803
804 prio &= MPIC_CPU_TASKPRI_MASK;
805 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, prio);
806}
807
808/*
809 * XXX: someone who knows mpic should check this.
810 * do we need to eoi the ipi including for kexec cpu here (see xics comments)?
811 * or can we reset the mpic in the new kernel?
812 */
813void mpic_teardown_this_cpu(int secondary)
814{
815 struct mpic *mpic = mpic_primary;
816 unsigned long flags;
817 u32 msk = 1 << hard_smp_processor_id();
818 unsigned int i;
819
820 BUG_ON(mpic == NULL);
821
822 DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
823 spin_lock_irqsave(&mpic_lock, flags);
824
825 /* let the mpic know we don't want intrs. */
826 for (i = 0; i < mpic->num_sources ; i++)
827 mpic_irq_write(i, MPIC_IRQ_DESTINATION,
828 mpic_irq_read(i, MPIC_IRQ_DESTINATION) & ~msk);
829
830 /* Set current processor priority to max */
831 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0xf);
832
833 spin_unlock_irqrestore(&mpic_lock, flags);
834}
835
836
837void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask)
838{
839 struct mpic *mpic = mpic_primary;
840
841 BUG_ON(mpic == NULL);
842
843 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no);
844
845 mpic_cpu_write(MPIC_CPU_IPI_DISPATCH_0 + ipi_no * 0x10,
846 mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0]));
847}
848
849int mpic_get_one_irq(struct mpic *mpic, struct pt_regs *regs)
850{
851 u32 irq;
852
853 irq = mpic_cpu_read(MPIC_CPU_INTACK) & MPIC_VECPRI_VECTOR_MASK;
854 DBG("%s: get_one_irq(): %d\n", mpic->name, irq);
855
856 if (mpic->cascade && irq == mpic->cascade_vec) {
857 DBG("%s: cascading ...\n", mpic->name);
858 irq = mpic->cascade(regs, mpic->cascade_data);
859 mpic_eoi(mpic);
860 return irq;
861 }
862 if (unlikely(irq == MPIC_VEC_SPURRIOUS))
863 return -1;
864 if (irq < MPIC_VEC_IPI_0)
865 return irq + mpic->irq_offset;
866 DBG("%s: ipi %d !\n", mpic->name, irq - MPIC_VEC_IPI_0);
867 return irq - MPIC_VEC_IPI_0 + mpic->ipi_offset;
868}
869
870int mpic_get_irq(struct pt_regs *regs)
871{
872 struct mpic *mpic = mpic_primary;
873
874 BUG_ON(mpic == NULL);
875
876 return mpic_get_one_irq(mpic, regs);
877}
878
879
880#ifdef CONFIG_SMP
881void mpic_request_ipis(void)
882{
883 struct mpic *mpic = mpic_primary;
884
885 BUG_ON(mpic == NULL);
886
887 printk("requesting IPIs ... \n");
888
889 /* IPIs are marked SA_INTERRUPT as they must run with irqs disabled */
890 request_irq(mpic->ipi_offset+0, mpic_ipi_action, SA_INTERRUPT,
891 "IPI0 (call function)", mpic);
892 request_irq(mpic->ipi_offset+1, mpic_ipi_action, SA_INTERRUPT,
893 "IPI1 (reschedule)", mpic);
894 request_irq(mpic->ipi_offset+2, mpic_ipi_action, SA_INTERRUPT,
895 "IPI2 (unused)", mpic);
896 request_irq(mpic->ipi_offset+3, mpic_ipi_action, SA_INTERRUPT,
897 "IPI3 (debugger break)", mpic);
898
899 printk("IPIs requested... \n");
900}
a9c59264
PM		 901
902void smp_mpic_message_pass(int target, int msg)
903{
904 /* make sure we're sending something that translates to an IPI */
905 if ((unsigned int)msg > 3) {
906 printk("SMP %d: smp_message_pass: unknown msg %d\n",
907 smp_processor_id(), msg);
908 return;
909 }
910 switch (target) {
911 case MSG_ALL:
912 mpic_send_ipi(msg, 0xffffffff);
913 break;
914 case MSG_ALL_BUT_SELF:
915 mpic_send_ipi(msg, 0xffffffff & ~(1 << smp_processor_id()));
916 break;
917 default:
918 mpic_send_ipi(msg, 1 << target);
919 break;
920 }
921}
14cf11af 922#endif /* CONFIG_SMP */
Linux kernel - Deliverables
This page took 0.082438 seconds and 5 git commands to generate.