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36ca09be D |
1 | /* |
2 | * MPIC timer driver | |
3 | * | |
4 | * Copyright 2013 Freescale Semiconductor, Inc. | |
5 | * Author: Dongsheng Wang <Dongsheng.Wang@freescale.com> | |
6 | * Li Yang <leoli@freescale.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/errno.h> | |
18 | #include <linux/mm.h> | |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/slab.h> | |
21 | #include <linux/of.h> | |
26a2056e | 22 | #include <linux/of_address.h> |
36ca09be | 23 | #include <linux/of_device.h> |
26a2056e | 24 | #include <linux/of_irq.h> |
36ca09be D |
25 | #include <linux/syscore_ops.h> |
26 | #include <sysdev/fsl_soc.h> | |
27 | #include <asm/io.h> | |
28 | ||
29 | #include <asm/mpic_timer.h> | |
30 | ||
31 | #define FSL_GLOBAL_TIMER 0x1 | |
32 | ||
33 | /* Clock Ratio | |
34 | * Divide by 64 0x00000300 | |
35 | * Divide by 32 0x00000200 | |
36 | * Divide by 16 0x00000100 | |
37 | * Divide by 8 0x00000000 (Hardware default div) | |
38 | */ | |
39 | #define MPIC_TIMER_TCR_CLKDIV 0x00000300 | |
40 | ||
41 | #define MPIC_TIMER_TCR_ROVR_OFFSET 24 | |
42 | ||
43 | #define TIMER_STOP 0x80000000 | |
0fd79588 | 44 | #define GTCCR_TOG 0x80000000 |
36ca09be D |
45 | #define TIMERS_PER_GROUP 4 |
46 | #define MAX_TICKS (~0U >> 1) | |
47 | #define MAX_TICKS_CASCADE (~0U) | |
48 | #define TIMER_OFFSET(num) (1 << (TIMERS_PER_GROUP - 1 - num)) | |
49 | ||
50 | /* tv_usec should be less than ONE_SECOND, otherwise use tv_sec */ | |
51 | #define ONE_SECOND 1000000 | |
52 | ||
53 | struct timer_regs { | |
54 | u32 gtccr; | |
55 | u32 res0[3]; | |
56 | u32 gtbcr; | |
57 | u32 res1[3]; | |
58 | u32 gtvpr; | |
59 | u32 res2[3]; | |
60 | u32 gtdr; | |
61 | u32 res3[3]; | |
62 | }; | |
63 | ||
64 | struct cascade_priv { | |
65 | u32 tcr_value; /* TCR register: CASC & ROVR value */ | |
66 | unsigned int cascade_map; /* cascade map */ | |
67 | unsigned int timer_num; /* cascade control timer */ | |
68 | }; | |
69 | ||
70 | struct timer_group_priv { | |
71 | struct timer_regs __iomem *regs; | |
72 | struct mpic_timer timer[TIMERS_PER_GROUP]; | |
73 | struct list_head node; | |
74 | unsigned int timerfreq; | |
75 | unsigned int idle; | |
76 | unsigned int flags; | |
77 | spinlock_t lock; | |
78 | void __iomem *group_tcr; | |
79 | }; | |
80 | ||
81 | static struct cascade_priv cascade_timer[] = { | |
82 | /* cascade timer 0 and 1 */ | |
83 | {0x1, 0xc, 0x1}, | |
84 | /* cascade timer 1 and 2 */ | |
85 | {0x2, 0x6, 0x2}, | |
86 | /* cascade timer 2 and 3 */ | |
87 | {0x4, 0x3, 0x3} | |
88 | }; | |
89 | ||
90 | static LIST_HEAD(timer_group_list); | |
91 | ||
92 | static void convert_ticks_to_time(struct timer_group_priv *priv, | |
93 | const u64 ticks, struct timeval *time) | |
94 | { | |
95 | u64 tmp_sec; | |
96 | ||
97 | time->tv_sec = (__kernel_time_t)div_u64(ticks, priv->timerfreq); | |
98 | tmp_sec = (u64)time->tv_sec * (u64)priv->timerfreq; | |
99 | ||
100 | time->tv_usec = (__kernel_suseconds_t) | |
101 | div_u64((ticks - tmp_sec) * 1000000, priv->timerfreq); | |
102 | ||
103 | return; | |
104 | } | |
105 | ||
106 | /* the time set by the user is converted to "ticks" */ | |
107 | static int convert_time_to_ticks(struct timer_group_priv *priv, | |
108 | const struct timeval *time, u64 *ticks) | |
109 | { | |
110 | u64 max_value; /* prevent u64 overflow */ | |
111 | u64 tmp = 0; | |
112 | ||
113 | u64 tmp_sec; | |
114 | u64 tmp_ms; | |
115 | u64 tmp_us; | |
116 | ||
117 | max_value = div_u64(ULLONG_MAX, priv->timerfreq); | |
118 | ||
119 | if (time->tv_sec > max_value || | |
120 | (time->tv_sec == max_value && time->tv_usec > 0)) | |
121 | return -EINVAL; | |
122 | ||
123 | tmp_sec = (u64)time->tv_sec * (u64)priv->timerfreq; | |
124 | tmp += tmp_sec; | |
125 | ||
126 | tmp_ms = time->tv_usec / 1000; | |
127 | tmp_ms = div_u64((u64)tmp_ms * (u64)priv->timerfreq, 1000); | |
128 | tmp += tmp_ms; | |
129 | ||
130 | tmp_us = time->tv_usec % 1000; | |
131 | tmp_us = div_u64((u64)tmp_us * (u64)priv->timerfreq, 1000000); | |
132 | tmp += tmp_us; | |
133 | ||
134 | *ticks = tmp; | |
135 | ||
136 | return 0; | |
137 | } | |
138 | ||
139 | /* detect whether there is a cascade timer available */ | |
140 | static struct mpic_timer *detect_idle_cascade_timer( | |
141 | struct timer_group_priv *priv) | |
142 | { | |
143 | struct cascade_priv *casc_priv; | |
144 | unsigned int map; | |
145 | unsigned int array_size = ARRAY_SIZE(cascade_timer); | |
146 | unsigned int num; | |
147 | unsigned int i; | |
148 | unsigned long flags; | |
149 | ||
150 | casc_priv = cascade_timer; | |
151 | for (i = 0; i < array_size; i++) { | |
152 | spin_lock_irqsave(&priv->lock, flags); | |
153 | map = casc_priv->cascade_map & priv->idle; | |
154 | if (map == casc_priv->cascade_map) { | |
155 | num = casc_priv->timer_num; | |
156 | priv->timer[num].cascade_handle = casc_priv; | |
157 | ||
158 | /* set timer busy */ | |
159 | priv->idle &= ~casc_priv->cascade_map; | |
160 | spin_unlock_irqrestore(&priv->lock, flags); | |
161 | return &priv->timer[num]; | |
162 | } | |
163 | spin_unlock_irqrestore(&priv->lock, flags); | |
164 | casc_priv++; | |
165 | } | |
166 | ||
167 | return NULL; | |
168 | } | |
169 | ||
170 | static int set_cascade_timer(struct timer_group_priv *priv, u64 ticks, | |
171 | unsigned int num) | |
172 | { | |
173 | struct cascade_priv *casc_priv; | |
174 | u32 tcr; | |
175 | u32 tmp_ticks; | |
176 | u32 rem_ticks; | |
177 | ||
178 | /* set group tcr reg for cascade */ | |
179 | casc_priv = priv->timer[num].cascade_handle; | |
180 | if (!casc_priv) | |
181 | return -EINVAL; | |
182 | ||
183 | tcr = casc_priv->tcr_value | | |
184 | (casc_priv->tcr_value << MPIC_TIMER_TCR_ROVR_OFFSET); | |
185 | setbits32(priv->group_tcr, tcr); | |
186 | ||
187 | tmp_ticks = div_u64_rem(ticks, MAX_TICKS_CASCADE, &rem_ticks); | |
188 | ||
189 | out_be32(&priv->regs[num].gtccr, 0); | |
190 | out_be32(&priv->regs[num].gtbcr, tmp_ticks | TIMER_STOP); | |
191 | ||
192 | out_be32(&priv->regs[num - 1].gtccr, 0); | |
193 | out_be32(&priv->regs[num - 1].gtbcr, rem_ticks); | |
194 | ||
195 | return 0; | |
196 | } | |
197 | ||
198 | static struct mpic_timer *get_cascade_timer(struct timer_group_priv *priv, | |
199 | u64 ticks) | |
200 | { | |
201 | struct mpic_timer *allocated_timer; | |
202 | ||
203 | /* Two cascade timers: Support the maximum time */ | |
204 | const u64 max_ticks = (u64)MAX_TICKS * (u64)MAX_TICKS_CASCADE; | |
205 | int ret; | |
206 | ||
207 | if (ticks > max_ticks) | |
208 | return NULL; | |
209 | ||
210 | /* detect idle timer */ | |
211 | allocated_timer = detect_idle_cascade_timer(priv); | |
212 | if (!allocated_timer) | |
213 | return NULL; | |
214 | ||
215 | /* set ticks to timer */ | |
216 | ret = set_cascade_timer(priv, ticks, allocated_timer->num); | |
217 | if (ret < 0) | |
218 | return NULL; | |
219 | ||
220 | return allocated_timer; | |
221 | } | |
222 | ||
223 | static struct mpic_timer *get_timer(const struct timeval *time) | |
224 | { | |
225 | struct timer_group_priv *priv; | |
226 | struct mpic_timer *timer; | |
227 | ||
228 | u64 ticks; | |
229 | unsigned int num; | |
230 | unsigned int i; | |
231 | unsigned long flags; | |
232 | int ret; | |
233 | ||
234 | list_for_each_entry(priv, &timer_group_list, node) { | |
235 | ret = convert_time_to_ticks(priv, time, &ticks); | |
236 | if (ret < 0) | |
237 | return NULL; | |
238 | ||
239 | if (ticks > MAX_TICKS) { | |
240 | if (!(priv->flags & FSL_GLOBAL_TIMER)) | |
241 | return NULL; | |
242 | ||
243 | timer = get_cascade_timer(priv, ticks); | |
244 | if (!timer) | |
245 | continue; | |
246 | ||
247 | return timer; | |
248 | } | |
249 | ||
250 | for (i = 0; i < TIMERS_PER_GROUP; i++) { | |
251 | /* one timer: Reverse allocation */ | |
252 | num = TIMERS_PER_GROUP - 1 - i; | |
253 | spin_lock_irqsave(&priv->lock, flags); | |
254 | if (priv->idle & (1 << i)) { | |
255 | /* set timer busy */ | |
256 | priv->idle &= ~(1 << i); | |
257 | /* set ticks & stop timer */ | |
258 | out_be32(&priv->regs[num].gtbcr, | |
259 | ticks | TIMER_STOP); | |
260 | out_be32(&priv->regs[num].gtccr, 0); | |
261 | priv->timer[num].cascade_handle = NULL; | |
262 | spin_unlock_irqrestore(&priv->lock, flags); | |
263 | return &priv->timer[num]; | |
264 | } | |
265 | spin_unlock_irqrestore(&priv->lock, flags); | |
266 | } | |
267 | } | |
268 | ||
269 | return NULL; | |
270 | } | |
271 | ||
272 | /** | |
273 | * mpic_start_timer - start hardware timer | |
274 | * @handle: the timer to be started. | |
275 | * | |
276 | * It will do ->fn(->dev) callback from the hardware interrupt at | |
277 | * the ->timeval point in the future. | |
278 | */ | |
279 | void mpic_start_timer(struct mpic_timer *handle) | |
280 | { | |
281 | struct timer_group_priv *priv = container_of(handle, | |
282 | struct timer_group_priv, timer[handle->num]); | |
283 | ||
284 | clrbits32(&priv->regs[handle->num].gtbcr, TIMER_STOP); | |
285 | } | |
286 | EXPORT_SYMBOL(mpic_start_timer); | |
287 | ||
288 | /** | |
289 | * mpic_stop_timer - stop hardware timer | |
290 | * @handle: the timer to be stoped | |
291 | * | |
292 | * The timer periodically generates an interrupt. Unless user stops the timer. | |
293 | */ | |
294 | void mpic_stop_timer(struct mpic_timer *handle) | |
295 | { | |
296 | struct timer_group_priv *priv = container_of(handle, | |
297 | struct timer_group_priv, timer[handle->num]); | |
298 | struct cascade_priv *casc_priv; | |
299 | ||
300 | setbits32(&priv->regs[handle->num].gtbcr, TIMER_STOP); | |
301 | ||
302 | casc_priv = priv->timer[handle->num].cascade_handle; | |
303 | if (casc_priv) { | |
304 | out_be32(&priv->regs[handle->num].gtccr, 0); | |
305 | out_be32(&priv->regs[handle->num - 1].gtccr, 0); | |
306 | } else { | |
307 | out_be32(&priv->regs[handle->num].gtccr, 0); | |
308 | } | |
309 | } | |
310 | EXPORT_SYMBOL(mpic_stop_timer); | |
311 | ||
312 | /** | |
313 | * mpic_get_remain_time - get timer time | |
314 | * @handle: the timer to be selected. | |
315 | * @time: time for timer | |
316 | * | |
317 | * Query timer remaining time. | |
318 | */ | |
319 | void mpic_get_remain_time(struct mpic_timer *handle, struct timeval *time) | |
320 | { | |
321 | struct timer_group_priv *priv = container_of(handle, | |
322 | struct timer_group_priv, timer[handle->num]); | |
323 | struct cascade_priv *casc_priv; | |
324 | ||
325 | u64 ticks; | |
326 | u32 tmp_ticks; | |
327 | ||
328 | casc_priv = priv->timer[handle->num].cascade_handle; | |
329 | if (casc_priv) { | |
330 | tmp_ticks = in_be32(&priv->regs[handle->num].gtccr); | |
0fd79588 | 331 | tmp_ticks &= ~GTCCR_TOG; |
36ca09be D |
332 | ticks = ((u64)tmp_ticks & UINT_MAX) * (u64)MAX_TICKS_CASCADE; |
333 | tmp_ticks = in_be32(&priv->regs[handle->num - 1].gtccr); | |
334 | ticks += tmp_ticks; | |
335 | } else { | |
336 | ticks = in_be32(&priv->regs[handle->num].gtccr); | |
0fd79588 | 337 | ticks &= ~GTCCR_TOG; |
36ca09be D |
338 | } |
339 | ||
340 | convert_ticks_to_time(priv, ticks, time); | |
341 | } | |
342 | EXPORT_SYMBOL(mpic_get_remain_time); | |
343 | ||
344 | /** | |
345 | * mpic_free_timer - free hardware timer | |
346 | * @handle: the timer to be removed. | |
347 | * | |
348 | * Free the timer. | |
349 | * | |
350 | * Note: can not be used in interrupt context. | |
351 | */ | |
352 | void mpic_free_timer(struct mpic_timer *handle) | |
353 | { | |
354 | struct timer_group_priv *priv = container_of(handle, | |
355 | struct timer_group_priv, timer[handle->num]); | |
356 | ||
357 | struct cascade_priv *casc_priv; | |
358 | unsigned long flags; | |
359 | ||
360 | mpic_stop_timer(handle); | |
361 | ||
362 | casc_priv = priv->timer[handle->num].cascade_handle; | |
363 | ||
364 | free_irq(priv->timer[handle->num].irq, priv->timer[handle->num].dev); | |
365 | ||
366 | spin_lock_irqsave(&priv->lock, flags); | |
367 | if (casc_priv) { | |
368 | u32 tcr; | |
369 | tcr = casc_priv->tcr_value | (casc_priv->tcr_value << | |
370 | MPIC_TIMER_TCR_ROVR_OFFSET); | |
371 | clrbits32(priv->group_tcr, tcr); | |
372 | priv->idle |= casc_priv->cascade_map; | |
373 | priv->timer[handle->num].cascade_handle = NULL; | |
374 | } else { | |
375 | priv->idle |= TIMER_OFFSET(handle->num); | |
376 | } | |
377 | spin_unlock_irqrestore(&priv->lock, flags); | |
378 | } | |
379 | EXPORT_SYMBOL(mpic_free_timer); | |
380 | ||
381 | /** | |
382 | * mpic_request_timer - get a hardware timer | |
383 | * @fn: interrupt handler function | |
384 | * @dev: callback function of the data | |
385 | * @time: time for timer | |
386 | * | |
387 | * This executes the "request_irq", returning NULL | |
388 | * else "handle" on success. | |
389 | */ | |
390 | struct mpic_timer *mpic_request_timer(irq_handler_t fn, void *dev, | |
391 | const struct timeval *time) | |
392 | { | |
393 | struct mpic_timer *allocated_timer; | |
394 | int ret; | |
395 | ||
396 | if (list_empty(&timer_group_list)) | |
397 | return NULL; | |
398 | ||
399 | if (!(time->tv_sec + time->tv_usec) || | |
400 | time->tv_sec < 0 || time->tv_usec < 0) | |
401 | return NULL; | |
402 | ||
403 | if (time->tv_usec > ONE_SECOND) | |
404 | return NULL; | |
405 | ||
406 | allocated_timer = get_timer(time); | |
407 | if (!allocated_timer) | |
408 | return NULL; | |
409 | ||
410 | ret = request_irq(allocated_timer->irq, fn, | |
411 | IRQF_TRIGGER_LOW, "global-timer", dev); | |
412 | if (ret) { | |
413 | mpic_free_timer(allocated_timer); | |
414 | return NULL; | |
415 | } | |
416 | ||
417 | allocated_timer->dev = dev; | |
418 | ||
419 | return allocated_timer; | |
420 | } | |
421 | EXPORT_SYMBOL(mpic_request_timer); | |
422 | ||
423 | static int timer_group_get_freq(struct device_node *np, | |
424 | struct timer_group_priv *priv) | |
425 | { | |
426 | u32 div; | |
427 | ||
428 | if (priv->flags & FSL_GLOBAL_TIMER) { | |
429 | struct device_node *dn; | |
430 | ||
431 | dn = of_find_compatible_node(NULL, NULL, "fsl,mpic"); | |
432 | if (dn) { | |
433 | of_property_read_u32(dn, "clock-frequency", | |
434 | &priv->timerfreq); | |
435 | of_node_put(dn); | |
436 | } | |
437 | } | |
438 | ||
439 | if (priv->timerfreq <= 0) | |
440 | return -EINVAL; | |
441 | ||
442 | if (priv->flags & FSL_GLOBAL_TIMER) { | |
443 | div = (1 << (MPIC_TIMER_TCR_CLKDIV >> 8)) * 8; | |
444 | priv->timerfreq /= div; | |
445 | } | |
446 | ||
447 | return 0; | |
448 | } | |
449 | ||
450 | static int timer_group_get_irq(struct device_node *np, | |
451 | struct timer_group_priv *priv) | |
452 | { | |
453 | const u32 all_timer[] = { 0, TIMERS_PER_GROUP }; | |
454 | const u32 *p; | |
455 | u32 offset; | |
456 | u32 count; | |
457 | ||
458 | unsigned int i; | |
459 | unsigned int j; | |
460 | unsigned int irq_index = 0; | |
461 | unsigned int irq; | |
462 | int len; | |
463 | ||
464 | p = of_get_property(np, "fsl,available-ranges", &len); | |
465 | if (p && len % (2 * sizeof(u32)) != 0) { | |
466 | pr_err("%s: malformed available-ranges property.\n", | |
467 | np->full_name); | |
468 | return -EINVAL; | |
469 | } | |
470 | ||
471 | if (!p) { | |
472 | p = all_timer; | |
473 | len = sizeof(all_timer); | |
474 | } | |
475 | ||
476 | len /= 2 * sizeof(u32); | |
477 | ||
478 | for (i = 0; i < len; i++) { | |
479 | offset = p[i * 2]; | |
480 | count = p[i * 2 + 1]; | |
481 | for (j = 0; j < count; j++) { | |
482 | irq = irq_of_parse_and_map(np, irq_index); | |
483 | if (!irq) { | |
484 | pr_err("%s: irq parse and map failed.\n", | |
485 | np->full_name); | |
486 | return -EINVAL; | |
487 | } | |
488 | ||
489 | /* Set timer idle */ | |
490 | priv->idle |= TIMER_OFFSET((offset + j)); | |
491 | priv->timer[offset + j].irq = irq; | |
492 | priv->timer[offset + j].num = offset + j; | |
493 | irq_index++; | |
494 | } | |
495 | } | |
496 | ||
497 | return 0; | |
498 | } | |
499 | ||
500 | static void timer_group_init(struct device_node *np) | |
501 | { | |
502 | struct timer_group_priv *priv; | |
503 | unsigned int i = 0; | |
504 | int ret; | |
505 | ||
506 | priv = kzalloc(sizeof(struct timer_group_priv), GFP_KERNEL); | |
507 | if (!priv) { | |
508 | pr_err("%s: cannot allocate memory for group.\n", | |
509 | np->full_name); | |
510 | return; | |
511 | } | |
512 | ||
513 | if (of_device_is_compatible(np, "fsl,mpic-global-timer")) | |
514 | priv->flags |= FSL_GLOBAL_TIMER; | |
515 | ||
516 | priv->regs = of_iomap(np, i++); | |
517 | if (!priv->regs) { | |
518 | pr_err("%s: cannot ioremap timer register address.\n", | |
519 | np->full_name); | |
520 | goto out; | |
521 | } | |
522 | ||
523 | if (priv->flags & FSL_GLOBAL_TIMER) { | |
524 | priv->group_tcr = of_iomap(np, i++); | |
525 | if (!priv->group_tcr) { | |
526 | pr_err("%s: cannot ioremap tcr address.\n", | |
527 | np->full_name); | |
528 | goto out; | |
529 | } | |
530 | } | |
531 | ||
532 | ret = timer_group_get_freq(np, priv); | |
533 | if (ret < 0) { | |
534 | pr_err("%s: cannot get timer frequency.\n", np->full_name); | |
535 | goto out; | |
536 | } | |
537 | ||
538 | ret = timer_group_get_irq(np, priv); | |
539 | if (ret < 0) { | |
540 | pr_err("%s: cannot get timer irqs.\n", np->full_name); | |
541 | goto out; | |
542 | } | |
543 | ||
544 | spin_lock_init(&priv->lock); | |
545 | ||
546 | /* Init FSL timer hardware */ | |
547 | if (priv->flags & FSL_GLOBAL_TIMER) | |
548 | setbits32(priv->group_tcr, MPIC_TIMER_TCR_CLKDIV); | |
549 | ||
550 | list_add_tail(&priv->node, &timer_group_list); | |
551 | ||
552 | return; | |
553 | ||
554 | out: | |
555 | if (priv->regs) | |
556 | iounmap(priv->regs); | |
557 | ||
558 | if (priv->group_tcr) | |
559 | iounmap(priv->group_tcr); | |
560 | ||
561 | kfree(priv); | |
562 | } | |
563 | ||
564 | static void mpic_timer_resume(void) | |
565 | { | |
566 | struct timer_group_priv *priv; | |
567 | ||
568 | list_for_each_entry(priv, &timer_group_list, node) { | |
569 | /* Init FSL timer hardware */ | |
570 | if (priv->flags & FSL_GLOBAL_TIMER) | |
571 | setbits32(priv->group_tcr, MPIC_TIMER_TCR_CLKDIV); | |
572 | } | |
573 | } | |
574 | ||
575 | static const struct of_device_id mpic_timer_ids[] = { | |
576 | { .compatible = "fsl,mpic-global-timer", }, | |
577 | {}, | |
578 | }; | |
579 | ||
580 | static struct syscore_ops mpic_timer_syscore_ops = { | |
581 | .resume = mpic_timer_resume, | |
582 | }; | |
583 | ||
584 | static int __init mpic_timer_init(void) | |
585 | { | |
586 | struct device_node *np = NULL; | |
587 | ||
588 | for_each_matching_node(np, mpic_timer_ids) | |
589 | timer_group_init(np); | |
590 | ||
591 | register_syscore_ops(&mpic_timer_syscore_ops); | |
592 | ||
593 | if (list_empty(&timer_group_list)) | |
594 | return -ENODEV; | |
595 | ||
596 | return 0; | |
597 | } | |
598 | subsys_initcall(mpic_timer_init); |