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05af7bd2 ME |
1 | /* |
2 | * Copyright 2006, Segher Boessenkool, IBM Corporation. | |
3 | * Copyright 2006-2007, Michael Ellerman, IBM Corporation. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; version 2 of the | |
8 | * License. | |
9 | * | |
10 | */ | |
11 | ||
12 | #include <linux/irq.h> | |
05af7bd2 ME |
13 | #include <linux/msi.h> |
14 | #include <asm/mpic.h> | |
15 | #include <asm/prom.h> | |
16 | #include <asm/hw_irq.h> | |
17 | #include <asm/ppc-pci.h> | |
25235f71 | 18 | #include <asm/msi_bitmap.h> |
05af7bd2 ME |
19 | |
20 | #include "mpic.h" | |
21 | ||
22 | /* A bit ugly, can we get this from the pci_dev somehow? */ | |
23 | static struct mpic *msi_mpic; | |
24 | ||
1c9db525 | 25 | static void mpic_u3msi_mask_irq(struct irq_data *data) |
05af7bd2 | 26 | { |
280510f1 | 27 | pci_msi_mask_irq(data); |
835c0553 | 28 | mpic_mask_irq(data); |
05af7bd2 ME |
29 | } |
30 | ||
1c9db525 | 31 | static void mpic_u3msi_unmask_irq(struct irq_data *data) |
05af7bd2 | 32 | { |
835c0553 | 33 | mpic_unmask_irq(data); |
280510f1 | 34 | pci_msi_unmask_irq(data); |
05af7bd2 ME |
35 | } |
36 | ||
37 | static struct irq_chip mpic_u3msi_chip = { | |
835c0553 LB |
38 | .irq_shutdown = mpic_u3msi_mask_irq, |
39 | .irq_mask = mpic_u3msi_mask_irq, | |
40 | .irq_unmask = mpic_u3msi_unmask_irq, | |
41 | .irq_eoi = mpic_end_irq, | |
42 | .irq_set_type = mpic_set_irq_type, | |
43 | .irq_set_affinity = mpic_set_affinity, | |
44 | .name = "MPIC-U3MSI", | |
05af7bd2 ME |
45 | }; |
46 | ||
47 | static u64 read_ht_magic_addr(struct pci_dev *pdev, unsigned int pos) | |
48 | { | |
49 | u8 flags; | |
50 | u32 tmp; | |
51 | u64 addr; | |
52 | ||
53 | pci_read_config_byte(pdev, pos + HT_MSI_FLAGS, &flags); | |
54 | ||
55 | if (flags & HT_MSI_FLAGS_FIXED) | |
56 | return HT_MSI_FIXED_ADDR; | |
57 | ||
58 | pci_read_config_dword(pdev, pos + HT_MSI_ADDR_LO, &tmp); | |
59 | addr = tmp & HT_MSI_ADDR_LO_MASK; | |
60 | pci_read_config_dword(pdev, pos + HT_MSI_ADDR_HI, &tmp); | |
61 | addr = addr | ((u64)tmp << 32); | |
62 | ||
63 | return addr; | |
64 | } | |
65 | ||
7a96c6b2 | 66 | static u64 find_ht_magic_addr(struct pci_dev *pdev, unsigned int hwirq) |
05af7bd2 ME |
67 | { |
68 | struct pci_bus *bus; | |
69 | unsigned int pos; | |
70 | ||
7a96c6b2 | 71 | for (bus = pdev->bus; bus && bus->self; bus = bus->parent) { |
05af7bd2 ME |
72 | pos = pci_find_ht_capability(bus->self, HT_CAPTYPE_MSI_MAPPING); |
73 | if (pos) | |
74 | return read_ht_magic_addr(bus->self, pos); | |
75 | } | |
76 | ||
77 | return 0; | |
78 | } | |
79 | ||
7a96c6b2 BH |
80 | static u64 find_u4_magic_addr(struct pci_dev *pdev, unsigned int hwirq) |
81 | { | |
82 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); | |
83 | ||
84 | /* U4 PCIe MSIs need to write to the special register in | |
85 | * the bridge that generates interrupts. There should be | |
86 | * theorically a register at 0xf8005000 where you just write | |
87 | * the MSI number and that triggers the right interrupt, but | |
88 | * unfortunately, this is busted in HW, the bridge endian swaps | |
89 | * the value and hits the wrong nibble in the register. | |
90 | * | |
91 | * So instead we use another register set which is used normally | |
92 | * for converting HT interrupts to MPIC interrupts, which decodes | |
93 | * the interrupt number as part of the low address bits | |
94 | * | |
95 | * This will not work if we ever use more than one legacy MSI in | |
96 | * a block but we never do. For one MSI or multiple MSI-X where | |
97 | * each interrupt address can be specified separately, it works | |
98 | * just fine. | |
99 | */ | |
100 | if (of_device_is_compatible(hose->dn, "u4-pcie") || | |
101 | of_device_is_compatible(hose->dn, "U4-pcie")) | |
102 | return 0xf8004000 | (hwirq << 4); | |
103 | ||
104 | return 0; | |
105 | } | |
106 | ||
05af7bd2 ME |
107 | static void u3msi_teardown_msi_irqs(struct pci_dev *pdev) |
108 | { | |
109 | struct msi_desc *entry; | |
e297c939 | 110 | irq_hw_number_t hwirq; |
05af7bd2 | 111 | |
2921d179 | 112 | for_each_pci_msi_entry(entry, pdev) { |
05af7bd2 ME |
113 | if (entry->irq == NO_IRQ) |
114 | continue; | |
115 | ||
e297c939 | 116 | hwirq = virq_to_hw(entry->irq); |
ec775d0e | 117 | irq_set_msi_desc(entry->irq, NULL); |
05af7bd2 | 118 | irq_dispose_mapping(entry->irq); |
e297c939 | 119 | msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, hwirq, 1); |
05af7bd2 ME |
120 | } |
121 | ||
122 | return; | |
123 | } | |
124 | ||
05af7bd2 ME |
125 | static int u3msi_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) |
126 | { | |
05af7bd2 ME |
127 | unsigned int virq; |
128 | struct msi_desc *entry; | |
129 | struct msi_msg msg; | |
21ccdd31 | 130 | u64 addr; |
25235f71 | 131 | int hwirq; |
21ccdd31 | 132 | |
6b2fd7ef AG |
133 | if (type == PCI_CAP_ID_MSIX) |
134 | pr_debug("u3msi: MSI-X untested, trying anyway.\n"); | |
135 | ||
136 | /* If we can't find a magic address then MSI ain't gonna work */ | |
137 | if (find_ht_magic_addr(pdev, 0) == 0 && | |
138 | find_u4_magic_addr(pdev, 0) == 0) { | |
139 | pr_debug("u3msi: no magic address found for %s\n", | |
140 | pci_name(pdev)); | |
141 | return -ENXIO; | |
142 | } | |
143 | ||
2921d179 | 144 | for_each_pci_msi_entry(entry, pdev) { |
25235f71 ME |
145 | hwirq = msi_bitmap_alloc_hwirqs(&msi_mpic->msi_bitmap, 1); |
146 | if (hwirq < 0) { | |
05af7bd2 | 147 | pr_debug("u3msi: failed allocating hwirq\n"); |
25235f71 | 148 | return hwirq; |
05af7bd2 ME |
149 | } |
150 | ||
7a96c6b2 BH |
151 | addr = find_ht_magic_addr(pdev, hwirq); |
152 | if (addr == 0) | |
153 | addr = find_u4_magic_addr(pdev, hwirq); | |
154 | msg.address_lo = addr & 0xFFFFFFFF; | |
155 | msg.address_hi = addr >> 32; | |
156 | ||
05af7bd2 ME |
157 | virq = irq_create_mapping(msi_mpic->irqhost, hwirq); |
158 | if (virq == NO_IRQ) { | |
25235f71 ME |
159 | pr_debug("u3msi: failed mapping hwirq 0x%x\n", hwirq); |
160 | msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, hwirq, 1); | |
d9303d66 | 161 | return -ENOSPC; |
05af7bd2 ME |
162 | } |
163 | ||
ec775d0e TG |
164 | irq_set_msi_desc(virq, entry); |
165 | irq_set_chip(virq, &mpic_u3msi_chip); | |
166 | irq_set_irq_type(virq, IRQ_TYPE_EDGE_RISING); | |
05af7bd2 | 167 | |
25235f71 ME |
168 | pr_debug("u3msi: allocated virq 0x%x (hw 0x%x) addr 0x%lx\n", |
169 | virq, hwirq, (unsigned long)addr); | |
21ccdd31 | 170 | |
7a96c6b2 BH |
171 | printk("u3msi: allocated virq 0x%x (hw 0x%x) addr 0x%lx\n", |
172 | virq, hwirq, (unsigned long)addr); | |
21ccdd31 | 173 | msg.data = hwirq; |
83a18912 | 174 | pci_write_msi_msg(virq, &msg); |
05af7bd2 ME |
175 | |
176 | hwirq++; | |
177 | } | |
178 | ||
179 | return 0; | |
05af7bd2 ME |
180 | } |
181 | ||
182 | int mpic_u3msi_init(struct mpic *mpic) | |
183 | { | |
184 | int rc; | |
14f95acd | 185 | struct pci_controller *phb; |
05af7bd2 ME |
186 | |
187 | rc = mpic_msi_init_allocator(mpic); | |
188 | if (rc) { | |
189 | pr_debug("u3msi: Error allocating bitmap!\n"); | |
190 | return rc; | |
191 | } | |
192 | ||
193 | pr_debug("u3msi: Registering MPIC U3 MSI callbacks.\n"); | |
194 | ||
195 | BUG_ON(msi_mpic); | |
196 | msi_mpic = mpic; | |
197 | ||
14f95acd DA |
198 | list_for_each_entry(phb, &hose_list, list_node) { |
199 | WARN_ON(phb->controller_ops.setup_msi_irqs); | |
200 | phb->controller_ops.setup_msi_irqs = u3msi_setup_msi_irqs; | |
201 | phb->controller_ops.teardown_msi_irqs = u3msi_teardown_msi_irqs; | |
202 | } | |
05af7bd2 ME |
203 | |
204 | return 0; | |
205 | } |