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5738ec6d BH |
1 | /* |
2 | * PCI / PCI-X / PCI-Express support for 4xx parts | |
3 | * | |
4 | * Copyright 2007 Ben. Herrenschmidt <benh@kernel.crashing.org>, IBM Corp. | |
5 | * | |
a2d2e1ec BH |
6 | * Most PCI Express code is coming from Stefan Roese implementation for |
7 | * arch/ppc in the Denx tree, slightly reworked by me. | |
8 | * | |
9 | * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de> | |
10 | * | |
11 | * Some of that comes itself from a previous implementation for 440SPE only | |
12 | * by Roland Dreier: | |
13 | * | |
14 | * Copyright (c) 2005 Cisco Systems. All rights reserved. | |
15 | * Roland Dreier <rolandd@cisco.com> | |
16 | * | |
5738ec6d BH |
17 | */ |
18 | ||
035ee428 BH |
19 | #undef DEBUG |
20 | ||
5738ec6d BH |
21 | #include <linux/kernel.h> |
22 | #include <linux/pci.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/of.h> | |
a2d2e1ec BH |
25 | #include <linux/bootmem.h> |
26 | #include <linux/delay.h> | |
5a0e3ad6 | 27 | #include <linux/slab.h> |
5738ec6d BH |
28 | |
29 | #include <asm/io.h> | |
30 | #include <asm/pci-bridge.h> | |
31 | #include <asm/machdep.h> | |
a2d2e1ec BH |
32 | #include <asm/dcr.h> |
33 | #include <asm/dcr-regs.h> | |
cc2e113b | 34 | #include <mm/mmu_decl.h> |
5738ec6d BH |
35 | |
36 | #include "ppc4xx_pci.h" | |
37 | ||
38 | static int dma_offset_set; | |
39 | ||
a2d2e1ec BH |
40 | #define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL)) |
41 | #define U64_TO_U32_HIGH(val) ((u32)((val) >> 32)) | |
42 | ||
8308c54d JF |
43 | #define RES_TO_U32_LOW(val) \ |
44 | ((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_LOW(val) : (val)) | |
45 | #define RES_TO_U32_HIGH(val) \ | |
46 | ((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_HIGH(val) : (0)) | |
a2d2e1ec | 47 | |
accf5ef2 SR |
48 | static inline int ppc440spe_revA(void) |
49 | { | |
50 | /* Catch both 440SPe variants, with and without RAID6 support */ | |
51 | if ((mfspr(SPRN_PVR) & 0xffefffff) == 0x53421890) | |
52 | return 1; | |
53 | else | |
54 | return 0; | |
55 | } | |
56 | ||
c839e0ef BH |
57 | static void fixup_ppc4xx_pci_bridge(struct pci_dev *dev) |
58 | { | |
59 | struct pci_controller *hose; | |
60 | int i; | |
61 | ||
62 | if (dev->devfn != 0 || dev->bus->self != NULL) | |
63 | return; | |
64 | ||
65 | hose = pci_bus_to_host(dev->bus); | |
66 | if (hose == NULL) | |
67 | return; | |
68 | ||
69 | if (!of_device_is_compatible(hose->dn, "ibm,plb-pciex") && | |
70 | !of_device_is_compatible(hose->dn, "ibm,plb-pcix") && | |
71 | !of_device_is_compatible(hose->dn, "ibm,plb-pci")) | |
72 | return; | |
73 | ||
5ce4b596 JB |
74 | if (of_device_is_compatible(hose->dn, "ibm,plb440epx-pci") || |
75 | of_device_is_compatible(hose->dn, "ibm,plb440grx-pci")) { | |
76 | hose->indirect_type |= PPC_INDIRECT_TYPE_BROKEN_MRM; | |
77 | } | |
78 | ||
c839e0ef BH |
79 | /* Hide the PCI host BARs from the kernel as their content doesn't |
80 | * fit well in the resource management | |
81 | */ | |
82 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
83 | dev->resource[i].start = dev->resource[i].end = 0; | |
84 | dev->resource[i].flags = 0; | |
85 | } | |
86 | ||
87 | printk(KERN_INFO "PCI: Hiding 4xx host bridge resources %s\n", | |
88 | pci_name(dev)); | |
89 | } | |
90 | DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, fixup_ppc4xx_pci_bridge); | |
91 | ||
5738ec6d BH |
92 | static int __init ppc4xx_parse_dma_ranges(struct pci_controller *hose, |
93 | void __iomem *reg, | |
94 | struct resource *res) | |
95 | { | |
96 | u64 size; | |
97 | const u32 *ranges; | |
98 | int rlen; | |
99 | int pna = of_n_addr_cells(hose->dn); | |
100 | int np = pna + 5; | |
101 | ||
102 | /* Default */ | |
103 | res->start = 0; | |
cc2e113b IY |
104 | size = 0x80000000; |
105 | res->end = size - 1; | |
5738ec6d BH |
106 | res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; |
107 | ||
108 | /* Get dma-ranges property */ | |
109 | ranges = of_get_property(hose->dn, "dma-ranges", &rlen); | |
110 | if (ranges == NULL) | |
111 | goto out; | |
112 | ||
113 | /* Walk it */ | |
114 | while ((rlen -= np * 4) >= 0) { | |
115 | u32 pci_space = ranges[0]; | |
116 | u64 pci_addr = of_read_number(ranges + 1, 2); | |
117 | u64 cpu_addr = of_translate_dma_address(hose->dn, ranges + 3); | |
118 | size = of_read_number(ranges + pna + 3, 2); | |
119 | ranges += np; | |
120 | if (cpu_addr == OF_BAD_ADDR || size == 0) | |
121 | continue; | |
122 | ||
123 | /* We only care about memory */ | |
124 | if ((pci_space & 0x03000000) != 0x02000000) | |
125 | continue; | |
126 | ||
127 | /* We currently only support memory at 0, and pci_addr | |
128 | * within 32 bits space | |
129 | */ | |
130 | if (cpu_addr != 0 || pci_addr > 0xffffffff) { | |
131 | printk(KERN_WARNING "%s: Ignored unsupported dma range" | |
132 | " 0x%016llx...0x%016llx -> 0x%016llx\n", | |
133 | hose->dn->full_name, | |
134 | pci_addr, pci_addr + size - 1, cpu_addr); | |
135 | continue; | |
136 | } | |
137 | ||
138 | /* Check if not prefetchable */ | |
139 | if (!(pci_space & 0x40000000)) | |
140 | res->flags &= ~IORESOURCE_PREFETCH; | |
141 | ||
142 | ||
143 | /* Use that */ | |
144 | res->start = pci_addr; | |
5738ec6d | 145 | /* Beware of 32 bits resources */ |
8308c54d JF |
146 | if (sizeof(resource_size_t) == sizeof(u32) && |
147 | (pci_addr + size) > 0x100000000ull) | |
5738ec6d BH |
148 | res->end = 0xffffffff; |
149 | else | |
5738ec6d BH |
150 | res->end = res->start + size - 1; |
151 | break; | |
152 | } | |
153 | ||
154 | /* We only support one global DMA offset */ | |
155 | if (dma_offset_set && pci_dram_offset != res->start) { | |
156 | printk(KERN_ERR "%s: dma-ranges(s) mismatch\n", | |
157 | hose->dn->full_name); | |
158 | return -ENXIO; | |
159 | } | |
160 | ||
161 | /* Check that we can fit all of memory as we don't support | |
162 | * DMA bounce buffers | |
163 | */ | |
164 | if (size < total_memory) { | |
165 | printk(KERN_ERR "%s: dma-ranges too small " | |
cc2e113b IY |
166 | "(size=%llx total_memory=%llx)\n", |
167 | hose->dn->full_name, size, (u64)total_memory); | |
5738ec6d BH |
168 | return -ENXIO; |
169 | } | |
170 | ||
171 | /* Check we are a power of 2 size and that base is a multiple of size*/ | |
cc2e113b | 172 | if ((size & (size - 1)) != 0 || |
5738ec6d BH |
173 | (res->start & (size - 1)) != 0) { |
174 | printk(KERN_ERR "%s: dma-ranges unaligned\n", | |
175 | hose->dn->full_name); | |
176 | return -ENXIO; | |
177 | } | |
178 | ||
179 | /* Check that we are fully contained within 32 bits space */ | |
180 | if (res->end > 0xffffffff) { | |
181 | printk(KERN_ERR "%s: dma-ranges outside of 32 bits space\n", | |
182 | hose->dn->full_name); | |
183 | return -ENXIO; | |
184 | } | |
185 | out: | |
186 | dma_offset_set = 1; | |
187 | pci_dram_offset = res->start; | |
188 | ||
189 | printk(KERN_INFO "4xx PCI DMA offset set to 0x%08lx\n", | |
190 | pci_dram_offset); | |
191 | return 0; | |
192 | } | |
193 | ||
194 | /* | |
195 | * 4xx PCI 2.x part | |
196 | */ | |
c839e0ef | 197 | |
84d727a1 BH |
198 | static int __init ppc4xx_setup_one_pci_PMM(struct pci_controller *hose, |
199 | void __iomem *reg, | |
200 | u64 plb_addr, | |
201 | u64 pci_addr, | |
202 | u64 size, | |
203 | unsigned int flags, | |
204 | int index) | |
205 | { | |
206 | u32 ma, pcila, pciha; | |
207 | ||
1ac00cc2 BH |
208 | /* Hack warning ! The "old" PCI 2.x cell only let us configure the low |
209 | * 32-bit of incoming PLB addresses. The top 4 bits of the 36-bit | |
210 | * address are actually hard wired to a value that appears to depend | |
211 | * on the specific SoC. For example, it's 0 on 440EP and 1 on 440EPx. | |
212 | * | |
213 | * The trick here is we just crop those top bits and ignore them when | |
214 | * programming the chip. That means the device-tree has to be right | |
215 | * for the specific part used (we don't print a warning if it's wrong | |
216 | * but on the other hand, you'll crash quickly enough), but at least | |
217 | * this code should work whatever the hard coded value is | |
218 | */ | |
219 | plb_addr &= 0xffffffffull; | |
220 | ||
221 | /* Note: Due to the above hack, the test below doesn't actually test | |
222 | * if you address is above 4G, but it tests that address and | |
223 | * (address + size) are both contained in the same 4G | |
224 | */ | |
84d727a1 BH |
225 | if ((plb_addr + size) > 0xffffffffull || !is_power_of_2(size) || |
226 | size < 0x1000 || (plb_addr & (size - 1)) != 0) { | |
227 | printk(KERN_WARNING "%s: Resource out of range\n", | |
228 | hose->dn->full_name); | |
229 | return -1; | |
230 | } | |
231 | ma = (0xffffffffu << ilog2(size)) | 1; | |
232 | if (flags & IORESOURCE_PREFETCH) | |
233 | ma |= 2; | |
234 | ||
235 | pciha = RES_TO_U32_HIGH(pci_addr); | |
236 | pcila = RES_TO_U32_LOW(pci_addr); | |
237 | ||
238 | writel(plb_addr, reg + PCIL0_PMM0LA + (0x10 * index)); | |
239 | writel(pcila, reg + PCIL0_PMM0PCILA + (0x10 * index)); | |
240 | writel(pciha, reg + PCIL0_PMM0PCIHA + (0x10 * index)); | |
241 | writel(ma, reg + PCIL0_PMM0MA + (0x10 * index)); | |
242 | ||
243 | return 0; | |
244 | } | |
245 | ||
c839e0ef BH |
246 | static void __init ppc4xx_configure_pci_PMMs(struct pci_controller *hose, |
247 | void __iomem *reg) | |
248 | { | |
84d727a1 | 249 | int i, j, found_isa_hole = 0; |
c839e0ef BH |
250 | |
251 | /* Setup outbound memory windows */ | |
252 | for (i = j = 0; i < 3; i++) { | |
253 | struct resource *res = &hose->mem_resources[i]; | |
254 | ||
255 | /* we only care about memory windows */ | |
256 | if (!(res->flags & IORESOURCE_MEM)) | |
257 | continue; | |
258 | if (j > 2) { | |
259 | printk(KERN_WARNING "%s: Too many ranges\n", | |
260 | hose->dn->full_name); | |
261 | break; | |
262 | } | |
263 | ||
84d727a1 BH |
264 | /* Configure the resource */ |
265 | if (ppc4xx_setup_one_pci_PMM(hose, reg, | |
266 | res->start, | |
267 | res->start - hose->pci_mem_offset, | |
28f65c11 | 268 | resource_size(res), |
84d727a1 BH |
269 | res->flags, |
270 | j) == 0) { | |
271 | j++; | |
272 | ||
273 | /* If the resource PCI address is 0 then we have our | |
274 | * ISA memory hole | |
275 | */ | |
276 | if (res->start == hose->pci_mem_offset) | |
277 | found_isa_hole = 1; | |
c839e0ef | 278 | } |
c839e0ef | 279 | } |
84d727a1 BH |
280 | |
281 | /* Handle ISA memory hole if not already covered */ | |
282 | if (j <= 2 && !found_isa_hole && hose->isa_mem_size) | |
283 | if (ppc4xx_setup_one_pci_PMM(hose, reg, hose->isa_mem_phys, 0, | |
284 | hose->isa_mem_size, 0, j) == 0) | |
285 | printk(KERN_INFO "%s: Legacy ISA memory support enabled\n", | |
286 | hose->dn->full_name); | |
c839e0ef BH |
287 | } |
288 | ||
289 | static void __init ppc4xx_configure_pci_PTMs(struct pci_controller *hose, | |
290 | void __iomem *reg, | |
291 | const struct resource *res) | |
292 | { | |
28f65c11 | 293 | resource_size_t size = resource_size(res); |
c839e0ef BH |
294 | u32 sa; |
295 | ||
296 | /* Calculate window size */ | |
297 | sa = (0xffffffffu << ilog2(size)) | 1; | |
298 | sa |= 0x1; | |
299 | ||
300 | /* RAM is always at 0 local for now */ | |
301 | writel(0, reg + PCIL0_PTM1LA); | |
302 | writel(sa, reg + PCIL0_PTM1MS); | |
303 | ||
304 | /* Map on PCI side */ | |
305 | early_write_config_dword(hose, hose->first_busno, 0, | |
306 | PCI_BASE_ADDRESS_1, res->start); | |
307 | early_write_config_dword(hose, hose->first_busno, 0, | |
308 | PCI_BASE_ADDRESS_2, 0x00000000); | |
309 | early_write_config_word(hose, hose->first_busno, 0, | |
310 | PCI_COMMAND, 0x0006); | |
311 | } | |
312 | ||
5738ec6d BH |
313 | static void __init ppc4xx_probe_pci_bridge(struct device_node *np) |
314 | { | |
315 | /* NYI */ | |
c839e0ef BH |
316 | struct resource rsrc_cfg; |
317 | struct resource rsrc_reg; | |
318 | struct resource dma_window; | |
319 | struct pci_controller *hose = NULL; | |
320 | void __iomem *reg = NULL; | |
321 | const int *bus_range; | |
322 | int primary = 0; | |
323 | ||
5a013fc7 MF |
324 | /* Check if device is enabled */ |
325 | if (!of_device_is_available(np)) { | |
326 | printk(KERN_INFO "%s: Port disabled via device-tree\n", | |
327 | np->full_name); | |
328 | return; | |
329 | } | |
330 | ||
c839e0ef BH |
331 | /* Fetch config space registers address */ |
332 | if (of_address_to_resource(np, 0, &rsrc_cfg)) { | |
5a013fc7 | 333 | printk(KERN_ERR "%s: Can't get PCI config register base !", |
c839e0ef BH |
334 | np->full_name); |
335 | return; | |
336 | } | |
337 | /* Fetch host bridge internal registers address */ | |
338 | if (of_address_to_resource(np, 3, &rsrc_reg)) { | |
339 | printk(KERN_ERR "%s: Can't get PCI internal register base !", | |
340 | np->full_name); | |
341 | return; | |
342 | } | |
343 | ||
344 | /* Check if primary bridge */ | |
345 | if (of_get_property(np, "primary", NULL)) | |
346 | primary = 1; | |
347 | ||
348 | /* Get bus range if any */ | |
349 | bus_range = of_get_property(np, "bus-range", NULL); | |
350 | ||
351 | /* Map registers */ | |
28f65c11 | 352 | reg = ioremap(rsrc_reg.start, resource_size(&rsrc_reg)); |
c839e0ef BH |
353 | if (reg == NULL) { |
354 | printk(KERN_ERR "%s: Can't map registers !", np->full_name); | |
355 | goto fail; | |
356 | } | |
357 | ||
358 | /* Allocate the host controller data structure */ | |
359 | hose = pcibios_alloc_controller(np); | |
360 | if (!hose) | |
361 | goto fail; | |
362 | ||
363 | hose->first_busno = bus_range ? bus_range[0] : 0x0; | |
364 | hose->last_busno = bus_range ? bus_range[1] : 0xff; | |
365 | ||
366 | /* Setup config space */ | |
367 | setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4, 0); | |
368 | ||
369 | /* Disable all windows */ | |
370 | writel(0, reg + PCIL0_PMM0MA); | |
371 | writel(0, reg + PCIL0_PMM1MA); | |
372 | writel(0, reg + PCIL0_PMM2MA); | |
373 | writel(0, reg + PCIL0_PTM1MS); | |
374 | writel(0, reg + PCIL0_PTM2MS); | |
375 | ||
376 | /* Parse outbound mapping resources */ | |
377 | pci_process_bridge_OF_ranges(hose, np, primary); | |
378 | ||
379 | /* Parse inbound mapping resources */ | |
380 | if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0) | |
381 | goto fail; | |
382 | ||
383 | /* Configure outbound ranges POMs */ | |
384 | ppc4xx_configure_pci_PMMs(hose, reg); | |
385 | ||
386 | /* Configure inbound ranges PIMs */ | |
387 | ppc4xx_configure_pci_PTMs(hose, reg, &dma_window); | |
388 | ||
389 | /* We don't need the registers anymore */ | |
390 | iounmap(reg); | |
391 | return; | |
392 | ||
393 | fail: | |
394 | if (hose) | |
395 | pcibios_free_controller(hose); | |
396 | if (reg) | |
397 | iounmap(reg); | |
5738ec6d BH |
398 | } |
399 | ||
400 | /* | |
401 | * 4xx PCI-X part | |
402 | */ | |
403 | ||
84d727a1 BH |
404 | static int __init ppc4xx_setup_one_pcix_POM(struct pci_controller *hose, |
405 | void __iomem *reg, | |
406 | u64 plb_addr, | |
407 | u64 pci_addr, | |
408 | u64 size, | |
409 | unsigned int flags, | |
410 | int index) | |
411 | { | |
412 | u32 lah, lal, pciah, pcial, sa; | |
413 | ||
414 | if (!is_power_of_2(size) || size < 0x1000 || | |
415 | (plb_addr & (size - 1)) != 0) { | |
416 | printk(KERN_WARNING "%s: Resource out of range\n", | |
417 | hose->dn->full_name); | |
418 | return -1; | |
419 | } | |
420 | ||
421 | /* Calculate register values */ | |
422 | lah = RES_TO_U32_HIGH(plb_addr); | |
423 | lal = RES_TO_U32_LOW(plb_addr); | |
424 | pciah = RES_TO_U32_HIGH(pci_addr); | |
425 | pcial = RES_TO_U32_LOW(pci_addr); | |
426 | sa = (0xffffffffu << ilog2(size)) | 0x1; | |
427 | ||
428 | /* Program register values */ | |
429 | if (index == 0) { | |
430 | writel(lah, reg + PCIX0_POM0LAH); | |
431 | writel(lal, reg + PCIX0_POM0LAL); | |
432 | writel(pciah, reg + PCIX0_POM0PCIAH); | |
433 | writel(pcial, reg + PCIX0_POM0PCIAL); | |
434 | writel(sa, reg + PCIX0_POM0SA); | |
435 | } else { | |
436 | writel(lah, reg + PCIX0_POM1LAH); | |
437 | writel(lal, reg + PCIX0_POM1LAL); | |
438 | writel(pciah, reg + PCIX0_POM1PCIAH); | |
439 | writel(pcial, reg + PCIX0_POM1PCIAL); | |
440 | writel(sa, reg + PCIX0_POM1SA); | |
441 | } | |
442 | ||
443 | return 0; | |
444 | } | |
445 | ||
5738ec6d BH |
446 | static void __init ppc4xx_configure_pcix_POMs(struct pci_controller *hose, |
447 | void __iomem *reg) | |
448 | { | |
84d727a1 | 449 | int i, j, found_isa_hole = 0; |
5738ec6d BH |
450 | |
451 | /* Setup outbound memory windows */ | |
452 | for (i = j = 0; i < 3; i++) { | |
453 | struct resource *res = &hose->mem_resources[i]; | |
454 | ||
455 | /* we only care about memory windows */ | |
456 | if (!(res->flags & IORESOURCE_MEM)) | |
457 | continue; | |
458 | if (j > 1) { | |
459 | printk(KERN_WARNING "%s: Too many ranges\n", | |
460 | hose->dn->full_name); | |
461 | break; | |
462 | } | |
463 | ||
84d727a1 BH |
464 | /* Configure the resource */ |
465 | if (ppc4xx_setup_one_pcix_POM(hose, reg, | |
466 | res->start, | |
467 | res->start - hose->pci_mem_offset, | |
28f65c11 | 468 | resource_size(res), |
84d727a1 BH |
469 | res->flags, |
470 | j) == 0) { | |
471 | j++; | |
472 | ||
473 | /* If the resource PCI address is 0 then we have our | |
474 | * ISA memory hole | |
475 | */ | |
476 | if (res->start == hose->pci_mem_offset) | |
477 | found_isa_hole = 1; | |
5738ec6d | 478 | } |
5738ec6d | 479 | } |
84d727a1 BH |
480 | |
481 | /* Handle ISA memory hole if not already covered */ | |
482 | if (j <= 1 && !found_isa_hole && hose->isa_mem_size) | |
483 | if (ppc4xx_setup_one_pcix_POM(hose, reg, hose->isa_mem_phys, 0, | |
484 | hose->isa_mem_size, 0, j) == 0) | |
485 | printk(KERN_INFO "%s: Legacy ISA memory support enabled\n", | |
486 | hose->dn->full_name); | |
5738ec6d BH |
487 | } |
488 | ||
489 | static void __init ppc4xx_configure_pcix_PIMs(struct pci_controller *hose, | |
490 | void __iomem *reg, | |
491 | const struct resource *res, | |
492 | int big_pim, | |
493 | int enable_msi_hole) | |
494 | { | |
28f65c11 | 495 | resource_size_t size = resource_size(res); |
5738ec6d BH |
496 | u32 sa; |
497 | ||
498 | /* RAM is always at 0 */ | |
499 | writel(0x00000000, reg + PCIX0_PIM0LAH); | |
500 | writel(0x00000000, reg + PCIX0_PIM0LAL); | |
501 | ||
502 | /* Calculate window size */ | |
503 | sa = (0xffffffffu << ilog2(size)) | 1; | |
504 | sa |= 0x1; | |
505 | if (res->flags & IORESOURCE_PREFETCH) | |
506 | sa |= 0x2; | |
507 | if (enable_msi_hole) | |
508 | sa |= 0x4; | |
509 | writel(sa, reg + PCIX0_PIM0SA); | |
510 | if (big_pim) | |
511 | writel(0xffffffff, reg + PCIX0_PIM0SAH); | |
512 | ||
513 | /* Map on PCI side */ | |
514 | writel(0x00000000, reg + PCIX0_BAR0H); | |
515 | writel(res->start, reg + PCIX0_BAR0L); | |
516 | writew(0x0006, reg + PCIX0_COMMAND); | |
517 | } | |
518 | ||
519 | static void __init ppc4xx_probe_pcix_bridge(struct device_node *np) | |
520 | { | |
521 | struct resource rsrc_cfg; | |
522 | struct resource rsrc_reg; | |
523 | struct resource dma_window; | |
524 | struct pci_controller *hose = NULL; | |
525 | void __iomem *reg = NULL; | |
526 | const int *bus_range; | |
527 | int big_pim = 0, msi = 0, primary = 0; | |
528 | ||
529 | /* Fetch config space registers address */ | |
530 | if (of_address_to_resource(np, 0, &rsrc_cfg)) { | |
531 | printk(KERN_ERR "%s:Can't get PCI-X config register base !", | |
532 | np->full_name); | |
533 | return; | |
534 | } | |
535 | /* Fetch host bridge internal registers address */ | |
536 | if (of_address_to_resource(np, 3, &rsrc_reg)) { | |
537 | printk(KERN_ERR "%s: Can't get PCI-X internal register base !", | |
538 | np->full_name); | |
539 | return; | |
540 | } | |
541 | ||
542 | /* Check if it supports large PIMs (440GX) */ | |
543 | if (of_get_property(np, "large-inbound-windows", NULL)) | |
544 | big_pim = 1; | |
545 | ||
546 | /* Check if we should enable MSIs inbound hole */ | |
547 | if (of_get_property(np, "enable-msi-hole", NULL)) | |
548 | msi = 1; | |
549 | ||
550 | /* Check if primary bridge */ | |
551 | if (of_get_property(np, "primary", NULL)) | |
552 | primary = 1; | |
553 | ||
554 | /* Get bus range if any */ | |
555 | bus_range = of_get_property(np, "bus-range", NULL); | |
556 | ||
557 | /* Map registers */ | |
28f65c11 | 558 | reg = ioremap(rsrc_reg.start, resource_size(&rsrc_reg)); |
5738ec6d BH |
559 | if (reg == NULL) { |
560 | printk(KERN_ERR "%s: Can't map registers !", np->full_name); | |
561 | goto fail; | |
562 | } | |
563 | ||
564 | /* Allocate the host controller data structure */ | |
565 | hose = pcibios_alloc_controller(np); | |
566 | if (!hose) | |
567 | goto fail; | |
568 | ||
569 | hose->first_busno = bus_range ? bus_range[0] : 0x0; | |
570 | hose->last_busno = bus_range ? bus_range[1] : 0xff; | |
571 | ||
572 | /* Setup config space */ | |
d234b3c3 SO |
573 | setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4, |
574 | PPC_INDIRECT_TYPE_SET_CFG_TYPE); | |
5738ec6d BH |
575 | |
576 | /* Disable all windows */ | |
577 | writel(0, reg + PCIX0_POM0SA); | |
578 | writel(0, reg + PCIX0_POM1SA); | |
579 | writel(0, reg + PCIX0_POM2SA); | |
580 | writel(0, reg + PCIX0_PIM0SA); | |
581 | writel(0, reg + PCIX0_PIM1SA); | |
582 | writel(0, reg + PCIX0_PIM2SA); | |
583 | if (big_pim) { | |
584 | writel(0, reg + PCIX0_PIM0SAH); | |
585 | writel(0, reg + PCIX0_PIM2SAH); | |
586 | } | |
587 | ||
588 | /* Parse outbound mapping resources */ | |
589 | pci_process_bridge_OF_ranges(hose, np, primary); | |
590 | ||
591 | /* Parse inbound mapping resources */ | |
592 | if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0) | |
593 | goto fail; | |
594 | ||
595 | /* Configure outbound ranges POMs */ | |
596 | ppc4xx_configure_pcix_POMs(hose, reg); | |
597 | ||
598 | /* Configure inbound ranges PIMs */ | |
599 | ppc4xx_configure_pcix_PIMs(hose, reg, &dma_window, big_pim, msi); | |
600 | ||
601 | /* We don't need the registers anymore */ | |
602 | iounmap(reg); | |
603 | return; | |
604 | ||
605 | fail: | |
606 | if (hose) | |
607 | pcibios_free_controller(hose); | |
608 | if (reg) | |
609 | iounmap(reg); | |
610 | } | |
611 | ||
a2d2e1ec BH |
612 | #ifdef CONFIG_PPC4xx_PCI_EXPRESS |
613 | ||
5738ec6d BH |
614 | /* |
615 | * 4xx PCI-Express part | |
a2d2e1ec BH |
616 | * |
617 | * We support 3 parts currently based on the compatible property: | |
618 | * | |
accf5ef2 | 619 | * ibm,plb-pciex-440spe |
a2d2e1ec | 620 | * ibm,plb-pciex-405ex |
66b7e504 | 621 | * ibm,plb-pciex-460ex |
a2d2e1ec BH |
622 | * |
623 | * Anything else will be rejected for now as they are all subtly | |
624 | * different unfortunately. | |
625 | * | |
5738ec6d | 626 | */ |
a2d2e1ec | 627 | |
78994e24 | 628 | #define MAX_PCIE_BUS_MAPPED 0x40 |
a2d2e1ec BH |
629 | |
630 | struct ppc4xx_pciex_port | |
631 | { | |
632 | struct pci_controller *hose; | |
633 | struct device_node *node; | |
634 | unsigned int index; | |
635 | int endpoint; | |
035ee428 BH |
636 | int link; |
637 | int has_ibpre; | |
a2d2e1ec BH |
638 | unsigned int sdr_base; |
639 | dcr_host_t dcrs; | |
640 | struct resource cfg_space; | |
641 | struct resource utl_regs; | |
035ee428 | 642 | void __iomem *utl_base; |
a2d2e1ec BH |
643 | }; |
644 | ||
645 | static struct ppc4xx_pciex_port *ppc4xx_pciex_ports; | |
646 | static unsigned int ppc4xx_pciex_port_count; | |
647 | ||
648 | struct ppc4xx_pciex_hwops | |
649 | { | |
650 | int (*core_init)(struct device_node *np); | |
651 | int (*port_init_hw)(struct ppc4xx_pciex_port *port); | |
652 | int (*setup_utl)(struct ppc4xx_pciex_port *port); | |
112d1fe9 | 653 | void (*check_link)(struct ppc4xx_pciex_port *port); |
a2d2e1ec BH |
654 | }; |
655 | ||
656 | static struct ppc4xx_pciex_hwops *ppc4xx_pciex_hwops; | |
657 | ||
658 | #ifdef CONFIG_44x | |
659 | ||
112d1fe9 TB |
660 | static int __init ppc4xx_pciex_wait_on_sdr(struct ppc4xx_pciex_port *port, |
661 | unsigned int sdr_offset, | |
662 | unsigned int mask, | |
663 | unsigned int value, | |
664 | int timeout_ms) | |
665 | { | |
666 | u32 val; | |
667 | ||
668 | while(timeout_ms--) { | |
669 | val = mfdcri(SDR0, port->sdr_base + sdr_offset); | |
670 | if ((val & mask) == value) { | |
671 | pr_debug("PCIE%d: Wait on SDR %x success with tm %d (%08x)\n", | |
672 | port->index, sdr_offset, timeout_ms, val); | |
673 | return 0; | |
674 | } | |
675 | msleep(1); | |
676 | } | |
677 | return -1; | |
678 | } | |
679 | ||
680 | static int __init ppc4xx_pciex_port_reset_sdr(struct ppc4xx_pciex_port *port) | |
681 | { | |
112d1fe9 TB |
682 | /* Wait for reset to complete */ |
683 | if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS, 1 << 20, 0, 10)) { | |
684 | printk(KERN_WARNING "PCIE%d: PGRST failed\n", | |
685 | port->index); | |
686 | return -1; | |
687 | } | |
688 | return 0; | |
689 | } | |
690 | ||
691 | static void __init ppc4xx_pciex_check_link_sdr(struct ppc4xx_pciex_port *port) | |
692 | { | |
a8e616b9 JB |
693 | printk(KERN_INFO "PCIE%d: Checking link...\n", port->index); |
694 | ||
112d1fe9 TB |
695 | /* Check for card presence detect if supported, if not, just wait for |
696 | * link unconditionally. | |
697 | * | |
698 | * note that we don't fail if there is no link, we just filter out | |
699 | * config space accesses. That way, it will be easier to implement | |
700 | * hotplug later on. | |
701 | */ | |
702 | if (!port->has_ibpre || | |
703 | !ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP, | |
704 | 1 << 28, 1 << 28, 100)) { | |
705 | printk(KERN_INFO | |
706 | "PCIE%d: Device detected, waiting for link...\n", | |
707 | port->index); | |
708 | if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP, | |
709 | 0x1000, 0x1000, 2000)) | |
710 | printk(KERN_WARNING | |
711 | "PCIE%d: Link up failed\n", port->index); | |
712 | else { | |
713 | printk(KERN_INFO | |
714 | "PCIE%d: link is up !\n", port->index); | |
715 | port->link = 1; | |
716 | } | |
717 | } else | |
718 | printk(KERN_INFO "PCIE%d: No device detected.\n", port->index); | |
719 | } | |
720 | ||
a2d2e1ec BH |
721 | /* Check various reset bits of the 440SPe PCIe core */ |
722 | static int __init ppc440spe_pciex_check_reset(struct device_node *np) | |
723 | { | |
724 | u32 valPE0, valPE1, valPE2; | |
725 | int err = 0; | |
726 | ||
727 | /* SDR0_PEGPLLLCT1 reset */ | |
728 | if (!(mfdcri(SDR0, PESDR0_PLLLCT1) & 0x01000000)) { | |
729 | /* | |
730 | * the PCIe core was probably already initialised | |
731 | * by firmware - let's re-reset RCSSET regs | |
732 | * | |
733 | * -- Shouldn't we also re-reset the whole thing ? -- BenH | |
734 | */ | |
735 | pr_debug("PCIE: SDR0_PLLLCT1 already reset.\n"); | |
736 | mtdcri(SDR0, PESDR0_440SPE_RCSSET, 0x01010000); | |
737 | mtdcri(SDR0, PESDR1_440SPE_RCSSET, 0x01010000); | |
738 | mtdcri(SDR0, PESDR2_440SPE_RCSSET, 0x01010000); | |
739 | } | |
740 | ||
741 | valPE0 = mfdcri(SDR0, PESDR0_440SPE_RCSSET); | |
742 | valPE1 = mfdcri(SDR0, PESDR1_440SPE_RCSSET); | |
743 | valPE2 = mfdcri(SDR0, PESDR2_440SPE_RCSSET); | |
744 | ||
745 | /* SDR0_PExRCSSET rstgu */ | |
746 | if (!(valPE0 & 0x01000000) || | |
747 | !(valPE1 & 0x01000000) || | |
748 | !(valPE2 & 0x01000000)) { | |
749 | printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstgu error\n"); | |
750 | err = -1; | |
751 | } | |
752 | ||
753 | /* SDR0_PExRCSSET rstdl */ | |
754 | if (!(valPE0 & 0x00010000) || | |
755 | !(valPE1 & 0x00010000) || | |
756 | !(valPE2 & 0x00010000)) { | |
757 | printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstdl error\n"); | |
758 | err = -1; | |
759 | } | |
760 | ||
761 | /* SDR0_PExRCSSET rstpyn */ | |
762 | if ((valPE0 & 0x00001000) || | |
763 | (valPE1 & 0x00001000) || | |
764 | (valPE2 & 0x00001000)) { | |
765 | printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstpyn error\n"); | |
766 | err = -1; | |
767 | } | |
768 | ||
769 | /* SDR0_PExRCSSET hldplb */ | |
770 | if ((valPE0 & 0x10000000) || | |
771 | (valPE1 & 0x10000000) || | |
772 | (valPE2 & 0x10000000)) { | |
773 | printk(KERN_INFO "PCIE: SDR0_PExRCSSET hldplb error\n"); | |
774 | err = -1; | |
775 | } | |
776 | ||
777 | /* SDR0_PExRCSSET rdy */ | |
778 | if ((valPE0 & 0x00100000) || | |
779 | (valPE1 & 0x00100000) || | |
780 | (valPE2 & 0x00100000)) { | |
781 | printk(KERN_INFO "PCIE: SDR0_PExRCSSET rdy error\n"); | |
782 | err = -1; | |
783 | } | |
784 | ||
785 | /* SDR0_PExRCSSET shutdown */ | |
786 | if ((valPE0 & 0x00000100) || | |
787 | (valPE1 & 0x00000100) || | |
788 | (valPE2 & 0x00000100)) { | |
789 | printk(KERN_INFO "PCIE: SDR0_PExRCSSET shutdown error\n"); | |
790 | err = -1; | |
791 | } | |
792 | ||
793 | return err; | |
794 | } | |
795 | ||
796 | /* Global PCIe core initializations for 440SPe core */ | |
797 | static int __init ppc440spe_pciex_core_init(struct device_node *np) | |
798 | { | |
799 | int time_out = 20; | |
800 | ||
801 | /* Set PLL clock receiver to LVPECL */ | |
6e42b21b | 802 | dcri_clrset(SDR0, PESDR0_PLLLCT1, 0, 1 << 28); |
a2d2e1ec BH |
803 | |
804 | /* Shouldn't we do all the calibration stuff etc... here ? */ | |
805 | if (ppc440spe_pciex_check_reset(np)) | |
806 | return -ENXIO; | |
807 | ||
808 | if (!(mfdcri(SDR0, PESDR0_PLLLCT2) & 0x10000)) { | |
809 | printk(KERN_INFO "PCIE: PESDR_PLLCT2 resistance calibration " | |
810 | "failed (0x%08x)\n", | |
811 | mfdcri(SDR0, PESDR0_PLLLCT2)); | |
812 | return -1; | |
813 | } | |
814 | ||
815 | /* De-assert reset of PCIe PLL, wait for lock */ | |
6e42b21b | 816 | dcri_clrset(SDR0, PESDR0_PLLLCT1, 1 << 24, 0); |
a2d2e1ec BH |
817 | udelay(3); |
818 | ||
819 | while (time_out) { | |
820 | if (!(mfdcri(SDR0, PESDR0_PLLLCT3) & 0x10000000)) { | |
821 | time_out--; | |
822 | udelay(1); | |
823 | } else | |
824 | break; | |
825 | } | |
826 | if (!time_out) { | |
827 | printk(KERN_INFO "PCIE: VCO output not locked\n"); | |
828 | return -1; | |
829 | } | |
830 | ||
831 | pr_debug("PCIE initialization OK\n"); | |
832 | ||
833 | return 3; | |
834 | } | |
835 | ||
836 | static int ppc440spe_pciex_init_port_hw(struct ppc4xx_pciex_port *port) | |
837 | { | |
838 | u32 val = 1 << 24; | |
839 | ||
840 | if (port->endpoint) | |
841 | val = PTYPE_LEGACY_ENDPOINT << 20; | |
842 | else | |
843 | val = PTYPE_ROOT_PORT << 20; | |
844 | ||
845 | if (port->index == 0) | |
846 | val |= LNKW_X8 << 12; | |
847 | else | |
848 | val |= LNKW_X4 << 12; | |
849 | ||
850 | mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val); | |
851 | mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x20222222); | |
accf5ef2 | 852 | if (ppc440spe_revA()) |
a2d2e1ec BH |
853 | mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x11000000); |
854 | mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL0SET1, 0x35000000); | |
855 | mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL1SET1, 0x35000000); | |
856 | mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL2SET1, 0x35000000); | |
857 | mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL3SET1, 0x35000000); | |
858 | if (port->index == 0) { | |
859 | mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL4SET1, | |
860 | 0x35000000); | |
861 | mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL5SET1, | |
862 | 0x35000000); | |
863 | mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL6SET1, | |
864 | 0x35000000); | |
865 | mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL7SET1, | |
866 | 0x35000000); | |
867 | } | |
6e42b21b VB |
868 | dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, |
869 | (1 << 24) | (1 << 16), 1 << 12); | |
a2d2e1ec | 870 | |
112d1fe9 | 871 | return ppc4xx_pciex_port_reset_sdr(port); |
a2d2e1ec BH |
872 | } |
873 | ||
035ee428 BH |
874 | static int ppc440speA_pciex_init_port_hw(struct ppc4xx_pciex_port *port) |
875 | { | |
876 | return ppc440spe_pciex_init_port_hw(port); | |
877 | } | |
878 | ||
879 | static int ppc440speB_pciex_init_port_hw(struct ppc4xx_pciex_port *port) | |
a2d2e1ec | 880 | { |
035ee428 BH |
881 | int rc = ppc440spe_pciex_init_port_hw(port); |
882 | ||
883 | port->has_ibpre = 1; | |
884 | ||
885 | return rc; | |
886 | } | |
a2d2e1ec | 887 | |
035ee428 BH |
888 | static int ppc440speA_pciex_init_utl(struct ppc4xx_pciex_port *port) |
889 | { | |
a2d2e1ec BH |
890 | /* XXX Check what that value means... I hate magic */ |
891 | dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x68782800); | |
892 | ||
a2d2e1ec BH |
893 | /* |
894 | * Set buffer allocations and then assert VRB and TXE. | |
895 | */ | |
035ee428 BH |
896 | out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000); |
897 | out_be32(port->utl_base + PEUTL_INTR, 0x02000000); | |
898 | out_be32(port->utl_base + PEUTL_OPDBSZ, 0x10000000); | |
899 | out_be32(port->utl_base + PEUTL_PBBSZ, 0x53000000); | |
900 | out_be32(port->utl_base + PEUTL_IPHBSZ, 0x08000000); | |
901 | out_be32(port->utl_base + PEUTL_IPDBSZ, 0x10000000); | |
902 | out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000); | |
903 | out_be32(port->utl_base + PEUTL_PCTL, 0x80800066); | |
a2d2e1ec | 904 | |
035ee428 BH |
905 | return 0; |
906 | } | |
907 | ||
908 | static int ppc440speB_pciex_init_utl(struct ppc4xx_pciex_port *port) | |
909 | { | |
910 | /* Report CRS to the operating system */ | |
911 | out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000); | |
a2d2e1ec BH |
912 | |
913 | return 0; | |
914 | } | |
915 | ||
916 | static struct ppc4xx_pciex_hwops ppc440speA_pcie_hwops __initdata = | |
917 | { | |
918 | .core_init = ppc440spe_pciex_core_init, | |
035ee428 | 919 | .port_init_hw = ppc440speA_pciex_init_port_hw, |
a2d2e1ec | 920 | .setup_utl = ppc440speA_pciex_init_utl, |
112d1fe9 | 921 | .check_link = ppc4xx_pciex_check_link_sdr, |
a2d2e1ec BH |
922 | }; |
923 | ||
924 | static struct ppc4xx_pciex_hwops ppc440speB_pcie_hwops __initdata = | |
925 | { | |
926 | .core_init = ppc440spe_pciex_core_init, | |
035ee428 BH |
927 | .port_init_hw = ppc440speB_pciex_init_port_hw, |
928 | .setup_utl = ppc440speB_pciex_init_utl, | |
112d1fe9 | 929 | .check_link = ppc4xx_pciex_check_link_sdr, |
a2d2e1ec BH |
930 | }; |
931 | ||
66b7e504 SR |
932 | static int __init ppc460ex_pciex_core_init(struct device_node *np) |
933 | { | |
934 | /* Nothing to do, return 2 ports */ | |
935 | return 2; | |
936 | } | |
937 | ||
938 | static int ppc460ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port) | |
939 | { | |
940 | u32 val; | |
941 | u32 utlset1; | |
942 | ||
5f91925c | 943 | if (port->endpoint) |
66b7e504 | 944 | val = PTYPE_LEGACY_ENDPOINT << 20; |
5f91925c | 945 | else |
66b7e504 | 946 | val = PTYPE_ROOT_PORT << 20; |
66b7e504 SR |
947 | |
948 | if (port->index == 0) { | |
949 | val |= LNKW_X1 << 12; | |
5f91925c | 950 | utlset1 = 0x20000000; |
66b7e504 SR |
951 | } else { |
952 | val |= LNKW_X4 << 12; | |
5f91925c | 953 | utlset1 = 0x20101101; |
66b7e504 SR |
954 | } |
955 | ||
956 | mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val); | |
957 | mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, utlset1); | |
958 | mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01210000); | |
959 | ||
960 | switch (port->index) { | |
961 | case 0: | |
962 | mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230); | |
e30c9875 | 963 | mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130); |
66b7e504 SR |
964 | mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006); |
965 | ||
966 | mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST,0x10000000); | |
967 | break; | |
968 | ||
969 | case 1: | |
970 | mtdcri(SDR0, PESDR1_460EX_L0CDRCTL, 0x00003230); | |
971 | mtdcri(SDR0, PESDR1_460EX_L1CDRCTL, 0x00003230); | |
972 | mtdcri(SDR0, PESDR1_460EX_L2CDRCTL, 0x00003230); | |
973 | mtdcri(SDR0, PESDR1_460EX_L3CDRCTL, 0x00003230); | |
e30c9875 TM |
974 | mtdcri(SDR0, PESDR1_460EX_L0DRV, 0x00000130); |
975 | mtdcri(SDR0, PESDR1_460EX_L1DRV, 0x00000130); | |
976 | mtdcri(SDR0, PESDR1_460EX_L2DRV, 0x00000130); | |
977 | mtdcri(SDR0, PESDR1_460EX_L3DRV, 0x00000130); | |
66b7e504 SR |
978 | mtdcri(SDR0, PESDR1_460EX_L0CLK, 0x00000006); |
979 | mtdcri(SDR0, PESDR1_460EX_L1CLK, 0x00000006); | |
980 | mtdcri(SDR0, PESDR1_460EX_L2CLK, 0x00000006); | |
981 | mtdcri(SDR0, PESDR1_460EX_L3CLK, 0x00000006); | |
982 | ||
983 | mtdcri(SDR0, PESDR1_460EX_PHY_CTL_RST,0x10000000); | |
984 | break; | |
985 | } | |
986 | ||
987 | mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, | |
988 | mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) | | |
989 | (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN)); | |
990 | ||
991 | /* Poll for PHY reset */ | |
992 | /* XXX FIXME add timeout */ | |
993 | switch (port->index) { | |
994 | case 0: | |
995 | while (!(mfdcri(SDR0, PESDR0_460EX_RSTSTA) & 0x1)) | |
996 | udelay(10); | |
997 | break; | |
998 | case 1: | |
999 | while (!(mfdcri(SDR0, PESDR1_460EX_RSTSTA) & 0x1)) | |
1000 | udelay(10); | |
1001 | break; | |
1002 | } | |
1003 | ||
1004 | mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, | |
1005 | (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) & | |
1006 | ~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) | | |
1007 | PESDRx_RCSSET_RSTPYN); | |
1008 | ||
1009 | port->has_ibpre = 1; | |
1010 | ||
112d1fe9 | 1011 | return ppc4xx_pciex_port_reset_sdr(port); |
66b7e504 SR |
1012 | } |
1013 | ||
1014 | static int ppc460ex_pciex_init_utl(struct ppc4xx_pciex_port *port) | |
1015 | { | |
1016 | dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0); | |
1017 | ||
1018 | /* | |
1019 | * Set buffer allocations and then assert VRB and TXE. | |
1020 | */ | |
1021 | out_be32(port->utl_base + PEUTL_PBCTL, 0x0800000c); | |
1022 | out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000); | |
1023 | out_be32(port->utl_base + PEUTL_INTR, 0x02000000); | |
1024 | out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000); | |
1025 | out_be32(port->utl_base + PEUTL_PBBSZ, 0x00000000); | |
1026 | out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000); | |
1027 | out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000); | |
1028 | out_be32(port->utl_base + PEUTL_RCIRQEN,0x00f00000); | |
1029 | out_be32(port->utl_base + PEUTL_PCTL, 0x80800066); | |
1030 | ||
1031 | return 0; | |
1032 | } | |
1033 | ||
1034 | static struct ppc4xx_pciex_hwops ppc460ex_pcie_hwops __initdata = | |
1035 | { | |
1036 | .core_init = ppc460ex_pciex_core_init, | |
1037 | .port_init_hw = ppc460ex_pciex_init_port_hw, | |
1038 | .setup_utl = ppc460ex_pciex_init_utl, | |
112d1fe9 | 1039 | .check_link = ppc4xx_pciex_check_link_sdr, |
66b7e504 SR |
1040 | }; |
1041 | ||
e2efc09e TM |
1042 | static int __init ppc460sx_pciex_core_init(struct device_node *np) |
1043 | { | |
1044 | /* HSS drive amplitude */ | |
1045 | mtdcri(SDR0, PESDR0_460SX_HSSL0DAMP, 0xB9843211); | |
1046 | mtdcri(SDR0, PESDR0_460SX_HSSL1DAMP, 0xB9843211); | |
1047 | mtdcri(SDR0, PESDR0_460SX_HSSL2DAMP, 0xB9843211); | |
1048 | mtdcri(SDR0, PESDR0_460SX_HSSL3DAMP, 0xB9843211); | |
1049 | mtdcri(SDR0, PESDR0_460SX_HSSL4DAMP, 0xB9843211); | |
1050 | mtdcri(SDR0, PESDR0_460SX_HSSL5DAMP, 0xB9843211); | |
1051 | mtdcri(SDR0, PESDR0_460SX_HSSL6DAMP, 0xB9843211); | |
1052 | mtdcri(SDR0, PESDR0_460SX_HSSL7DAMP, 0xB9843211); | |
1053 | ||
1054 | mtdcri(SDR0, PESDR1_460SX_HSSL0DAMP, 0xB9843211); | |
1055 | mtdcri(SDR0, PESDR1_460SX_HSSL1DAMP, 0xB9843211); | |
1056 | mtdcri(SDR0, PESDR1_460SX_HSSL2DAMP, 0xB9843211); | |
1057 | mtdcri(SDR0, PESDR1_460SX_HSSL3DAMP, 0xB9843211); | |
1058 | ||
1059 | mtdcri(SDR0, PESDR2_460SX_HSSL0DAMP, 0xB9843211); | |
1060 | mtdcri(SDR0, PESDR2_460SX_HSSL1DAMP, 0xB9843211); | |
1061 | mtdcri(SDR0, PESDR2_460SX_HSSL2DAMP, 0xB9843211); | |
1062 | mtdcri(SDR0, PESDR2_460SX_HSSL3DAMP, 0xB9843211); | |
1063 | ||
1064 | /* HSS TX pre-emphasis */ | |
1065 | mtdcri(SDR0, PESDR0_460SX_HSSL0COEFA, 0xDCB98987); | |
1066 | mtdcri(SDR0, PESDR0_460SX_HSSL1COEFA, 0xDCB98987); | |
1067 | mtdcri(SDR0, PESDR0_460SX_HSSL2COEFA, 0xDCB98987); | |
1068 | mtdcri(SDR0, PESDR0_460SX_HSSL3COEFA, 0xDCB98987); | |
1069 | mtdcri(SDR0, PESDR0_460SX_HSSL4COEFA, 0xDCB98987); | |
1070 | mtdcri(SDR0, PESDR0_460SX_HSSL5COEFA, 0xDCB98987); | |
1071 | mtdcri(SDR0, PESDR0_460SX_HSSL6COEFA, 0xDCB98987); | |
1072 | mtdcri(SDR0, PESDR0_460SX_HSSL7COEFA, 0xDCB98987); | |
1073 | ||
1074 | mtdcri(SDR0, PESDR1_460SX_HSSL0COEFA, 0xDCB98987); | |
1075 | mtdcri(SDR0, PESDR1_460SX_HSSL1COEFA, 0xDCB98987); | |
1076 | mtdcri(SDR0, PESDR1_460SX_HSSL2COEFA, 0xDCB98987); | |
1077 | mtdcri(SDR0, PESDR1_460SX_HSSL3COEFA, 0xDCB98987); | |
1078 | ||
1079 | mtdcri(SDR0, PESDR2_460SX_HSSL0COEFA, 0xDCB98987); | |
1080 | mtdcri(SDR0, PESDR2_460SX_HSSL1COEFA, 0xDCB98987); | |
1081 | mtdcri(SDR0, PESDR2_460SX_HSSL2COEFA, 0xDCB98987); | |
1082 | mtdcri(SDR0, PESDR2_460SX_HSSL3COEFA, 0xDCB98987); | |
1083 | ||
1084 | /* HSS TX calibration control */ | |
1085 | mtdcri(SDR0, PESDR0_460SX_HSSL1CALDRV, 0x22222222); | |
1086 | mtdcri(SDR0, PESDR1_460SX_HSSL1CALDRV, 0x22220000); | |
1087 | mtdcri(SDR0, PESDR2_460SX_HSSL1CALDRV, 0x22220000); | |
1088 | ||
1089 | /* HSS TX slew control */ | |
1090 | mtdcri(SDR0, PESDR0_460SX_HSSSLEW, 0xFFFFFFFF); | |
1091 | mtdcri(SDR0, PESDR1_460SX_HSSSLEW, 0xFFFF0000); | |
1092 | mtdcri(SDR0, PESDR2_460SX_HSSSLEW, 0xFFFF0000); | |
1093 | ||
1094 | udelay(100); | |
1095 | ||
1096 | /* De-assert PLLRESET */ | |
1097 | dcri_clrset(SDR0, PESDR0_PLLLCT2, 0x00000100, 0); | |
1098 | ||
1099 | /* Reset DL, UTL, GPL before configuration */ | |
1100 | mtdcri(SDR0, PESDR0_460SX_RCSSET, | |
1101 | PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU); | |
1102 | mtdcri(SDR0, PESDR1_460SX_RCSSET, | |
1103 | PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU); | |
1104 | mtdcri(SDR0, PESDR2_460SX_RCSSET, | |
1105 | PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU); | |
1106 | ||
1107 | udelay(100); | |
1108 | ||
1109 | /* | |
1110 | * If bifurcation is not enabled, u-boot would have disabled the | |
1111 | * third PCIe port | |
1112 | */ | |
1113 | if (((mfdcri(SDR0, PESDR1_460SX_HSSCTLSET) & 0x00000001) == | |
1114 | 0x00000001)) { | |
1115 | printk(KERN_INFO "PCI: PCIE bifurcation setup successfully.\n"); | |
1116 | printk(KERN_INFO "PCI: Total 3 PCIE ports are present\n"); | |
1117 | return 3; | |
1118 | } | |
1119 | ||
1120 | printk(KERN_INFO "PCI: Total 2 PCIE ports are present\n"); | |
1121 | return 2; | |
1122 | } | |
1123 | ||
1124 | static int ppc460sx_pciex_init_port_hw(struct ppc4xx_pciex_port *port) | |
1125 | { | |
1126 | ||
1127 | if (port->endpoint) | |
1128 | dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2, | |
1129 | 0x01000000, 0); | |
1130 | else | |
1131 | dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2, | |
1132 | 0, 0x01000000); | |
1133 | ||
1134 | /*Gen-1*/ | |
1135 | mtdcri(SDR0, port->sdr_base + PESDRn_460SX_RCEI, 0x08000000); | |
1136 | ||
1137 | dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, | |
1138 | (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL), | |
1139 | PESDRx_RCSSET_RSTPYN); | |
1140 | ||
1141 | port->has_ibpre = 1; | |
1142 | ||
112d1fe9 | 1143 | return ppc4xx_pciex_port_reset_sdr(port); |
e2efc09e TM |
1144 | } |
1145 | ||
1146 | static int ppc460sx_pciex_init_utl(struct ppc4xx_pciex_port *port) | |
1147 | { | |
1148 | /* Max 128 Bytes */ | |
1149 | out_be32 (port->utl_base + PEUTL_PBBSZ, 0x00000000); | |
1150 | return 0; | |
1151 | } | |
1152 | ||
1153 | static struct ppc4xx_pciex_hwops ppc460sx_pcie_hwops __initdata = { | |
1154 | .core_init = ppc460sx_pciex_core_init, | |
1155 | .port_init_hw = ppc460sx_pciex_init_port_hw, | |
1156 | .setup_utl = ppc460sx_pciex_init_utl, | |
112d1fe9 | 1157 | .check_link = ppc4xx_pciex_check_link_sdr, |
e2efc09e TM |
1158 | }; |
1159 | ||
a2d2e1ec BH |
1160 | #endif /* CONFIG_44x */ |
1161 | ||
1162 | #ifdef CONFIG_40x | |
1163 | ||
1164 | static int __init ppc405ex_pciex_core_init(struct device_node *np) | |
1165 | { | |
1166 | /* Nothing to do, return 2 ports */ | |
1167 | return 2; | |
1168 | } | |
1169 | ||
1170 | static void ppc405ex_pcie_phy_reset(struct ppc4xx_pciex_port *port) | |
1171 | { | |
1172 | /* Assert the PE0_PHY reset */ | |
1173 | mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01010000); | |
1174 | msleep(1); | |
1175 | ||
1176 | /* deassert the PE0_hotreset */ | |
1177 | if (port->endpoint) | |
1178 | mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01111000); | |
1179 | else | |
1180 | mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01101000); | |
1181 | ||
1182 | /* poll for phy !reset */ | |
1183 | /* XXX FIXME add timeout */ | |
1184 | while (!(mfdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSTA) & 0x00001000)) | |
1185 | ; | |
1186 | ||
1187 | /* deassert the PE0_gpl_utl_reset */ | |
1188 | mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x00101000); | |
1189 | } | |
1190 | ||
1191 | static int ppc405ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port) | |
1192 | { | |
1193 | u32 val; | |
1194 | ||
1195 | if (port->endpoint) | |
1196 | val = PTYPE_LEGACY_ENDPOINT; | |
1197 | else | |
1198 | val = PTYPE_ROOT_PORT; | |
1199 | ||
1200 | mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, | |
1201 | 1 << 24 | val << 20 | LNKW_X1 << 12); | |
1202 | ||
1203 | mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000); | |
1204 | mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000); | |
1205 | mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET1, 0x720F0000); | |
1206 | mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET2, 0x70600003); | |
1207 | ||
1208 | /* | |
1209 | * Only reset the PHY when no link is currently established. | |
1210 | * This is for the Atheros PCIe board which has problems to establish | |
1211 | * the link (again) after this PHY reset. All other currently tested | |
1212 | * PCIe boards don't show this problem. | |
1213 | * This has to be re-tested and fixed in a later release! | |
1214 | */ | |
a2d2e1ec BH |
1215 | val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP); |
1216 | if (!(val & 0x00001000)) | |
1217 | ppc405ex_pcie_phy_reset(port); | |
a2d2e1ec BH |
1218 | |
1219 | dcr_write(port->dcrs, DCRO_PEGPL_CFG, 0x10000000); /* guarded on */ | |
1220 | ||
55aaf6ec SR |
1221 | port->has_ibpre = 1; |
1222 | ||
112d1fe9 | 1223 | return ppc4xx_pciex_port_reset_sdr(port); |
a2d2e1ec BH |
1224 | } |
1225 | ||
1226 | static int ppc405ex_pciex_init_utl(struct ppc4xx_pciex_port *port) | |
1227 | { | |
a2d2e1ec BH |
1228 | dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0); |
1229 | ||
a2d2e1ec BH |
1230 | /* |
1231 | * Set buffer allocations and then assert VRB and TXE. | |
1232 | */ | |
035ee428 BH |
1233 | out_be32(port->utl_base + PEUTL_OUTTR, 0x02000000); |
1234 | out_be32(port->utl_base + PEUTL_INTR, 0x02000000); | |
1235 | out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000); | |
1236 | out_be32(port->utl_base + PEUTL_PBBSZ, 0x21000000); | |
1237 | out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000); | |
1238 | out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000); | |
1239 | out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000); | |
1240 | out_be32(port->utl_base + PEUTL_PCTL, 0x80800066); | |
a2d2e1ec | 1241 | |
035ee428 | 1242 | out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000); |
a2d2e1ec BH |
1243 | |
1244 | return 0; | |
1245 | } | |
1246 | ||
1247 | static struct ppc4xx_pciex_hwops ppc405ex_pcie_hwops __initdata = | |
1248 | { | |
1249 | .core_init = ppc405ex_pciex_core_init, | |
1250 | .port_init_hw = ppc405ex_pciex_init_port_hw, | |
1251 | .setup_utl = ppc405ex_pciex_init_utl, | |
112d1fe9 | 1252 | .check_link = ppc4xx_pciex_check_link_sdr, |
a2d2e1ec BH |
1253 | }; |
1254 | ||
1255 | #endif /* CONFIG_40x */ | |
1256 | ||
a2d2e1ec BH |
1257 | /* Check that the core has been initied and if not, do it */ |
1258 | static int __init ppc4xx_pciex_check_core_init(struct device_node *np) | |
1259 | { | |
1260 | static int core_init; | |
1261 | int count = -ENODEV; | |
1262 | ||
1263 | if (core_init++) | |
1264 | return 0; | |
1265 | ||
1266 | #ifdef CONFIG_44x | |
accf5ef2 SR |
1267 | if (of_device_is_compatible(np, "ibm,plb-pciex-440spe")) { |
1268 | if (ppc440spe_revA()) | |
1269 | ppc4xx_pciex_hwops = &ppc440speA_pcie_hwops; | |
1270 | else | |
1271 | ppc4xx_pciex_hwops = &ppc440speB_pcie_hwops; | |
1272 | } | |
66b7e504 SR |
1273 | if (of_device_is_compatible(np, "ibm,plb-pciex-460ex")) |
1274 | ppc4xx_pciex_hwops = &ppc460ex_pcie_hwops; | |
e2efc09e TM |
1275 | if (of_device_is_compatible(np, "ibm,plb-pciex-460sx")) |
1276 | ppc4xx_pciex_hwops = &ppc460sx_pcie_hwops; | |
a2d2e1ec BH |
1277 | #endif /* CONFIG_44x */ |
1278 | #ifdef CONFIG_40x | |
1279 | if (of_device_is_compatible(np, "ibm,plb-pciex-405ex")) | |
1280 | ppc4xx_pciex_hwops = &ppc405ex_pcie_hwops; | |
1281 | #endif | |
1282 | if (ppc4xx_pciex_hwops == NULL) { | |
1283 | printk(KERN_WARNING "PCIE: unknown host type %s\n", | |
1284 | np->full_name); | |
1285 | return -ENODEV; | |
1286 | } | |
1287 | ||
1288 | count = ppc4xx_pciex_hwops->core_init(np); | |
1289 | if (count > 0) { | |
1290 | ppc4xx_pciex_ports = | |
1291 | kzalloc(count * sizeof(struct ppc4xx_pciex_port), | |
1292 | GFP_KERNEL); | |
1293 | if (ppc4xx_pciex_ports) { | |
1294 | ppc4xx_pciex_port_count = count; | |
1295 | return 0; | |
1296 | } | |
1297 | printk(KERN_WARNING "PCIE: failed to allocate ports array\n"); | |
1298 | return -ENOMEM; | |
1299 | } | |
1300 | return -ENODEV; | |
1301 | } | |
1302 | ||
1303 | static void __init ppc4xx_pciex_port_init_mapping(struct ppc4xx_pciex_port *port) | |
1304 | { | |
1305 | /* We map PCI Express configuration based on the reg property */ | |
1306 | dcr_write(port->dcrs, DCRO_PEGPL_CFGBAH, | |
1307 | RES_TO_U32_HIGH(port->cfg_space.start)); | |
1308 | dcr_write(port->dcrs, DCRO_PEGPL_CFGBAL, | |
1309 | RES_TO_U32_LOW(port->cfg_space.start)); | |
1310 | ||
1311 | /* XXX FIXME: Use size from reg property. For now, map 512M */ | |
1312 | dcr_write(port->dcrs, DCRO_PEGPL_CFGMSK, 0xe0000001); | |
1313 | ||
1314 | /* We map UTL registers based on the reg property */ | |
1315 | dcr_write(port->dcrs, DCRO_PEGPL_REGBAH, | |
1316 | RES_TO_U32_HIGH(port->utl_regs.start)); | |
1317 | dcr_write(port->dcrs, DCRO_PEGPL_REGBAL, | |
1318 | RES_TO_U32_LOW(port->utl_regs.start)); | |
1319 | ||
1320 | /* XXX FIXME: Use size from reg property */ | |
1321 | dcr_write(port->dcrs, DCRO_PEGPL_REGMSK, 0x00007001); | |
1322 | ||
1323 | /* Disable all other outbound windows */ | |
1324 | dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, 0); | |
1325 | dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, 0); | |
1326 | dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, 0); | |
1327 | dcr_write(port->dcrs, DCRO_PEGPL_MSGMSK, 0); | |
1328 | } | |
1329 | ||
035ee428 BH |
1330 | static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port) |
1331 | { | |
1332 | int rc = 0; | |
a2d2e1ec BH |
1333 | |
1334 | /* Init HW */ | |
1335 | if (ppc4xx_pciex_hwops->port_init_hw) | |
1336 | rc = ppc4xx_pciex_hwops->port_init_hw(port); | |
1337 | if (rc != 0) | |
1338 | return rc; | |
1339 | ||
112d1fe9 TB |
1340 | if (ppc4xx_pciex_hwops->check_link) |
1341 | ppc4xx_pciex_hwops->check_link(port); | |
a2d2e1ec BH |
1342 | |
1343 | /* | |
1344 | * Initialize mapping: disable all regions and configure | |
1345 | * CFG and REG regions based on resources in the device tree | |
1346 | */ | |
1347 | ppc4xx_pciex_port_init_mapping(port); | |
1348 | ||
1349 | /* | |
035ee428 BH |
1350 | * Map UTL |
1351 | */ | |
1352 | port->utl_base = ioremap(port->utl_regs.start, 0x100); | |
1353 | BUG_ON(port->utl_base == NULL); | |
1354 | ||
1355 | /* | |
1356 | * Setup UTL registers --BenH. | |
a2d2e1ec BH |
1357 | */ |
1358 | if (ppc4xx_pciex_hwops->setup_utl) | |
1359 | ppc4xx_pciex_hwops->setup_utl(port); | |
1360 | ||
1361 | /* | |
1362 | * Check for VC0 active and assert RDY. | |
1363 | */ | |
112d1fe9 TB |
1364 | if (port->sdr_base) { |
1365 | if (port->link && | |
1366 | ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS, | |
1367 | 1 << 16, 1 << 16, 5000)) { | |
1368 | printk(KERN_INFO "PCIE%d: VC0 not active\n", port->index); | |
1369 | port->link = 0; | |
1370 | } | |
1371 | ||
1372 | dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20); | |
a2d2e1ec | 1373 | } |
035ee428 | 1374 | |
a2d2e1ec BH |
1375 | msleep(100); |
1376 | ||
1377 | return 0; | |
1378 | } | |
1379 | ||
1380 | static int ppc4xx_pciex_validate_bdf(struct ppc4xx_pciex_port *port, | |
1381 | struct pci_bus *bus, | |
1382 | unsigned int devfn) | |
1383 | { | |
1384 | static int message; | |
1385 | ||
1386 | /* Endpoint can not generate upstream(remote) config cycles */ | |
1387 | if (port->endpoint && bus->number != port->hose->first_busno) | |
1388 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1389 | ||
1390 | /* Check we are within the mapped range */ | |
1391 | if (bus->number > port->hose->last_busno) { | |
1392 | if (!message) { | |
1393 | printk(KERN_WARNING "Warning! Probing bus %u" | |
1394 | " out of range !\n", bus->number); | |
1395 | message++; | |
1396 | } | |
1397 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1398 | } | |
1399 | ||
1400 | /* The root complex has only one device / function */ | |
1401 | if (bus->number == port->hose->first_busno && devfn != 0) | |
1402 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1403 | ||
1404 | /* The other side of the RC has only one device as well */ | |
1405 | if (bus->number == (port->hose->first_busno + 1) && | |
1406 | PCI_SLOT(devfn) != 0) | |
1407 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1408 | ||
035ee428 BH |
1409 | /* Check if we have a link */ |
1410 | if ((bus->number != port->hose->first_busno) && !port->link) | |
1411 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1412 | ||
a2d2e1ec BH |
1413 | return 0; |
1414 | } | |
1415 | ||
1416 | static void __iomem *ppc4xx_pciex_get_config_base(struct ppc4xx_pciex_port *port, | |
1417 | struct pci_bus *bus, | |
1418 | unsigned int devfn) | |
1419 | { | |
1420 | int relbus; | |
1421 | ||
1422 | /* Remove the casts when we finally remove the stupid volatile | |
1423 | * in struct pci_controller | |
1424 | */ | |
1425 | if (bus->number == port->hose->first_busno) | |
1426 | return (void __iomem *)port->hose->cfg_addr; | |
1427 | ||
1428 | relbus = bus->number - (port->hose->first_busno + 1); | |
1429 | return (void __iomem *)port->hose->cfg_data + | |
1430 | ((relbus << 20) | (devfn << 12)); | |
1431 | } | |
1432 | ||
1433 | static int ppc4xx_pciex_read_config(struct pci_bus *bus, unsigned int devfn, | |
1434 | int offset, int len, u32 *val) | |
1435 | { | |
f159edae | 1436 | struct pci_controller *hose = pci_bus_to_host(bus); |
a2d2e1ec BH |
1437 | struct ppc4xx_pciex_port *port = |
1438 | &ppc4xx_pciex_ports[hose->indirect_type]; | |
1439 | void __iomem *addr; | |
1440 | u32 gpl_cfg; | |
1441 | ||
1442 | BUG_ON(hose != port->hose); | |
1443 | ||
1444 | if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0) | |
1445 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1446 | ||
1447 | addr = ppc4xx_pciex_get_config_base(port, bus, devfn); | |
1448 | ||
1449 | /* | |
1450 | * Reading from configuration space of non-existing device can | |
1451 | * generate transaction errors. For the read duration we suppress | |
1452 | * assertion of machine check exceptions to avoid those. | |
1453 | */ | |
1454 | gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG); | |
1455 | dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA); | |
1456 | ||
035ee428 BH |
1457 | /* Make sure no CRS is recorded */ |
1458 | out_be32(port->utl_base + PEUTL_RCSTA, 0x00040000); | |
1459 | ||
a2d2e1ec BH |
1460 | switch (len) { |
1461 | case 1: | |
1462 | *val = in_8((u8 *)(addr + offset)); | |
1463 | break; | |
1464 | case 2: | |
1465 | *val = in_le16((u16 *)(addr + offset)); | |
1466 | break; | |
1467 | default: | |
1468 | *val = in_le32((u32 *)(addr + offset)); | |
1469 | break; | |
1470 | } | |
1471 | ||
1472 | pr_debug("pcie-config-read: bus=%3d [%3d..%3d] devfn=0x%04x" | |
1473 | " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n", | |
1474 | bus->number, hose->first_busno, hose->last_busno, | |
1475 | devfn, offset, len, addr + offset, *val); | |
1476 | ||
035ee428 BH |
1477 | /* Check for CRS (440SPe rev B does that for us but heh ..) */ |
1478 | if (in_be32(port->utl_base + PEUTL_RCSTA) & 0x00040000) { | |
1479 | pr_debug("Got CRS !\n"); | |
1480 | if (len != 4 || offset != 0) | |
1481 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1482 | *val = 0xffff0001; | |
1483 | } | |
1484 | ||
a2d2e1ec BH |
1485 | dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg); |
1486 | ||
1487 | return PCIBIOS_SUCCESSFUL; | |
1488 | } | |
1489 | ||
1490 | static int ppc4xx_pciex_write_config(struct pci_bus *bus, unsigned int devfn, | |
1491 | int offset, int len, u32 val) | |
1492 | { | |
f159edae | 1493 | struct pci_controller *hose = pci_bus_to_host(bus); |
a2d2e1ec BH |
1494 | struct ppc4xx_pciex_port *port = |
1495 | &ppc4xx_pciex_ports[hose->indirect_type]; | |
1496 | void __iomem *addr; | |
1497 | u32 gpl_cfg; | |
1498 | ||
1499 | if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0) | |
1500 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1501 | ||
1502 | addr = ppc4xx_pciex_get_config_base(port, bus, devfn); | |
1503 | ||
1504 | /* | |
1505 | * Reading from configuration space of non-existing device can | |
1506 | * generate transaction errors. For the read duration we suppress | |
1507 | * assertion of machine check exceptions to avoid those. | |
1508 | */ | |
1509 | gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG); | |
1510 | dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA); | |
1511 | ||
1512 | pr_debug("pcie-config-write: bus=%3d [%3d..%3d] devfn=0x%04x" | |
1513 | " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n", | |
1514 | bus->number, hose->first_busno, hose->last_busno, | |
1515 | devfn, offset, len, addr + offset, val); | |
1516 | ||
1517 | switch (len) { | |
1518 | case 1: | |
1519 | out_8((u8 *)(addr + offset), val); | |
1520 | break; | |
1521 | case 2: | |
1522 | out_le16((u16 *)(addr + offset), val); | |
1523 | break; | |
1524 | default: | |
1525 | out_le32((u32 *)(addr + offset), val); | |
1526 | break; | |
1527 | } | |
1528 | ||
1529 | dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg); | |
1530 | ||
1531 | return PCIBIOS_SUCCESSFUL; | |
1532 | } | |
1533 | ||
1534 | static struct pci_ops ppc4xx_pciex_pci_ops = | |
1535 | { | |
1536 | .read = ppc4xx_pciex_read_config, | |
1537 | .write = ppc4xx_pciex_write_config, | |
1538 | }; | |
1539 | ||
84d727a1 BH |
1540 | static int __init ppc4xx_setup_one_pciex_POM(struct ppc4xx_pciex_port *port, |
1541 | struct pci_controller *hose, | |
1542 | void __iomem *mbase, | |
1543 | u64 plb_addr, | |
1544 | u64 pci_addr, | |
1545 | u64 size, | |
1546 | unsigned int flags, | |
1547 | int index) | |
1548 | { | |
1549 | u32 lah, lal, pciah, pcial, sa; | |
1550 | ||
1551 | if (!is_power_of_2(size) || | |
1552 | (index < 2 && size < 0x100000) || | |
1553 | (index == 2 && size < 0x100) || | |
1554 | (plb_addr & (size - 1)) != 0) { | |
1555 | printk(KERN_WARNING "%s: Resource out of range\n", | |
1556 | hose->dn->full_name); | |
1557 | return -1; | |
1558 | } | |
1559 | ||
1560 | /* Calculate register values */ | |
1561 | lah = RES_TO_U32_HIGH(plb_addr); | |
1562 | lal = RES_TO_U32_LOW(plb_addr); | |
1563 | pciah = RES_TO_U32_HIGH(pci_addr); | |
1564 | pcial = RES_TO_U32_LOW(pci_addr); | |
1565 | sa = (0xffffffffu << ilog2(size)) | 0x1; | |
1566 | ||
1567 | /* Program register values */ | |
1568 | switch (index) { | |
1569 | case 0: | |
1570 | out_le32(mbase + PECFG_POM0LAH, pciah); | |
1571 | out_le32(mbase + PECFG_POM0LAL, pcial); | |
1572 | dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAH, lah); | |
1573 | dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAL, lal); | |
1574 | dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKH, 0x7fffffff); | |
1575 | /* Note that 3 here means enabled | single region */ | |
1576 | dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, sa | 3); | |
1577 | break; | |
1578 | case 1: | |
1579 | out_le32(mbase + PECFG_POM1LAH, pciah); | |
1580 | out_le32(mbase + PECFG_POM1LAL, pcial); | |
1581 | dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAH, lah); | |
1582 | dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAL, lal); | |
1583 | dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKH, 0x7fffffff); | |
1584 | /* Note that 3 here means enabled | single region */ | |
1585 | dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, sa | 3); | |
1586 | break; | |
1587 | case 2: | |
1588 | out_le32(mbase + PECFG_POM2LAH, pciah); | |
1589 | out_le32(mbase + PECFG_POM2LAL, pcial); | |
1590 | dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAH, lah); | |
1591 | dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAL, lal); | |
1592 | dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKH, 0x7fffffff); | |
1593 | /* Note that 3 here means enabled | IO space !!! */ | |
1594 | dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, sa | 3); | |
1595 | break; | |
1596 | } | |
1597 | ||
1598 | return 0; | |
1599 | } | |
1600 | ||
a2d2e1ec BH |
1601 | static void __init ppc4xx_configure_pciex_POMs(struct ppc4xx_pciex_port *port, |
1602 | struct pci_controller *hose, | |
1603 | void __iomem *mbase) | |
1604 | { | |
84d727a1 | 1605 | int i, j, found_isa_hole = 0; |
a2d2e1ec BH |
1606 | |
1607 | /* Setup outbound memory windows */ | |
1608 | for (i = j = 0; i < 3; i++) { | |
1609 | struct resource *res = &hose->mem_resources[i]; | |
1610 | ||
1611 | /* we only care about memory windows */ | |
1612 | if (!(res->flags & IORESOURCE_MEM)) | |
1613 | continue; | |
1614 | if (j > 1) { | |
1615 | printk(KERN_WARNING "%s: Too many ranges\n", | |
1616 | port->node->full_name); | |
1617 | break; | |
1618 | } | |
1619 | ||
84d727a1 BH |
1620 | /* Configure the resource */ |
1621 | if (ppc4xx_setup_one_pciex_POM(port, hose, mbase, | |
1622 | res->start, | |
1623 | res->start - hose->pci_mem_offset, | |
28f65c11 | 1624 | resource_size(res), |
84d727a1 BH |
1625 | res->flags, |
1626 | j) == 0) { | |
1627 | j++; | |
1628 | ||
1629 | /* If the resource PCI address is 0 then we have our | |
1630 | * ISA memory hole | |
1631 | */ | |
1632 | if (res->start == hose->pci_mem_offset) | |
1633 | found_isa_hole = 1; | |
a2d2e1ec | 1634 | } |
a2d2e1ec BH |
1635 | } |
1636 | ||
84d727a1 BH |
1637 | /* Handle ISA memory hole if not already covered */ |
1638 | if (j <= 1 && !found_isa_hole && hose->isa_mem_size) | |
1639 | if (ppc4xx_setup_one_pciex_POM(port, hose, mbase, | |
1640 | hose->isa_mem_phys, 0, | |
1641 | hose->isa_mem_size, 0, j) == 0) | |
1642 | printk(KERN_INFO "%s: Legacy ISA memory support enabled\n", | |
1643 | hose->dn->full_name); | |
1644 | ||
1645 | /* Configure IO, always 64K starting at 0. We hard wire it to 64K ! | |
1646 | * Note also that it -has- to be region index 2 on this HW | |
1647 | */ | |
1648 | if (hose->io_resource.flags & IORESOURCE_IO) | |
1649 | ppc4xx_setup_one_pciex_POM(port, hose, mbase, | |
1650 | hose->io_base_phys, 0, | |
1651 | 0x10000, IORESOURCE_IO, 2); | |
a2d2e1ec BH |
1652 | } |
1653 | ||
1654 | static void __init ppc4xx_configure_pciex_PIMs(struct ppc4xx_pciex_port *port, | |
1655 | struct pci_controller *hose, | |
1656 | void __iomem *mbase, | |
1657 | struct resource *res) | |
1658 | { | |
28f65c11 | 1659 | resource_size_t size = resource_size(res); |
a2d2e1ec BH |
1660 | u64 sa; |
1661 | ||
80daac3f SR |
1662 | if (port->endpoint) { |
1663 | resource_size_t ep_addr = 0; | |
1664 | resource_size_t ep_size = 32 << 20; | |
1665 | ||
1666 | /* Currently we map a fixed 64MByte window to PLB address | |
1667 | * 0 (SDRAM). This should probably be configurable via a dts | |
1668 | * property. | |
1669 | */ | |
1670 | ||
1671 | /* Calculate window size */ | |
d258e64e | 1672 | sa = (0xffffffffffffffffull << ilog2(ep_size)); |
80daac3f SR |
1673 | |
1674 | /* Setup BAR0 */ | |
1675 | out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa)); | |
1676 | out_le32(mbase + PECFG_BAR0LMPA, RES_TO_U32_LOW(sa) | | |
1677 | PCI_BASE_ADDRESS_MEM_TYPE_64); | |
a2d2e1ec | 1678 | |
80daac3f SR |
1679 | /* Disable BAR1 & BAR2 */ |
1680 | out_le32(mbase + PECFG_BAR1MPA, 0); | |
1681 | out_le32(mbase + PECFG_BAR2HMPA, 0); | |
1682 | out_le32(mbase + PECFG_BAR2LMPA, 0); | |
a2d2e1ec | 1683 | |
80daac3f SR |
1684 | out_le32(mbase + PECFG_PIM01SAH, RES_TO_U32_HIGH(sa)); |
1685 | out_le32(mbase + PECFG_PIM01SAL, RES_TO_U32_LOW(sa)); | |
1686 | ||
1687 | out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(ep_addr)); | |
1688 | out_le32(mbase + PCI_BASE_ADDRESS_1, RES_TO_U32_HIGH(ep_addr)); | |
1689 | } else { | |
1690 | /* Calculate window size */ | |
d258e64e | 1691 | sa = (0xffffffffffffffffull << ilog2(size)); |
80daac3f SR |
1692 | if (res->flags & IORESOURCE_PREFETCH) |
1693 | sa |= 0x8; | |
1694 | ||
1695 | out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa)); | |
1696 | out_le32(mbase + PECFG_BAR0LMPA, RES_TO_U32_LOW(sa)); | |
1697 | ||
1698 | /* The setup of the split looks weird to me ... let's see | |
1699 | * if it works | |
1700 | */ | |
1701 | out_le32(mbase + PECFG_PIM0LAL, 0x00000000); | |
1702 | out_le32(mbase + PECFG_PIM0LAH, 0x00000000); | |
1703 | out_le32(mbase + PECFG_PIM1LAL, 0x00000000); | |
1704 | out_le32(mbase + PECFG_PIM1LAH, 0x00000000); | |
1705 | out_le32(mbase + PECFG_PIM01SAH, 0xffff0000); | |
1706 | out_le32(mbase + PECFG_PIM01SAL, 0x00000000); | |
1707 | ||
1708 | out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(res->start)); | |
1709 | out_le32(mbase + PCI_BASE_ADDRESS_1, RES_TO_U32_HIGH(res->start)); | |
1710 | } | |
a2d2e1ec BH |
1711 | |
1712 | /* Enable inbound mapping */ | |
1713 | out_le32(mbase + PECFG_PIMEN, 0x1); | |
1714 | ||
a2d2e1ec BH |
1715 | /* Enable I/O, Mem, and Busmaster cycles */ |
1716 | out_le16(mbase + PCI_COMMAND, | |
1717 | in_le16(mbase + PCI_COMMAND) | | |
1718 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); | |
1719 | } | |
1720 | ||
1721 | static void __init ppc4xx_pciex_port_setup_hose(struct ppc4xx_pciex_port *port) | |
1722 | { | |
1723 | struct resource dma_window; | |
1724 | struct pci_controller *hose = NULL; | |
1725 | const int *bus_range; | |
1726 | int primary = 0, busses; | |
1727 | void __iomem *mbase = NULL, *cfg_data = NULL; | |
80daac3f SR |
1728 | const u32 *pval; |
1729 | u32 val; | |
a2d2e1ec BH |
1730 | |
1731 | /* Check if primary bridge */ | |
1732 | if (of_get_property(port->node, "primary", NULL)) | |
1733 | primary = 1; | |
1734 | ||
1735 | /* Get bus range if any */ | |
1736 | bus_range = of_get_property(port->node, "bus-range", NULL); | |
1737 | ||
1738 | /* Allocate the host controller data structure */ | |
1739 | hose = pcibios_alloc_controller(port->node); | |
1740 | if (!hose) | |
1741 | goto fail; | |
1742 | ||
1743 | /* We stick the port number in "indirect_type" so the config space | |
1744 | * ops can retrieve the port data structure easily | |
1745 | */ | |
1746 | hose->indirect_type = port->index; | |
1747 | ||
1748 | /* Get bus range */ | |
1749 | hose->first_busno = bus_range ? bus_range[0] : 0x0; | |
1750 | hose->last_busno = bus_range ? bus_range[1] : 0xff; | |
1751 | ||
1752 | /* Because of how big mapping the config space is (1M per bus), we | |
1753 | * limit how many busses we support. In the long run, we could replace | |
1754 | * that with something akin to kmap_atomic instead. We set aside 1 bus | |
1755 | * for the host itself too. | |
1756 | */ | |
1757 | busses = hose->last_busno - hose->first_busno; /* This is off by 1 */ | |
1758 | if (busses > MAX_PCIE_BUS_MAPPED) { | |
1759 | busses = MAX_PCIE_BUS_MAPPED; | |
1760 | hose->last_busno = hose->first_busno + busses; | |
1761 | } | |
1762 | ||
80daac3f SR |
1763 | if (!port->endpoint) { |
1764 | /* Only map the external config space in cfg_data for | |
1765 | * PCIe root-complexes. External space is 1M per bus | |
1766 | */ | |
1767 | cfg_data = ioremap(port->cfg_space.start + | |
1768 | (hose->first_busno + 1) * 0x100000, | |
1769 | busses * 0x100000); | |
1770 | if (cfg_data == NULL) { | |
1771 | printk(KERN_ERR "%s: Can't map external config space !", | |
1772 | port->node->full_name); | |
1773 | goto fail; | |
1774 | } | |
1775 | hose->cfg_data = cfg_data; | |
1776 | } | |
1777 | ||
1778 | /* Always map the host config space in cfg_addr. | |
1779 | * Internal space is 4K | |
a2d2e1ec | 1780 | */ |
a2d2e1ec | 1781 | mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000); |
80daac3f SR |
1782 | if (mbase == NULL) { |
1783 | printk(KERN_ERR "%s: Can't map internal config space !", | |
a2d2e1ec BH |
1784 | port->node->full_name); |
1785 | goto fail; | |
1786 | } | |
a2d2e1ec BH |
1787 | hose->cfg_addr = mbase; |
1788 | ||
1789 | pr_debug("PCIE %s, bus %d..%d\n", port->node->full_name, | |
1790 | hose->first_busno, hose->last_busno); | |
1791 | pr_debug(" config space mapped at: root @0x%p, other @0x%p\n", | |
1792 | hose->cfg_addr, hose->cfg_data); | |
1793 | ||
1794 | /* Setup config space */ | |
1795 | hose->ops = &ppc4xx_pciex_pci_ops; | |
1796 | port->hose = hose; | |
1797 | mbase = (void __iomem *)hose->cfg_addr; | |
1798 | ||
80daac3f SR |
1799 | if (!port->endpoint) { |
1800 | /* | |
1801 | * Set bus numbers on our root port | |
1802 | */ | |
1803 | out_8(mbase + PCI_PRIMARY_BUS, hose->first_busno); | |
1804 | out_8(mbase + PCI_SECONDARY_BUS, hose->first_busno + 1); | |
1805 | out_8(mbase + PCI_SUBORDINATE_BUS, hose->last_busno); | |
1806 | } | |
a2d2e1ec BH |
1807 | |
1808 | /* | |
1809 | * OMRs are already reset, also disable PIMs | |
1810 | */ | |
1811 | out_le32(mbase + PECFG_PIMEN, 0); | |
1812 | ||
1813 | /* Parse outbound mapping resources */ | |
1814 | pci_process_bridge_OF_ranges(hose, port->node, primary); | |
1815 | ||
1816 | /* Parse inbound mapping resources */ | |
1817 | if (ppc4xx_parse_dma_ranges(hose, mbase, &dma_window) != 0) | |
1818 | goto fail; | |
1819 | ||
1820 | /* Configure outbound ranges POMs */ | |
1821 | ppc4xx_configure_pciex_POMs(port, hose, mbase); | |
1822 | ||
1823 | /* Configure inbound ranges PIMs */ | |
1824 | ppc4xx_configure_pciex_PIMs(port, hose, mbase, &dma_window); | |
1825 | ||
1826 | /* The root complex doesn't show up if we don't set some vendor | |
80daac3f SR |
1827 | * and device IDs into it. The defaults below are the same bogus |
1828 | * one that the initial code in arch/ppc had. This can be | |
1829 | * overwritten by setting the "vendor-id/device-id" properties | |
1830 | * in the pciex node. | |
a2d2e1ec | 1831 | */ |
a2d2e1ec | 1832 | |
80daac3f SR |
1833 | /* Get the (optional) vendor-/device-id from the device-tree */ |
1834 | pval = of_get_property(port->node, "vendor-id", NULL); | |
1835 | if (pval) { | |
1836 | val = *pval; | |
1837 | } else { | |
1838 | if (!port->endpoint) | |
1839 | val = 0xaaa0 + port->index; | |
1840 | else | |
1841 | val = 0xeee0 + port->index; | |
1842 | } | |
1843 | out_le16(mbase + 0x200, val); | |
1844 | ||
1845 | pval = of_get_property(port->node, "device-id", NULL); | |
1846 | if (pval) { | |
1847 | val = *pval; | |
1848 | } else { | |
1849 | if (!port->endpoint) | |
1850 | val = 0xbed0 + port->index; | |
1851 | else | |
1852 | val = 0xfed0 + port->index; | |
1853 | } | |
1854 | out_le16(mbase + 0x202, val); | |
1855 | ||
1856 | if (!port->endpoint) { | |
1857 | /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */ | |
1858 | out_le32(mbase + 0x208, 0x06040001); | |
1859 | ||
1860 | printk(KERN_INFO "PCIE%d: successfully set as root-complex\n", | |
1861 | port->index); | |
1862 | } else { | |
1863 | /* Set Class Code to Processor/PPC */ | |
1864 | out_le32(mbase + 0x208, 0x0b200001); | |
1865 | ||
1866 | printk(KERN_INFO "PCIE%d: successfully set as endpoint\n", | |
1867 | port->index); | |
1868 | } | |
a2d2e1ec | 1869 | |
a2d2e1ec BH |
1870 | return; |
1871 | fail: | |
1872 | if (hose) | |
1873 | pcibios_free_controller(hose); | |
1874 | if (cfg_data) | |
1875 | iounmap(cfg_data); | |
1876 | if (mbase) | |
1877 | iounmap(mbase); | |
1878 | } | |
1879 | ||
5738ec6d BH |
1880 | static void __init ppc4xx_probe_pciex_bridge(struct device_node *np) |
1881 | { | |
a2d2e1ec BH |
1882 | struct ppc4xx_pciex_port *port; |
1883 | const u32 *pval; | |
1884 | int portno; | |
1885 | unsigned int dcrs; | |
80daac3f | 1886 | const char *val; |
a2d2e1ec BH |
1887 | |
1888 | /* First, proceed to core initialization as we assume there's | |
1889 | * only one PCIe core in the system | |
1890 | */ | |
1891 | if (ppc4xx_pciex_check_core_init(np)) | |
1892 | return; | |
1893 | ||
1894 | /* Get the port number from the device-tree */ | |
1895 | pval = of_get_property(np, "port", NULL); | |
1896 | if (pval == NULL) { | |
1897 | printk(KERN_ERR "PCIE: Can't find port number for %s\n", | |
1898 | np->full_name); | |
1899 | return; | |
1900 | } | |
1901 | portno = *pval; | |
1902 | if (portno >= ppc4xx_pciex_port_count) { | |
1903 | printk(KERN_ERR "PCIE: port number out of range for %s\n", | |
1904 | np->full_name); | |
1905 | return; | |
1906 | } | |
1907 | port = &ppc4xx_pciex_ports[portno]; | |
1908 | port->index = portno; | |
995ada8d SR |
1909 | |
1910 | /* | |
1911 | * Check if device is enabled | |
1912 | */ | |
1913 | if (!of_device_is_available(np)) { | |
1914 | printk(KERN_INFO "PCIE%d: Port disabled via device-tree\n", port->index); | |
1915 | return; | |
1916 | } | |
1917 | ||
a2d2e1ec BH |
1918 | port->node = of_node_get(np); |
1919 | pval = of_get_property(np, "sdr-base", NULL); | |
1920 | if (pval == NULL) { | |
1921 | printk(KERN_ERR "PCIE: missing sdr-base for %s\n", | |
1922 | np->full_name); | |
1923 | return; | |
1924 | } | |
1925 | port->sdr_base = *pval; | |
1926 | ||
80daac3f SR |
1927 | /* Check if device_type property is set to "pci" or "pci-endpoint". |
1928 | * Resulting from this setup this PCIe port will be configured | |
1929 | * as root-complex or as endpoint. | |
1930 | */ | |
1931 | val = of_get_property(port->node, "device_type", NULL); | |
1932 | if (!strcmp(val, "pci-endpoint")) { | |
1933 | port->endpoint = 1; | |
1934 | } else if (!strcmp(val, "pci")) { | |
1935 | port->endpoint = 0; | |
1936 | } else { | |
1937 | printk(KERN_ERR "PCIE: missing or incorrect device_type for %s\n", | |
1938 | np->full_name); | |
1939 | return; | |
1940 | } | |
035ee428 | 1941 | |
a2d2e1ec BH |
1942 | /* Fetch config space registers address */ |
1943 | if (of_address_to_resource(np, 0, &port->cfg_space)) { | |
1944 | printk(KERN_ERR "%s: Can't get PCI-E config space !", | |
1945 | np->full_name); | |
1946 | return; | |
1947 | } | |
1948 | /* Fetch host bridge internal registers address */ | |
1949 | if (of_address_to_resource(np, 1, &port->utl_regs)) { | |
1950 | printk(KERN_ERR "%s: Can't get UTL register base !", | |
1951 | np->full_name); | |
1952 | return; | |
1953 | } | |
1954 | ||
1955 | /* Map DCRs */ | |
1956 | dcrs = dcr_resource_start(np, 0); | |
1957 | if (dcrs == 0) { | |
1958 | printk(KERN_ERR "%s: Can't get DCR register base !", | |
1959 | np->full_name); | |
1960 | return; | |
1961 | } | |
1962 | port->dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0)); | |
1963 | ||
1964 | /* Initialize the port specific registers */ | |
035ee428 BH |
1965 | if (ppc4xx_pciex_port_init(port)) { |
1966 | printk(KERN_WARNING "PCIE%d: Port init failed\n", port->index); | |
a2d2e1ec | 1967 | return; |
035ee428 | 1968 | } |
a2d2e1ec BH |
1969 | |
1970 | /* Setup the linux hose data structure */ | |
1971 | ppc4xx_pciex_port_setup_hose(port); | |
5738ec6d BH |
1972 | } |
1973 | ||
a2d2e1ec BH |
1974 | #endif /* CONFIG_PPC4xx_PCI_EXPRESS */ |
1975 | ||
5738ec6d BH |
1976 | static int __init ppc4xx_pci_find_bridges(void) |
1977 | { | |
1978 | struct device_node *np; | |
1979 | ||
0e47ff1c | 1980 | pci_add_flags(PCI_ENABLE_PROC_DOMAINS | PCI_COMPAT_DOMAIN_0); |
41b6a085 | 1981 | |
a2d2e1ec | 1982 | #ifdef CONFIG_PPC4xx_PCI_EXPRESS |
5738ec6d BH |
1983 | for_each_compatible_node(np, NULL, "ibm,plb-pciex") |
1984 | ppc4xx_probe_pciex_bridge(np); | |
a2d2e1ec | 1985 | #endif |
5738ec6d BH |
1986 | for_each_compatible_node(np, NULL, "ibm,plb-pcix") |
1987 | ppc4xx_probe_pcix_bridge(np); | |
1988 | for_each_compatible_node(np, NULL, "ibm,plb-pci") | |
1989 | ppc4xx_probe_pci_bridge(np); | |
1990 | ||
1991 | return 0; | |
1992 | } | |
1993 | arch_initcall(ppc4xx_pci_find_bridges); | |
1994 |