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generic: make PFN_PHYS explicitly return phys_addr_t
[deliverable/linux.git] / arch / powerpc / sysdev / ppc4xx_pci.c
CommitLineData
5738ec6d
BH		 1/*
2 * PCI / PCI-X / PCI-Express support for 4xx parts
3 *
4 * Copyright 2007 Ben. Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
5 *
a2d2e1ec
BH		 6 * Most PCI Express code is coming from Stefan Roese implementation for
7 * arch/ppc in the Denx tree, slightly reworked by me.
8 *
9 * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
10 *
11 * Some of that comes itself from a previous implementation for 440SPE only
12 * by Roland Dreier:
13 *
14 * Copyright (c) 2005 Cisco Systems. All rights reserved.
15 * Roland Dreier <rolandd@cisco.com>
16 *
5738ec6d
BH		 17 */
18
035ee428
BH		 19#undef DEBUG
20
5738ec6d
BH		 21#include <linux/kernel.h>
22#include <linux/pci.h>
23#include <linux/init.h>
24#include <linux/of.h>
a2d2e1ec
BH		 25#include <linux/bootmem.h>
26#include <linux/delay.h>
5738ec6d
BH		 27
28#include <asm/io.h>
29#include <asm/pci-bridge.h>
30#include <asm/machdep.h>
a2d2e1ec
BH		 31#include <asm/dcr.h>
32#include <asm/dcr-regs.h>
5738ec6d
BH		 33
34#include "ppc4xx_pci.h"
35
36static int dma_offset_set;
37
38/* Move that to a useable header */
39extern unsigned long total_memory;
40
a2d2e1ec
BH		 41#define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL))
42#define U64_TO_U32_HIGH(val) ((u32)((val) >> 32))
43
44#ifdef CONFIG_RESOURCES_64BIT
45#define RES_TO_U32_LOW(val) U64_TO_U32_LOW(val)
46#define RES_TO_U32_HIGH(val) U64_TO_U32_HIGH(val)
47#else
48#define RES_TO_U32_LOW(val) (val)
49#define RES_TO_U32_HIGH(val) (0)
50#endif
51
accf5ef2
SR		 52static inline int ppc440spe_revA(void)
53{
54 /* Catch both 440SPe variants, with and without RAID6 support */
55 if ((mfspr(SPRN_PVR) & 0xffefffff) == 0x53421890)
56 return 1;
57 else
58 return 0;
59}
60
c839e0ef
BH		 61static void fixup_ppc4xx_pci_bridge(struct pci_dev *dev)
62{
63 struct pci_controller *hose;
64 int i;
65
66 if (dev->devfn != 0 || dev->bus->self != NULL)
67 return;
68
69 hose = pci_bus_to_host(dev->bus);
70 if (hose == NULL)
71 return;
72
73 if (!of_device_is_compatible(hose->dn, "ibm,plb-pciex") &&
74 !of_device_is_compatible(hose->dn, "ibm,plb-pcix") &&
75 !of_device_is_compatible(hose->dn, "ibm,plb-pci"))
76 return;
77
5ce4b596
JB		 78 if (of_device_is_compatible(hose->dn, "ibm,plb440epx-pci") ||
79 of_device_is_compatible(hose->dn, "ibm,plb440grx-pci")) {
80 hose->indirect_type |= PPC_INDIRECT_TYPE_BROKEN_MRM;
81 }
82
c839e0ef
BH		 83 /* Hide the PCI host BARs from the kernel as their content doesn't
84 * fit well in the resource management
85 */
86 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
87 dev->resource[i].start = dev->resource[i].end = 0;
88 dev->resource[i].flags = 0;
89 }
90
91 printk(KERN_INFO "PCI: Hiding 4xx host bridge resources %s\n",
92 pci_name(dev));
93}
94DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, fixup_ppc4xx_pci_bridge);
95
5738ec6d
BH		 96static int __init ppc4xx_parse_dma_ranges(struct pci_controller *hose,
97 void __iomem *reg,
98 struct resource *res)
99{
100 u64 size;
101 const u32 *ranges;
102 int rlen;
103 int pna = of_n_addr_cells(hose->dn);
104 int np = pna + 5;
105
106 /* Default */
107 res->start = 0;
108 res->end = size = 0x80000000;
109 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
110
111 /* Get dma-ranges property */
112 ranges = of_get_property(hose->dn, "dma-ranges", &rlen);
113 if (ranges == NULL)
114 goto out;
115
116 /* Walk it */
117 while ((rlen -= np * 4) >= 0) {
118 u32 pci_space = ranges[0];
119 u64 pci_addr = of_read_number(ranges + 1, 2);
120 u64 cpu_addr = of_translate_dma_address(hose->dn, ranges + 3);
121 size = of_read_number(ranges + pna + 3, 2);
122 ranges += np;
123 if (cpu_addr == OF_BAD_ADDR || size == 0)
124 continue;
125
126 /* We only care about memory */
127 if ((pci_space & 0x03000000) != 0x02000000)
128 continue;
129
130 /* We currently only support memory at 0, and pci_addr
131 * within 32 bits space
132 */
133 if (cpu_addr != 0 || pci_addr > 0xffffffff) {
134 printk(KERN_WARNING "%s: Ignored unsupported dma range"
135 " 0x%016llx...0x%016llx -> 0x%016llx\n",
136 hose->dn->full_name,
137 pci_addr, pci_addr + size - 1, cpu_addr);
138 continue;
139 }
140
141 /* Check if not prefetchable */
142 if (!(pci_space & 0x40000000))
143 res->flags &= ~IORESOURCE_PREFETCH;
144
145
146 /* Use that */
147 res->start = pci_addr;
148#ifndef CONFIG_RESOURCES_64BIT
149 /* Beware of 32 bits resources */
150 if ((pci_addr + size) > 0x100000000ull)
151 res->end = 0xffffffff;
152 else
153#endif
154 res->end = res->start + size - 1;
155 break;
156 }
157
158 /* We only support one global DMA offset */
159 if (dma_offset_set && pci_dram_offset != res->start) {
160 printk(KERN_ERR "%s: dma-ranges(s) mismatch\n",
161 hose->dn->full_name);
162 return -ENXIO;
163 }
164
165 /* Check that we can fit all of memory as we don't support
166 * DMA bounce buffers
167 */
168 if (size < total_memory) {
169 printk(KERN_ERR "%s: dma-ranges too small "
170 "(size=%llx total_memory=%lx)\n",
171 hose->dn->full_name, size, total_memory);
172 return -ENXIO;
173 }
174
175 /* Check we are a power of 2 size and that base is a multiple of size*/
176 if (!is_power_of_2(size) ||
177 (res->start & (size - 1)) != 0) {
178 printk(KERN_ERR "%s: dma-ranges unaligned\n",
179 hose->dn->full_name);
180 return -ENXIO;
181 }
182
183 /* Check that we are fully contained within 32 bits space */
184 if (res->end > 0xffffffff) {
185 printk(KERN_ERR "%s: dma-ranges outside of 32 bits space\n",
186 hose->dn->full_name);
187 return -ENXIO;
188 }
189 out:
190 dma_offset_set = 1;
191 pci_dram_offset = res->start;
192
193 printk(KERN_INFO "4xx PCI DMA offset set to 0x%08lx\n",
194 pci_dram_offset);
195 return 0;
196}
197
198/*
199 * 4xx PCI 2.x part
200 */
c839e0ef
BH		 201
202static void __init ppc4xx_configure_pci_PMMs(struct pci_controller *hose,
203 void __iomem *reg)
204{
205 u32 la, ma, pcila, pciha;
206 int i, j;
207
208 /* Setup outbound memory windows */
209 for (i = j = 0; i < 3; i++) {
210 struct resource *res = &hose->mem_resources[i];
211
212 /* we only care about memory windows */
213 if (!(res->flags & IORESOURCE_MEM))
214 continue;
215 if (j > 2) {
216 printk(KERN_WARNING "%s: Too many ranges\n",
217 hose->dn->full_name);
218 break;
219 }
220
221 /* Calculate register values */
222 la = res->start;
a2d2e1ec
BH		 223 pciha = RES_TO_U32_HIGH(res->start - hose->pci_mem_offset);
224 pcila = RES_TO_U32_LOW(res->start - hose->pci_mem_offset);
c839e0ef
BH		 225
226 ma = res->end + 1 - res->start;
227 if (!is_power_of_2(ma) || ma < 0x1000 || ma > 0xffffffffu) {
228 printk(KERN_WARNING "%s: Resource out of range\n",
229 hose->dn->full_name);
230 continue;
231 }
232 ma = (0xffffffffu << ilog2(ma)) | 0x1;
233 if (res->flags & IORESOURCE_PREFETCH)
234 ma |= 0x2;
235
236 /* Program register values */
237 writel(la, reg + PCIL0_PMM0LA + (0x10 * j));
238 writel(pcila, reg + PCIL0_PMM0PCILA + (0x10 * j));
239 writel(pciha, reg + PCIL0_PMM0PCIHA + (0x10 * j));
240 writel(ma, reg + PCIL0_PMM0MA + (0x10 * j));
241 j++;
242 }
243}
244
245static void __init ppc4xx_configure_pci_PTMs(struct pci_controller *hose,
246 void __iomem *reg,
247 const struct resource *res)
248{
249 resource_size_t size = res->end - res->start + 1;
250 u32 sa;
251
252 /* Calculate window size */
253 sa = (0xffffffffu << ilog2(size)) | 1;
254 sa |= 0x1;
255
256 /* RAM is always at 0 local for now */
257 writel(0, reg + PCIL0_PTM1LA);
258 writel(sa, reg + PCIL0_PTM1MS);
259
260 /* Map on PCI side */
261 early_write_config_dword(hose, hose->first_busno, 0,
262 PCI_BASE_ADDRESS_1, res->start);
263 early_write_config_dword(hose, hose->first_busno, 0,
264 PCI_BASE_ADDRESS_2, 0x00000000);
265 early_write_config_word(hose, hose->first_busno, 0,
266 PCI_COMMAND, 0x0006);
267}
268
5738ec6d
BH		 269static void __init ppc4xx_probe_pci_bridge(struct device_node *np)
270{
271 /* NYI */
c839e0ef
BH		 272 struct resource rsrc_cfg;
273 struct resource rsrc_reg;
274 struct resource dma_window;
275 struct pci_controller *hose = NULL;
276 void __iomem *reg = NULL;
277 const int *bus_range;
278 int primary = 0;
279
280 /* Fetch config space registers address */
281 if (of_address_to_resource(np, 0, &rsrc_cfg)) {
282 printk(KERN_ERR "%s:Can't get PCI config register base !",
283 np->full_name);
284 return;
285 }
286 /* Fetch host bridge internal registers address */
287 if (of_address_to_resource(np, 3, &rsrc_reg)) {
288 printk(KERN_ERR "%s: Can't get PCI internal register base !",
289 np->full_name);
290 return;
291 }
292
293 /* Check if primary bridge */
294 if (of_get_property(np, "primary", NULL))
295 primary = 1;
296
297 /* Get bus range if any */
298 bus_range = of_get_property(np, "bus-range", NULL);
299
300 /* Map registers */
301 reg = ioremap(rsrc_reg.start, rsrc_reg.end + 1 - rsrc_reg.start);
302 if (reg == NULL) {
303 printk(KERN_ERR "%s: Can't map registers !", np->full_name);
304 goto fail;
305 }
306
307 /* Allocate the host controller data structure */
308 hose = pcibios_alloc_controller(np);
309 if (!hose)
310 goto fail;
311
312 hose->first_busno = bus_range ? bus_range[0] : 0x0;
313 hose->last_busno = bus_range ? bus_range[1] : 0xff;
314
315 /* Setup config space */
316 setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4, 0);
317
318 /* Disable all windows */
319 writel(0, reg + PCIL0_PMM0MA);
320 writel(0, reg + PCIL0_PMM1MA);
321 writel(0, reg + PCIL0_PMM2MA);
322 writel(0, reg + PCIL0_PTM1MS);
323 writel(0, reg + PCIL0_PTM2MS);
324
325 /* Parse outbound mapping resources */
326 pci_process_bridge_OF_ranges(hose, np, primary);
327
328 /* Parse inbound mapping resources */
329 if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0)
330 goto fail;
331
332 /* Configure outbound ranges POMs */
333 ppc4xx_configure_pci_PMMs(hose, reg);
334
335 /* Configure inbound ranges PIMs */
336 ppc4xx_configure_pci_PTMs(hose, reg, &dma_window);
337
338 /* We don't need the registers anymore */
339 iounmap(reg);
340 return;
341
342 fail:
343 if (hose)
344 pcibios_free_controller(hose);
345 if (reg)
346 iounmap(reg);
5738ec6d
BH		 347}
348
349/*
350 * 4xx PCI-X part
351 */
352
353static void __init ppc4xx_configure_pcix_POMs(struct pci_controller *hose,
354 void __iomem *reg)
355{
356 u32 lah, lal, pciah, pcial, sa;
357 int i, j;
358
359 /* Setup outbound memory windows */
360 for (i = j = 0; i < 3; i++) {
361 struct resource *res = &hose->mem_resources[i];
362
363 /* we only care about memory windows */
364 if (!(res->flags & IORESOURCE_MEM))
365 continue;
366 if (j > 1) {
367 printk(KERN_WARNING "%s: Too many ranges\n",
368 hose->dn->full_name);
369 break;
370 }
371
372 /* Calculate register values */
a2d2e1ec
BH		 373 lah = RES_TO_U32_HIGH(res->start);
374 lal = RES_TO_U32_LOW(res->start);
375 pciah = RES_TO_U32_HIGH(res->start - hose->pci_mem_offset);
376 pcial = RES_TO_U32_LOW(res->start - hose->pci_mem_offset);
5738ec6d
BH		 377 sa = res->end + 1 - res->start;
378 if (!is_power_of_2(sa) || sa < 0x100000 ||
379 sa > 0xffffffffu) {
380 printk(KERN_WARNING "%s: Resource out of range\n",
381 hose->dn->full_name);
382 continue;
383 }
384 sa = (0xffffffffu << ilog2(sa)) | 0x1;
385
386 /* Program register values */
387 if (j == 0) {
388 writel(lah, reg + PCIX0_POM0LAH);
389 writel(lal, reg + PCIX0_POM0LAL);
390 writel(pciah, reg + PCIX0_POM0PCIAH);
391 writel(pcial, reg + PCIX0_POM0PCIAL);
392 writel(sa, reg + PCIX0_POM0SA);
393 } else {
394 writel(lah, reg + PCIX0_POM1LAH);
395 writel(lal, reg + PCIX0_POM1LAL);
396 writel(pciah, reg + PCIX0_POM1PCIAH);
397 writel(pcial, reg + PCIX0_POM1PCIAL);
398 writel(sa, reg + PCIX0_POM1SA);
399 }
400 j++;
401 }
402}
403
404static void __init ppc4xx_configure_pcix_PIMs(struct pci_controller *hose,
405 void __iomem *reg,
406 const struct resource *res,
407 int big_pim,
408 int enable_msi_hole)
409{
410 resource_size_t size = res->end - res->start + 1;
411 u32 sa;
412
413 /* RAM is always at 0 */
414 writel(0x00000000, reg + PCIX0_PIM0LAH);
415 writel(0x00000000, reg + PCIX0_PIM0LAL);
416
417 /* Calculate window size */
418 sa = (0xffffffffu << ilog2(size)) | 1;
419 sa |= 0x1;
420 if (res->flags & IORESOURCE_PREFETCH)
421 sa |= 0x2;
422 if (enable_msi_hole)
423 sa |= 0x4;
424 writel(sa, reg + PCIX0_PIM0SA);
425 if (big_pim)
426 writel(0xffffffff, reg + PCIX0_PIM0SAH);
427
428 /* Map on PCI side */
429 writel(0x00000000, reg + PCIX0_BAR0H);
430 writel(res->start, reg + PCIX0_BAR0L);
431 writew(0x0006, reg + PCIX0_COMMAND);
432}
433
434static void __init ppc4xx_probe_pcix_bridge(struct device_node *np)
435{
436 struct resource rsrc_cfg;
437 struct resource rsrc_reg;
438 struct resource dma_window;
439 struct pci_controller *hose = NULL;
440 void __iomem *reg = NULL;
441 const int *bus_range;
442 int big_pim = 0, msi = 0, primary = 0;
443
444 /* Fetch config space registers address */
445 if (of_address_to_resource(np, 0, &rsrc_cfg)) {
446 printk(KERN_ERR "%s:Can't get PCI-X config register base !",
447 np->full_name);
448 return;
449 }
450 /* Fetch host bridge internal registers address */
451 if (of_address_to_resource(np, 3, &rsrc_reg)) {
452 printk(KERN_ERR "%s: Can't get PCI-X internal register base !",
453 np->full_name);
454 return;
455 }
456
457 /* Check if it supports large PIMs (440GX) */
458 if (of_get_property(np, "large-inbound-windows", NULL))
459 big_pim = 1;
460
461 /* Check if we should enable MSIs inbound hole */
462 if (of_get_property(np, "enable-msi-hole", NULL))
463 msi = 1;
464
465 /* Check if primary bridge */
466 if (of_get_property(np, "primary", NULL))
467 primary = 1;
468
469 /* Get bus range if any */
470 bus_range = of_get_property(np, "bus-range", NULL);
471
472 /* Map registers */
473 reg = ioremap(rsrc_reg.start, rsrc_reg.end + 1 - rsrc_reg.start);
474 if (reg == NULL) {
475 printk(KERN_ERR "%s: Can't map registers !", np->full_name);
476 goto fail;
477 }
478
479 /* Allocate the host controller data structure */
480 hose = pcibios_alloc_controller(np);
481 if (!hose)
482 goto fail;
483
484 hose->first_busno = bus_range ? bus_range[0] : 0x0;
485 hose->last_busno = bus_range ? bus_range[1] : 0xff;
486
487 /* Setup config space */
488 setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4, 0);
489
490 /* Disable all windows */
491 writel(0, reg + PCIX0_POM0SA);
492 writel(0, reg + PCIX0_POM1SA);
493 writel(0, reg + PCIX0_POM2SA);
494 writel(0, reg + PCIX0_PIM0SA);
495 writel(0, reg + PCIX0_PIM1SA);
496 writel(0, reg + PCIX0_PIM2SA);
497 if (big_pim) {
498 writel(0, reg + PCIX0_PIM0SAH);
499 writel(0, reg + PCIX0_PIM2SAH);
500 }
501
502 /* Parse outbound mapping resources */
503 pci_process_bridge_OF_ranges(hose, np, primary);
504
505 /* Parse inbound mapping resources */
506 if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0)
507 goto fail;
508
509 /* Configure outbound ranges POMs */
510 ppc4xx_configure_pcix_POMs(hose, reg);
511
512 /* Configure inbound ranges PIMs */
513 ppc4xx_configure_pcix_PIMs(hose, reg, &dma_window, big_pim, msi);
514
515 /* We don't need the registers anymore */
516 iounmap(reg);
517 return;
518
519 fail:
520 if (hose)
521 pcibios_free_controller(hose);
522 if (reg)
523 iounmap(reg);
524}
525
a2d2e1ec
BH		 526#ifdef CONFIG_PPC4xx_PCI_EXPRESS
527
5738ec6d
BH		 528/*
529 * 4xx PCI-Express part
a2d2e1ec
BH		 530 *
531 * We support 3 parts currently based on the compatible property:
532 *
accf5ef2 533 * ibm,plb-pciex-440spe
a2d2e1ec 534 * ibm,plb-pciex-405ex
66b7e504 535 * ibm,plb-pciex-460ex
a2d2e1ec
BH		 536 *
537 * Anything else will be rejected for now as they are all subtly
538 * different unfortunately.
539 *
5738ec6d 540 */
a2d2e1ec 541
78994e24 542#define MAX_PCIE_BUS_MAPPED 0x40
a2d2e1ec
BH		 543
544struct ppc4xx_pciex_port
545{
546 struct pci_controller *hose;
547 struct device_node *node;
548 unsigned int index;
549 int endpoint;
035ee428
BH		 550 int link;
551 int has_ibpre;
a2d2e1ec
BH		 552 unsigned int sdr_base;
553 dcr_host_t dcrs;
554 struct resource cfg_space;
555 struct resource utl_regs;
035ee428 556 void __iomem *utl_base;
a2d2e1ec
BH		 557};
558
559static struct ppc4xx_pciex_port *ppc4xx_pciex_ports;
560static unsigned int ppc4xx_pciex_port_count;
561
562struct ppc4xx_pciex_hwops
563{
564 int (*core_init)(struct device_node *np);
565 int (*port_init_hw)(struct ppc4xx_pciex_port *port);
566 int (*setup_utl)(struct ppc4xx_pciex_port *port);
567};
568
569static struct ppc4xx_pciex_hwops *ppc4xx_pciex_hwops;
570
571#ifdef CONFIG_44x
572
573/* Check various reset bits of the 440SPe PCIe core */
574static int __init ppc440spe_pciex_check_reset(struct device_node *np)
575{
576 u32 valPE0, valPE1, valPE2;
577 int err = 0;
578
579 /* SDR0_PEGPLLLCT1 reset */
580 if (!(mfdcri(SDR0, PESDR0_PLLLCT1) & 0x01000000)) {
581 /*
582 * the PCIe core was probably already initialised
583 * by firmware - let's re-reset RCSSET regs
584 *
585 * -- Shouldn't we also re-reset the whole thing ? -- BenH
586 */
587 pr_debug("PCIE: SDR0_PLLLCT1 already reset.\n");
588 mtdcri(SDR0, PESDR0_440SPE_RCSSET, 0x01010000);
589 mtdcri(SDR0, PESDR1_440SPE_RCSSET, 0x01010000);
590 mtdcri(SDR0, PESDR2_440SPE_RCSSET, 0x01010000);
591 }
592
593 valPE0 = mfdcri(SDR0, PESDR0_440SPE_RCSSET);
594 valPE1 = mfdcri(SDR0, PESDR1_440SPE_RCSSET);
595 valPE2 = mfdcri(SDR0, PESDR2_440SPE_RCSSET);
596
597 /* SDR0_PExRCSSET rstgu */
598 if (!(valPE0 & 0x01000000) ||
599 !(valPE1 & 0x01000000) ||
600 !(valPE2 & 0x01000000)) {
601 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstgu error\n");
602 err = -1;
603 }
604
605 /* SDR0_PExRCSSET rstdl */
606 if (!(valPE0 & 0x00010000) ||
607 !(valPE1 & 0x00010000) ||
608 !(valPE2 & 0x00010000)) {
609 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstdl error\n");
610 err = -1;
611 }
612
613 /* SDR0_PExRCSSET rstpyn */
614 if ((valPE0 & 0x00001000) ||
615 (valPE1 & 0x00001000) ||
616 (valPE2 & 0x00001000)) {
617 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstpyn error\n");
618 err = -1;
619 }
620
621 /* SDR0_PExRCSSET hldplb */
622 if ((valPE0 & 0x10000000) ||
623 (valPE1 & 0x10000000) ||
624 (valPE2 & 0x10000000)) {
625 printk(KERN_INFO "PCIE: SDR0_PExRCSSET hldplb error\n");
626 err = -1;
627 }
628
629 /* SDR0_PExRCSSET rdy */
630 if ((valPE0 & 0x00100000) ||
631 (valPE1 & 0x00100000) ||
632 (valPE2 & 0x00100000)) {
633 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rdy error\n");
634 err = -1;
635 }
636
637 /* SDR0_PExRCSSET shutdown */
638 if ((valPE0 & 0x00000100) ||
639 (valPE1 & 0x00000100) ||
640 (valPE2 & 0x00000100)) {
641 printk(KERN_INFO "PCIE: SDR0_PExRCSSET shutdown error\n");
642 err = -1;
643 }
644
645 return err;
646}
647
648/* Global PCIe core initializations for 440SPe core */
649static int __init ppc440spe_pciex_core_init(struct device_node *np)
650{
651 int time_out = 20;
652
653 /* Set PLL clock receiver to LVPECL */
6e42b21b 654 dcri_clrset(SDR0, PESDR0_PLLLCT1, 0, 1 << 28);
a2d2e1ec
BH		 655
656 /* Shouldn't we do all the calibration stuff etc... here ? */
657 if (ppc440spe_pciex_check_reset(np))
658 return -ENXIO;
659
660 if (!(mfdcri(SDR0, PESDR0_PLLLCT2) & 0x10000)) {
661 printk(KERN_INFO "PCIE: PESDR_PLLCT2 resistance calibration "
662 "failed (0x%08x)\n",
663 mfdcri(SDR0, PESDR0_PLLLCT2));
664 return -1;
665 }
666
667 /* De-assert reset of PCIe PLL, wait for lock */
6e42b21b 668 dcri_clrset(SDR0, PESDR0_PLLLCT1, 1 << 24, 0);
a2d2e1ec
BH		 669 udelay(3);
670
671 while (time_out) {
672 if (!(mfdcri(SDR0, PESDR0_PLLLCT3) & 0x10000000)) {
673 time_out--;
674 udelay(1);
675 } else
676 break;
677 }
678 if (!time_out) {
679 printk(KERN_INFO "PCIE: VCO output not locked\n");
680 return -1;
681 }
682
683 pr_debug("PCIE initialization OK\n");
684
685 return 3;
686}
687
688static int ppc440spe_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
689{
690 u32 val = 1 << 24;
691
692 if (port->endpoint)
693 val = PTYPE_LEGACY_ENDPOINT << 20;
694 else
695 val = PTYPE_ROOT_PORT << 20;
696
697 if (port->index == 0)
698 val |= LNKW_X8 << 12;
699 else
700 val |= LNKW_X4 << 12;
701
702 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
703 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x20222222);
accf5ef2 704 if (ppc440spe_revA())
a2d2e1ec
BH		 705 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x11000000);
706 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL0SET1, 0x35000000);
707 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL1SET1, 0x35000000);
708 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL2SET1, 0x35000000);
709 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL3SET1, 0x35000000);
710 if (port->index == 0) {
711 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL4SET1,
712 0x35000000);
713 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL5SET1,
714 0x35000000);
715 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL6SET1,
716 0x35000000);
717 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL7SET1,
718 0x35000000);
719 }
6e42b21b
VB		 720 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,
721 (1 << 24) | (1 << 16), 1 << 12);
a2d2e1ec
BH		 722
723 return 0;
724}
725
035ee428
BH		 726static int ppc440speA_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
727{
728 return ppc440spe_pciex_init_port_hw(port);
729}
730
731static int ppc440speB_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
a2d2e1ec 732{
035ee428
BH		 733 int rc = ppc440spe_pciex_init_port_hw(port);
734
735 port->has_ibpre = 1;
736
737 return rc;
738}
a2d2e1ec 739
035ee428
BH		 740static int ppc440speA_pciex_init_utl(struct ppc4xx_pciex_port *port)
741{
a2d2e1ec
BH		 742 /* XXX Check what that value means... I hate magic */
743 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x68782800);
744
a2d2e1ec
BH		 745 /*
746 * Set buffer allocations and then assert VRB and TXE.
747 */
035ee428
BH		 748 out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000);
749 out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
750 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x10000000);
751 out_be32(port->utl_base + PEUTL_PBBSZ, 0x53000000);
752 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x08000000);
753 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x10000000);
754 out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000);
755 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
a2d2e1ec 756
035ee428
BH		 757 return 0;
758}
759
760static int ppc440speB_pciex_init_utl(struct ppc4xx_pciex_port *port)
761{
762 /* Report CRS to the operating system */
763 out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000);
a2d2e1ec
BH		 764
765 return 0;
766}
767
768static struct ppc4xx_pciex_hwops ppc440speA_pcie_hwops __initdata =
769{
770 .core_init = ppc440spe_pciex_core_init,
035ee428 771 .port_init_hw = ppc440speA_pciex_init_port_hw,
a2d2e1ec
BH		 772 .setup_utl = ppc440speA_pciex_init_utl,
773};
774
775static struct ppc4xx_pciex_hwops ppc440speB_pcie_hwops __initdata =
776{
777 .core_init = ppc440spe_pciex_core_init,
035ee428
BH		 778 .port_init_hw = ppc440speB_pciex_init_port_hw,
779 .setup_utl = ppc440speB_pciex_init_utl,
a2d2e1ec
BH		 780};
781
66b7e504
SR		 782static int __init ppc460ex_pciex_core_init(struct device_node *np)
783{
784 /* Nothing to do, return 2 ports */
785 return 2;
786}
787
788static int ppc460ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
789{
790 u32 val;
791 u32 utlset1;
792
5f91925c 793 if (port->endpoint)
66b7e504 794 val = PTYPE_LEGACY_ENDPOINT << 20;
5f91925c 795 else
66b7e504 796 val = PTYPE_ROOT_PORT << 20;
66b7e504
SR		 797
798 if (port->index == 0) {
799 val |= LNKW_X1 << 12;
5f91925c 800 utlset1 = 0x20000000;
66b7e504
SR		 801 } else {
802 val |= LNKW_X4 << 12;
5f91925c 803 utlset1 = 0x20101101;
66b7e504
SR		 804 }
805
806 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
807 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, utlset1);
808 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01210000);
809
810 switch (port->index) {
811 case 0:
812 mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230);
813 mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000136);
814 mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006);
815
816 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST,0x10000000);
817 break;
818
819 case 1:
820 mtdcri(SDR0, PESDR1_460EX_L0CDRCTL, 0x00003230);
821 mtdcri(SDR0, PESDR1_460EX_L1CDRCTL, 0x00003230);
822 mtdcri(SDR0, PESDR1_460EX_L2CDRCTL, 0x00003230);
823 mtdcri(SDR0, PESDR1_460EX_L3CDRCTL, 0x00003230);
824 mtdcri(SDR0, PESDR1_460EX_L0DRV, 0x00000136);
825 mtdcri(SDR0, PESDR1_460EX_L1DRV, 0x00000136);
826 mtdcri(SDR0, PESDR1_460EX_L2DRV, 0x00000136);
827 mtdcri(SDR0, PESDR1_460EX_L3DRV, 0x00000136);
828 mtdcri(SDR0, PESDR1_460EX_L0CLK, 0x00000006);
829 mtdcri(SDR0, PESDR1_460EX_L1CLK, 0x00000006);
830 mtdcri(SDR0, PESDR1_460EX_L2CLK, 0x00000006);
831 mtdcri(SDR0, PESDR1_460EX_L3CLK, 0x00000006);
832
833 mtdcri(SDR0, PESDR1_460EX_PHY_CTL_RST,0x10000000);
834 break;
835 }
836
837 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
838 mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |
839 (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN));
840
841 /* Poll for PHY reset */
842 /* XXX FIXME add timeout */
843 switch (port->index) {
844 case 0:
845 while (!(mfdcri(SDR0, PESDR0_460EX_RSTSTA) & 0x1))
846 udelay(10);
847 break;
848 case 1:
849 while (!(mfdcri(SDR0, PESDR1_460EX_RSTSTA) & 0x1))
850 udelay(10);
851 break;
852 }
853
854 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
855 (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) &
856 ~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) |
857 PESDRx_RCSSET_RSTPYN);
858
859 port->has_ibpre = 1;
860
861 return 0;
862}
863
864static int ppc460ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
865{
866 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0);
867
868 /*
869 * Set buffer allocations and then assert VRB and TXE.
870 */
871 out_be32(port->utl_base + PEUTL_PBCTL, 0x0800000c);
872 out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000);
873 out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
874 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000);
875 out_be32(port->utl_base + PEUTL_PBBSZ, 0x00000000);
876 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000);
877 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000);
878 out_be32(port->utl_base + PEUTL_RCIRQEN,0x00f00000);
879 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
880
881 return 0;
882}
883
884static struct ppc4xx_pciex_hwops ppc460ex_pcie_hwops __initdata =
885{
886 .core_init = ppc460ex_pciex_core_init,
887 .port_init_hw = ppc460ex_pciex_init_port_hw,
888 .setup_utl = ppc460ex_pciex_init_utl,
889};
890
a2d2e1ec
BH		 891#endif /* CONFIG_44x */
892
893#ifdef CONFIG_40x
894
895static int __init ppc405ex_pciex_core_init(struct device_node *np)
896{
897 /* Nothing to do, return 2 ports */
898 return 2;
899}
900
901static void ppc405ex_pcie_phy_reset(struct ppc4xx_pciex_port *port)
902{
903 /* Assert the PE0_PHY reset */
904 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01010000);
905 msleep(1);
906
907 /* deassert the PE0_hotreset */
908 if (port->endpoint)
909 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01111000);
910 else
911 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01101000);
912
913 /* poll for phy !reset */
914 /* XXX FIXME add timeout */
915 while (!(mfdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSTA) & 0x00001000))
916 ;
917
918 /* deassert the PE0_gpl_utl_reset */
919 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x00101000);
920}
921
922static int ppc405ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
923{
924 u32 val;
925
926 if (port->endpoint)
927 val = PTYPE_LEGACY_ENDPOINT;
928 else
929 val = PTYPE_ROOT_PORT;
930
931 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET,
932 1 << 24 | val << 20 | LNKW_X1 << 12);
933
934 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000);
935 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000);
936 mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET1, 0x720F0000);
937 mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET2, 0x70600003);
938
939 /*
940 * Only reset the PHY when no link is currently established.
941 * This is for the Atheros PCIe board which has problems to establish
942 * the link (again) after this PHY reset. All other currently tested
943 * PCIe boards don't show this problem.
944 * This has to be re-tested and fixed in a later release!
945 */
a2d2e1ec
BH		 946 val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
947 if (!(val & 0x00001000))
948 ppc405ex_pcie_phy_reset(port);
a2d2e1ec
BH		 949
950 dcr_write(port->dcrs, DCRO_PEGPL_CFG, 0x10000000); /* guarded on */
951
55aaf6ec
SR		 952 port->has_ibpre = 1;
953
a2d2e1ec
BH		 954 return 0;
955}
956
957static int ppc405ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
958{
a2d2e1ec
BH		 959 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0);
960
a2d2e1ec
BH		 961 /*
962 * Set buffer allocations and then assert VRB and TXE.
963 */
035ee428
BH		 964 out_be32(port->utl_base + PEUTL_OUTTR, 0x02000000);
965 out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
966 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000);
967 out_be32(port->utl_base + PEUTL_PBBSZ, 0x21000000);
968 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000);
969 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000);
970 out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000);
971 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
a2d2e1ec 972
035ee428 973 out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000);
a2d2e1ec
BH		 974
975 return 0;
976}
977
978static struct ppc4xx_pciex_hwops ppc405ex_pcie_hwops __initdata =
979{
980 .core_init = ppc405ex_pciex_core_init,
981 .port_init_hw = ppc405ex_pciex_init_port_hw,
982 .setup_utl = ppc405ex_pciex_init_utl,
983};
984
985#endif /* CONFIG_40x */
986
987
988/* Check that the core has been initied and if not, do it */
989static int __init ppc4xx_pciex_check_core_init(struct device_node *np)
990{
991 static int core_init;
992 int count = -ENODEV;
993
994 if (core_init++)
995 return 0;
996
997#ifdef CONFIG_44x
accf5ef2
SR		 998 if (of_device_is_compatible(np, "ibm,plb-pciex-440spe")) {
999 if (ppc440spe_revA())
1000 ppc4xx_pciex_hwops = &ppc440speA_pcie_hwops;
1001 else
1002 ppc4xx_pciex_hwops = &ppc440speB_pcie_hwops;
1003 }
66b7e504
SR		 1004 if (of_device_is_compatible(np, "ibm,plb-pciex-460ex"))
1005 ppc4xx_pciex_hwops = &ppc460ex_pcie_hwops;
a2d2e1ec
BH		 1006#endif /* CONFIG_44x */
1007#ifdef CONFIG_40x
1008 if (of_device_is_compatible(np, "ibm,plb-pciex-405ex"))
1009 ppc4xx_pciex_hwops = &ppc405ex_pcie_hwops;
1010#endif
1011 if (ppc4xx_pciex_hwops == NULL) {
1012 printk(KERN_WARNING "PCIE: unknown host type %s\n",
1013 np->full_name);
1014 return -ENODEV;
1015 }
1016
1017 count = ppc4xx_pciex_hwops->core_init(np);
1018 if (count > 0) {
1019 ppc4xx_pciex_ports =
1020 kzalloc(count * sizeof(struct ppc4xx_pciex_port),
1021 GFP_KERNEL);
1022 if (ppc4xx_pciex_ports) {
1023 ppc4xx_pciex_port_count = count;
1024 return 0;
1025 }
1026 printk(KERN_WARNING "PCIE: failed to allocate ports array\n");
1027 return -ENOMEM;
1028 }
1029 return -ENODEV;
1030}
1031
1032static void __init ppc4xx_pciex_port_init_mapping(struct ppc4xx_pciex_port *port)
1033{
1034 /* We map PCI Express configuration based on the reg property */
1035 dcr_write(port->dcrs, DCRO_PEGPL_CFGBAH,
1036 RES_TO_U32_HIGH(port->cfg_space.start));
1037 dcr_write(port->dcrs, DCRO_PEGPL_CFGBAL,
1038 RES_TO_U32_LOW(port->cfg_space.start));
1039
1040 /* XXX FIXME: Use size from reg property. For now, map 512M */
1041 dcr_write(port->dcrs, DCRO_PEGPL_CFGMSK, 0xe0000001);
1042
1043 /* We map UTL registers based on the reg property */
1044 dcr_write(port->dcrs, DCRO_PEGPL_REGBAH,
1045 RES_TO_U32_HIGH(port->utl_regs.start));
1046 dcr_write(port->dcrs, DCRO_PEGPL_REGBAL,
1047 RES_TO_U32_LOW(port->utl_regs.start));
1048
1049 /* XXX FIXME: Use size from reg property */
1050 dcr_write(port->dcrs, DCRO_PEGPL_REGMSK, 0x00007001);
1051
1052 /* Disable all other outbound windows */
1053 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, 0);
1054 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, 0);
1055 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, 0);
1056 dcr_write(port->dcrs, DCRO_PEGPL_MSGMSK, 0);
1057}
1058
035ee428
BH		 1059static int __init ppc4xx_pciex_wait_on_sdr(struct ppc4xx_pciex_port *port,
1060 unsigned int sdr_offset,
1061 unsigned int mask,
1062 unsigned int value,
1063 int timeout_ms)
a2d2e1ec 1064{
a2d2e1ec
BH		 1065 u32 val;
1066
035ee428
BH		 1067 while(timeout_ms--) {
1068 val = mfdcri(SDR0, port->sdr_base + sdr_offset);
1069 if ((val & mask) == value) {
1070 pr_debug("PCIE%d: Wait on SDR %x success with tm %d (%08x)\n",
1071 port->index, sdr_offset, timeout_ms, val);
1072 return 0;
1073 }
1074 msleep(1);
1075 }
1076 return -1;
1077}
1078
1079static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port)
1080{
1081 int rc = 0;
a2d2e1ec
BH		 1082
1083 /* Init HW */
1084 if (ppc4xx_pciex_hwops->port_init_hw)
1085 rc = ppc4xx_pciex_hwops->port_init_hw(port);
1086 if (rc != 0)
1087 return rc;
1088
035ee428 1089 printk(KERN_INFO "PCIE%d: Checking link...\n",
a2d2e1ec 1090 port->index);
a2d2e1ec 1091
035ee428
BH		 1092 /* Wait for reset to complete */
1093 if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS, 1 << 20, 0, 10)) {
1094 printk(KERN_WARNING "PCIE%d: PGRST failed\n",
1095 port->index);
a2d2e1ec
BH		 1096 return -1;
1097 }
1098
035ee428
BH		 1099 /* Check for card presence detect if supported, if not, just wait for
1100 * link unconditionally.
1101 *
1102 * note that we don't fail if there is no link, we just filter out
1103 * config space accesses. That way, it will be easier to implement
1104 * hotplug later on.
a2d2e1ec 1105 */
035ee428
BH		 1106 if (!port->has_ibpre ||
1107 !ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
1108 1 << 28, 1 << 28, 100)) {
1109 printk(KERN_INFO
1110 "PCIE%d: Device detected, waiting for link...\n",
a2d2e1ec 1111 port->index);
035ee428
BH		 1112 if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
1113 0x1000, 0x1000, 2000))
1114 printk(KERN_WARNING
1115 "PCIE%d: Link up failed\n", port->index);
1116 else {
1117 printk(KERN_INFO
1118 "PCIE%d: link is up !\n", port->index);
1119 port->link = 1;
1120 }
1121 } else
1122 printk(KERN_INFO "PCIE%d: No device detected.\n", port->index);
a2d2e1ec
BH		 1123
1124 /*
1125 * Initialize mapping: disable all regions and configure
1126 * CFG and REG regions based on resources in the device tree
1127 */
1128 ppc4xx_pciex_port_init_mapping(port);
1129
1130 /*
035ee428
BH		 1131 * Map UTL
1132 */
1133 port->utl_base = ioremap(port->utl_regs.start, 0x100);
1134 BUG_ON(port->utl_base == NULL);
1135
1136 /*
1137 * Setup UTL registers --BenH.
a2d2e1ec
BH		 1138 */
1139 if (ppc4xx_pciex_hwops->setup_utl)
1140 ppc4xx_pciex_hwops->setup_utl(port);
1141
1142 /*
1143 * Check for VC0 active and assert RDY.
1144 */
035ee428
BH		 1145 if (port->link &&
1146 ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS,
1147 1 << 16, 1 << 16, 5000)) {
1148 printk(KERN_INFO "PCIE%d: VC0 not active\n", port->index);
1149 port->link = 0;
a2d2e1ec 1150 }
035ee428 1151
6e42b21b 1152 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20);
a2d2e1ec
BH		 1153 msleep(100);
1154
1155 return 0;
1156}
1157
1158static int ppc4xx_pciex_validate_bdf(struct ppc4xx_pciex_port *port,
1159 struct pci_bus *bus,
1160 unsigned int devfn)
1161{
1162 static int message;
1163
1164 /* Endpoint can not generate upstream(remote) config cycles */
1165 if (port->endpoint && bus->number != port->hose->first_busno)
1166 return PCIBIOS_DEVICE_NOT_FOUND;
1167
1168 /* Check we are within the mapped range */
1169 if (bus->number > port->hose->last_busno) {
1170 if (!message) {
1171 printk(KERN_WARNING "Warning! Probing bus %u"
1172 " out of range !\n", bus->number);
1173 message++;
1174 }
1175 return PCIBIOS_DEVICE_NOT_FOUND;
1176 }
1177
1178 /* The root complex has only one device / function */
1179 if (bus->number == port->hose->first_busno && devfn != 0)
1180 return PCIBIOS_DEVICE_NOT_FOUND;
1181
1182 /* The other side of the RC has only one device as well */
1183 if (bus->number == (port->hose->first_busno + 1) &&
1184 PCI_SLOT(devfn) != 0)
1185 return PCIBIOS_DEVICE_NOT_FOUND;
1186
035ee428
BH		 1187 /* Check if we have a link */
1188 if ((bus->number != port->hose->first_busno) && !port->link)
1189 return PCIBIOS_DEVICE_NOT_FOUND;
1190
a2d2e1ec
BH		 1191 return 0;
1192}
1193
1194static void __iomem *ppc4xx_pciex_get_config_base(struct ppc4xx_pciex_port *port,
1195 struct pci_bus *bus,
1196 unsigned int devfn)
1197{
1198 int relbus;
1199
1200 /* Remove the casts when we finally remove the stupid volatile
1201 * in struct pci_controller
1202 */
1203 if (bus->number == port->hose->first_busno)
1204 return (void __iomem *)port->hose->cfg_addr;
1205
1206 relbus = bus->number - (port->hose->first_busno + 1);
1207 return (void __iomem *)port->hose->cfg_data +
1208 ((relbus << 20) | (devfn << 12));
1209}
1210
1211static int ppc4xx_pciex_read_config(struct pci_bus *bus, unsigned int devfn,
1212 int offset, int len, u32 *val)
1213{
1214 struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
1215 struct ppc4xx_pciex_port *port =
1216 &ppc4xx_pciex_ports[hose->indirect_type];
1217 void __iomem *addr;
1218 u32 gpl_cfg;
1219
1220 BUG_ON(hose != port->hose);
1221
1222 if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0)
1223 return PCIBIOS_DEVICE_NOT_FOUND;
1224
1225 addr = ppc4xx_pciex_get_config_base(port, bus, devfn);
1226
1227 /*
1228 * Reading from configuration space of non-existing device can
1229 * generate transaction errors. For the read duration we suppress
1230 * assertion of machine check exceptions to avoid those.
1231 */
1232 gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG);
1233 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA);
1234
035ee428
BH		 1235 /* Make sure no CRS is recorded */
1236 out_be32(port->utl_base + PEUTL_RCSTA, 0x00040000);
1237
a2d2e1ec
BH		 1238 switch (len) {
1239 case 1:
1240 *val = in_8((u8 *)(addr + offset));
1241 break;
1242 case 2:
1243 *val = in_le16((u16 *)(addr + offset));
1244 break;
1245 default:
1246 *val = in_le32((u32 *)(addr + offset));
1247 break;
1248 }
1249
1250 pr_debug("pcie-config-read: bus=%3d [%3d..%3d] devfn=0x%04x"
1251 " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n",
1252 bus->number, hose->first_busno, hose->last_busno,
1253 devfn, offset, len, addr + offset, *val);
1254
035ee428
BH		 1255 /* Check for CRS (440SPe rev B does that for us but heh ..) */
1256 if (in_be32(port->utl_base + PEUTL_RCSTA) & 0x00040000) {
1257 pr_debug("Got CRS !\n");
1258 if (len != 4 || offset != 0)
1259 return PCIBIOS_DEVICE_NOT_FOUND;
1260 *val = 0xffff0001;
1261 }
1262
a2d2e1ec
BH		 1263 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg);
1264
1265 return PCIBIOS_SUCCESSFUL;
1266}
1267
1268static int ppc4xx_pciex_write_config(struct pci_bus *bus, unsigned int devfn,
1269 int offset, int len, u32 val)
1270{
1271 struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
1272 struct ppc4xx_pciex_port *port =
1273 &ppc4xx_pciex_ports[hose->indirect_type];
1274 void __iomem *addr;
1275 u32 gpl_cfg;
1276
1277 if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0)
1278 return PCIBIOS_DEVICE_NOT_FOUND;
1279
1280 addr = ppc4xx_pciex_get_config_base(port, bus, devfn);
1281
1282 /*
1283 * Reading from configuration space of non-existing device can
1284 * generate transaction errors. For the read duration we suppress
1285 * assertion of machine check exceptions to avoid those.
1286 */
1287 gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG);
1288 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA);
1289
1290 pr_debug("pcie-config-write: bus=%3d [%3d..%3d] devfn=0x%04x"
1291 " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n",
1292 bus->number, hose->first_busno, hose->last_busno,
1293 devfn, offset, len, addr + offset, val);
1294
1295 switch (len) {
1296 case 1:
1297 out_8((u8 *)(addr + offset), val);
1298 break;
1299 case 2:
1300 out_le16((u16 *)(addr + offset), val);
1301 break;
1302 default:
1303 out_le32((u32 *)(addr + offset), val);
1304 break;
1305 }
1306
1307 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg);
1308
1309 return PCIBIOS_SUCCESSFUL;
1310}
1311
1312static struct pci_ops ppc4xx_pciex_pci_ops =
1313{
1314 .read = ppc4xx_pciex_read_config,
1315 .write = ppc4xx_pciex_write_config,
1316};
1317
1318static void __init ppc4xx_configure_pciex_POMs(struct ppc4xx_pciex_port *port,
1319 struct pci_controller *hose,
1320 void __iomem *mbase)
1321{
1322 u32 lah, lal, pciah, pcial, sa;
1323 int i, j;
1324
1325 /* Setup outbound memory windows */
1326 for (i = j = 0; i < 3; i++) {
1327 struct resource *res = &hose->mem_resources[i];
1328
1329 /* we only care about memory windows */
1330 if (!(res->flags & IORESOURCE_MEM))
1331 continue;
1332 if (j > 1) {
1333 printk(KERN_WARNING "%s: Too many ranges\n",
1334 port->node->full_name);
1335 break;
1336 }
1337
1338 /* Calculate register values */
1339 lah = RES_TO_U32_HIGH(res->start);
1340 lal = RES_TO_U32_LOW(res->start);
1341 pciah = RES_TO_U32_HIGH(res->start - hose->pci_mem_offset);
1342 pcial = RES_TO_U32_LOW(res->start - hose->pci_mem_offset);
1343 sa = res->end + 1 - res->start;
1344 if (!is_power_of_2(sa) || sa < 0x100000 ||
1345 sa > 0xffffffffu) {
1346 printk(KERN_WARNING "%s: Resource out of range\n",
1347 port->node->full_name);
1348 continue;
1349 }
1350 sa = (0xffffffffu << ilog2(sa)) | 0x1;
1351
1352 /* Program register values */
1353 switch (j) {
1354 case 0:
1355 out_le32(mbase + PECFG_POM0LAH, pciah);
1356 out_le32(mbase + PECFG_POM0LAL, pcial);
1357 dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAH, lah);
1358 dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAL, lal);
1359 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKH, 0x7fffffff);
1360 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, sa | 3);
1361 break;
1362 case 1:
1363 out_le32(mbase + PECFG_POM1LAH, pciah);
1364 out_le32(mbase + PECFG_POM1LAL, pcial);
1365 dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAH, lah);
1366 dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAL, lal);
1367 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKH, 0x7fffffff);
1368 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, sa | 3);
1369 break;
1370 }
1371 j++;
1372 }
1373
1374 /* Configure IO, always 64K starting at 0 */
1375 if (hose->io_resource.flags & IORESOURCE_IO) {
1376 lah = RES_TO_U32_HIGH(hose->io_base_phys);
1377 lal = RES_TO_U32_LOW(hose->io_base_phys);
1378 out_le32(mbase + PECFG_POM2LAH, 0);
1379 out_le32(mbase + PECFG_POM2LAL, 0);
1380 dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAH, lah);
1381 dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAL, lal);
1382 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKH, 0x7fffffff);
1383 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, 0xffff0000 | 3);
1384 }
1385}
1386
1387static void __init ppc4xx_configure_pciex_PIMs(struct ppc4xx_pciex_port *port,
1388 struct pci_controller *hose,
1389 void __iomem *mbase,
1390 struct resource *res)
1391{
1392 resource_size_t size = res->end - res->start + 1;
1393 u64 sa;
1394
80daac3f
SR		 1395 if (port->endpoint) {
1396 resource_size_t ep_addr = 0;
1397 resource_size_t ep_size = 32 << 20;
1398
1399 /* Currently we map a fixed 64MByte window to PLB address
1400 * 0 (SDRAM). This should probably be configurable via a dts
1401 * property.
1402 */
1403
1404 /* Calculate window size */
1405 sa = (0xffffffffffffffffull << ilog2(ep_size));;
1406
1407 /* Setup BAR0 */
1408 out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa));
1409 out_le32(mbase + PECFG_BAR0LMPA, RES_TO_U32_LOW(sa) |
1410 PCI_BASE_ADDRESS_MEM_TYPE_64);
a2d2e1ec 1411
80daac3f
SR		 1412 /* Disable BAR1 & BAR2 */
1413 out_le32(mbase + PECFG_BAR1MPA, 0);
1414 out_le32(mbase + PECFG_BAR2HMPA, 0);
1415 out_le32(mbase + PECFG_BAR2LMPA, 0);
a2d2e1ec 1416
80daac3f
SR		 1417 out_le32(mbase + PECFG_PIM01SAH, RES_TO_U32_HIGH(sa));
1418 out_le32(mbase + PECFG_PIM01SAL, RES_TO_U32_LOW(sa));
1419
1420 out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(ep_addr));
1421 out_le32(mbase + PCI_BASE_ADDRESS_1, RES_TO_U32_HIGH(ep_addr));
1422 } else {
1423 /* Calculate window size */
1424 sa = (0xffffffffffffffffull << ilog2(size));;
1425 if (res->flags & IORESOURCE_PREFETCH)
1426 sa |= 0x8;
1427
1428 out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa));
1429 out_le32(mbase + PECFG_BAR0LMPA, RES_TO_U32_LOW(sa));
1430
1431 /* The setup of the split looks weird to me ... let's see
1432 * if it works
1433 */
1434 out_le32(mbase + PECFG_PIM0LAL, 0x00000000);
1435 out_le32(mbase + PECFG_PIM0LAH, 0x00000000);
1436 out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
1437 out_le32(mbase + PECFG_PIM1LAH, 0x00000000);
1438 out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);
1439 out_le32(mbase + PECFG_PIM01SAL, 0x00000000);
1440
1441 out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(res->start));
1442 out_le32(mbase + PCI_BASE_ADDRESS_1, RES_TO_U32_HIGH(res->start));
1443 }
a2d2e1ec
BH		 1444
1445 /* Enable inbound mapping */
1446 out_le32(mbase + PECFG_PIMEN, 0x1);
1447
a2d2e1ec
BH		 1448 /* Enable I/O, Mem, and Busmaster cycles */
1449 out_le16(mbase + PCI_COMMAND,
1450 in_le16(mbase + PCI_COMMAND) |
1451 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
1452}
1453
1454static void __init ppc4xx_pciex_port_setup_hose(struct ppc4xx_pciex_port *port)
1455{
1456 struct resource dma_window;
1457 struct pci_controller *hose = NULL;
1458 const int *bus_range;
1459 int primary = 0, busses;
1460 void __iomem *mbase = NULL, *cfg_data = NULL;
80daac3f
SR		 1461 const u32 *pval;
1462 u32 val;
a2d2e1ec
BH		 1463
1464 /* Check if primary bridge */
1465 if (of_get_property(port->node, "primary", NULL))
1466 primary = 1;
1467
1468 /* Get bus range if any */
1469 bus_range = of_get_property(port->node, "bus-range", NULL);
1470
1471 /* Allocate the host controller data structure */
1472 hose = pcibios_alloc_controller(port->node);
1473 if (!hose)
1474 goto fail;
1475
1476 /* We stick the port number in "indirect_type" so the config space
1477 * ops can retrieve the port data structure easily
1478 */
1479 hose->indirect_type = port->index;
1480
1481 /* Get bus range */
1482 hose->first_busno = bus_range ? bus_range[0] : 0x0;
1483 hose->last_busno = bus_range ? bus_range[1] : 0xff;
1484
1485 /* Because of how big mapping the config space is (1M per bus), we
1486 * limit how many busses we support. In the long run, we could replace
1487 * that with something akin to kmap_atomic instead. We set aside 1 bus
1488 * for the host itself too.
1489 */
1490 busses = hose->last_busno - hose->first_busno; /* This is off by 1 */
1491 if (busses > MAX_PCIE_BUS_MAPPED) {
1492 busses = MAX_PCIE_BUS_MAPPED;
1493 hose->last_busno = hose->first_busno + busses;
1494 }
1495
80daac3f
SR		 1496 if (!port->endpoint) {
1497 /* Only map the external config space in cfg_data for
1498 * PCIe root-complexes. External space is 1M per bus
1499 */
1500 cfg_data = ioremap(port->cfg_space.start +
1501 (hose->first_busno + 1) * 0x100000,
1502 busses * 0x100000);
1503 if (cfg_data == NULL) {
1504 printk(KERN_ERR "%s: Can't map external config space !",
1505 port->node->full_name);
1506 goto fail;
1507 }
1508 hose->cfg_data = cfg_data;
1509 }
1510
1511 /* Always map the host config space in cfg_addr.
1512 * Internal space is 4K
a2d2e1ec 1513 */
a2d2e1ec 1514 mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000);
80daac3f
SR		 1515 if (mbase == NULL) {
1516 printk(KERN_ERR "%s: Can't map internal config space !",
a2d2e1ec
BH		 1517 port->node->full_name);
1518 goto fail;
1519 }
a2d2e1ec
BH		 1520 hose->cfg_addr = mbase;
1521
1522 pr_debug("PCIE %s, bus %d..%d\n", port->node->full_name,
1523 hose->first_busno, hose->last_busno);
1524 pr_debug(" config space mapped at: root @0x%p, other @0x%p\n",
1525 hose->cfg_addr, hose->cfg_data);
1526
1527 /* Setup config space */
1528 hose->ops = &ppc4xx_pciex_pci_ops;
1529 port->hose = hose;
1530 mbase = (void __iomem *)hose->cfg_addr;
1531
80daac3f
SR		 1532 if (!port->endpoint) {
1533 /*
1534 * Set bus numbers on our root port
1535 */
1536 out_8(mbase + PCI_PRIMARY_BUS, hose->first_busno);
1537 out_8(mbase + PCI_SECONDARY_BUS, hose->first_busno + 1);
1538 out_8(mbase + PCI_SUBORDINATE_BUS, hose->last_busno);
1539 }
a2d2e1ec
BH		 1540
1541 /*
1542 * OMRs are already reset, also disable PIMs
1543 */
1544 out_le32(mbase + PECFG_PIMEN, 0);
1545
1546 /* Parse outbound mapping resources */
1547 pci_process_bridge_OF_ranges(hose, port->node, primary);
1548
1549 /* Parse inbound mapping resources */
1550 if (ppc4xx_parse_dma_ranges(hose, mbase, &dma_window) != 0)
1551 goto fail;
1552
1553 /* Configure outbound ranges POMs */
1554 ppc4xx_configure_pciex_POMs(port, hose, mbase);
1555
1556 /* Configure inbound ranges PIMs */
1557 ppc4xx_configure_pciex_PIMs(port, hose, mbase, &dma_window);
1558
1559 /* The root complex doesn't show up if we don't set some vendor
80daac3f
SR		 1560 * and device IDs into it. The defaults below are the same bogus
1561 * one that the initial code in arch/ppc had. This can be
1562 * overwritten by setting the "vendor-id/device-id" properties
1563 * in the pciex node.
a2d2e1ec 1564 */
a2d2e1ec 1565
80daac3f
SR		 1566 /* Get the (optional) vendor-/device-id from the device-tree */
1567 pval = of_get_property(port->node, "vendor-id", NULL);
1568 if (pval) {
1569 val = *pval;
1570 } else {
1571 if (!port->endpoint)
1572 val = 0xaaa0 + port->index;
1573 else
1574 val = 0xeee0 + port->index;
1575 }
1576 out_le16(mbase + 0x200, val);
1577
1578 pval = of_get_property(port->node, "device-id", NULL);
1579 if (pval) {
1580 val = *pval;
1581 } else {
1582 if (!port->endpoint)
1583 val = 0xbed0 + port->index;
1584 else
1585 val = 0xfed0 + port->index;
1586 }
1587 out_le16(mbase + 0x202, val);
1588
1589 if (!port->endpoint) {
1590 /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */
1591 out_le32(mbase + 0x208, 0x06040001);
1592
1593 printk(KERN_INFO "PCIE%d: successfully set as root-complex\n",
1594 port->index);
1595 } else {
1596 /* Set Class Code to Processor/PPC */
1597 out_le32(mbase + 0x208, 0x0b200001);
1598
1599 printk(KERN_INFO "PCIE%d: successfully set as endpoint\n",
1600 port->index);
1601 }
a2d2e1ec 1602
a2d2e1ec
BH		 1603 return;
1604 fail:
1605 if (hose)
1606 pcibios_free_controller(hose);
1607 if (cfg_data)
1608 iounmap(cfg_data);
1609 if (mbase)
1610 iounmap(mbase);
1611}
1612
5738ec6d
BH		 1613static void __init ppc4xx_probe_pciex_bridge(struct device_node *np)
1614{
a2d2e1ec
BH		 1615 struct ppc4xx_pciex_port *port;
1616 const u32 *pval;
1617 int portno;
1618 unsigned int dcrs;
80daac3f 1619 const char *val;
a2d2e1ec
BH		 1620
1621 /* First, proceed to core initialization as we assume there's
1622 * only one PCIe core in the system
1623 */
1624 if (ppc4xx_pciex_check_core_init(np))
1625 return;
1626
1627 /* Get the port number from the device-tree */
1628 pval = of_get_property(np, "port", NULL);
1629 if (pval == NULL) {
1630 printk(KERN_ERR "PCIE: Can't find port number for %s\n",
1631 np->full_name);
1632 return;
1633 }
1634 portno = *pval;
1635 if (portno >= ppc4xx_pciex_port_count) {
1636 printk(KERN_ERR "PCIE: port number out of range for %s\n",
1637 np->full_name);
1638 return;
1639 }
1640 port = &ppc4xx_pciex_ports[portno];
1641 port->index = portno;
995ada8d
SR		 1642
1643 /*
1644 * Check if device is enabled
1645 */
1646 if (!of_device_is_available(np)) {
1647 printk(KERN_INFO "PCIE%d: Port disabled via device-tree\n", port->index);
1648 return;
1649 }
1650
a2d2e1ec
BH		 1651 port->node = of_node_get(np);
1652 pval = of_get_property(np, "sdr-base", NULL);
1653 if (pval == NULL) {
1654 printk(KERN_ERR "PCIE: missing sdr-base for %s\n",
1655 np->full_name);
1656 return;
1657 }
1658 port->sdr_base = *pval;
1659
80daac3f
SR		 1660 /* Check if device_type property is set to "pci" or "pci-endpoint".
1661 * Resulting from this setup this PCIe port will be configured
1662 * as root-complex or as endpoint.
1663 */
1664 val = of_get_property(port->node, "device_type", NULL);
1665 if (!strcmp(val, "pci-endpoint")) {
1666 port->endpoint = 1;
1667 } else if (!strcmp(val, "pci")) {
1668 port->endpoint = 0;
1669 } else {
1670 printk(KERN_ERR "PCIE: missing or incorrect device_type for %s\n",
1671 np->full_name);
1672 return;
1673 }
035ee428 1674
a2d2e1ec
BH		 1675 /* Fetch config space registers address */
1676 if (of_address_to_resource(np, 0, &port->cfg_space)) {
1677 printk(KERN_ERR "%s: Can't get PCI-E config space !",
1678 np->full_name);
1679 return;
1680 }
1681 /* Fetch host bridge internal registers address */
1682 if (of_address_to_resource(np, 1, &port->utl_regs)) {
1683 printk(KERN_ERR "%s: Can't get UTL register base !",
1684 np->full_name);
1685 return;
1686 }
1687
1688 /* Map DCRs */
1689 dcrs = dcr_resource_start(np, 0);
1690 if (dcrs == 0) {
1691 printk(KERN_ERR "%s: Can't get DCR register base !",
1692 np->full_name);
1693 return;
1694 }
1695 port->dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
1696
1697 /* Initialize the port specific registers */
035ee428
BH		 1698 if (ppc4xx_pciex_port_init(port)) {
1699 printk(KERN_WARNING "PCIE%d: Port init failed\n", port->index);
a2d2e1ec 1700 return;
035ee428 1701 }
a2d2e1ec
BH		 1702
1703 /* Setup the linux hose data structure */
1704 ppc4xx_pciex_port_setup_hose(port);
5738ec6d
BH		 1705}
1706
a2d2e1ec
BH		 1707#endif /* CONFIG_PPC4xx_PCI_EXPRESS */
1708
5738ec6d
BH		 1709static int __init ppc4xx_pci_find_bridges(void)
1710{
1711 struct device_node *np;
1712
a2d2e1ec 1713#ifdef CONFIG_PPC4xx_PCI_EXPRESS
5738ec6d
BH		 1714 for_each_compatible_node(np, NULL, "ibm,plb-pciex")
1715 ppc4xx_probe_pciex_bridge(np);
a2d2e1ec 1716#endif
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BH		 1717 for_each_compatible_node(np, NULL, "ibm,plb-pcix")
1718 ppc4xx_probe_pcix_bridge(np);
1719 for_each_compatible_node(np, NULL, "ibm,plb-pci")
1720 ppc4xx_probe_pci_bridge(np);
1721
1722 return 0;
1723}
1724arch_initcall(ppc4xx_pci_find_bridges);
1725
Linux kernel - Deliverables
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