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[POWERPC] 4xx: Add PPC4xx L2-cache support (440GX)
[deliverable/linux.git] / arch / powerpc / sysdev / ppc4xx_soc.c
CommitLineData
2a706919
SR		 1/*
2 * IBM/AMCC PPC4xx SoC setup code
3 *
4 * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
5 *
6 * L2 cache routines cloned from arch/ppc/syslib/ibm440gx_common.c which is:
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 * Copyright (c) 2003 - 2006 Zultys Technologies
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <linux/stddef.h>
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/errno.h>
20#include <linux/interrupt.h>
21#include <linux/irq.h>
22#include <linux/of_platform.h>
23
24#include <asm/dcr.h>
25#include <asm/dcr-regs.h>
26
27static u32 dcrbase_l2c;
28
29/*
30 * L2-cache
31 */
32
33/* Issue L2C diagnostic command */
34static inline u32 l2c_diag(u32 addr)
35{
36 mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, addr);
37 mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_DIAG);
38 while (!(mfdcr(dcrbase_l2c + DCRN_L2C0_SR) & L2C_SR_CC))
39 ;
40
41 return mfdcr(dcrbase_l2c + DCRN_L2C0_DATA);
42}
43
44static irqreturn_t l2c_error_handler(int irq, void *dev)
45{
46 u32 sr = mfdcr(dcrbase_l2c + DCRN_L2C0_SR);
47
48 if (sr & L2C_SR_CPE) {
49 /* Read cache trapped address */
50 u32 addr = l2c_diag(0x42000000);
51 printk(KERN_EMERG "L2C: Cache Parity Error, addr[16:26] = 0x%08x\n",
52 addr);
53 }
54 if (sr & L2C_SR_TPE) {
55 /* Read tag trapped address */
56 u32 addr = l2c_diag(0x82000000) >> 16;
57 printk(KERN_EMERG "L2C: Tag Parity Error, addr[16:26] = 0x%08x\n",
58 addr);
59 }
60
61 /* Clear parity errors */
62 if (sr & (L2C_SR_CPE | L2C_SR_TPE)){
63 mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, 0);
64 mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_CCP | L2C_CMD_CTE);
65 } else {
66 printk(KERN_EMERG "L2C: LRU error\n");
67 }
68
69 return IRQ_HANDLED;
70}
71
72static int __init ppc4xx_l2c_probe(void)
73{
74 struct device_node *np;
75 u32 r;
76 unsigned long flags;
77 int irq;
78 const u32 *dcrreg;
79 u32 dcrbase_isram;
80 int len;
81 const u32 *prop;
82 u32 l2_size;
83
84 np = of_find_compatible_node(NULL, NULL, "ibm,l2-cache");
85 if (!np)
86 return 0;
87
88 /* Get l2 cache size */
89 prop = of_get_property(np, "cache-size", NULL);
90 if (prop == NULL) {
91 printk(KERN_ERR "%s: Can't get cache-size!\n", np->full_name);
92 of_node_put(np);
93 return -ENODEV;
94 }
95 l2_size = prop[0];
96
97 /* Map DCRs */
98 dcrreg = of_get_property(np, "dcr-reg", &len);
99 if (!dcrreg || (len != 4 * sizeof(u32))) {
100 printk(KERN_ERR "%s: Can't get DCR register base !",
101 np->full_name);
102 of_node_put(np);
103 return -ENODEV;
104 }
105 dcrbase_isram = dcrreg[0];
106 dcrbase_l2c = dcrreg[2];
107
108 /* Get and map irq number from device tree */
109 irq = irq_of_parse_and_map(np, 0);
110 if (irq == NO_IRQ) {
111 printk(KERN_ERR "irq_of_parse_and_map failed\n");
112 of_node_put(np);
113 return -ENODEV;
114 }
115
116 /* Install error handler */
117 if (request_irq(irq, l2c_error_handler, IRQF_DISABLED, "L2C", 0) < 0) {
118 printk(KERN_ERR "Cannot install L2C error handler"
119 ", cache is not enabled\n");
120 of_node_put(np);
121 return -ENODEV;
122 }
123
124 local_irq_save(flags);
125 asm volatile ("sync" ::: "memory");
126
127 /* Disable SRAM */
128 mtdcr(dcrbase_isram + DCRN_SRAM0_DPC,
129 mfdcr(dcrbase_isram + DCRN_SRAM0_DPC) & ~SRAM_DPC_ENABLE);
130 mtdcr(dcrbase_isram + DCRN_SRAM0_SB0CR,
131 mfdcr(dcrbase_isram + DCRN_SRAM0_SB0CR) & ~SRAM_SBCR_BU_MASK);
132 mtdcr(dcrbase_isram + DCRN_SRAM0_SB1CR,
133 mfdcr(dcrbase_isram + DCRN_SRAM0_SB1CR) & ~SRAM_SBCR_BU_MASK);
134 mtdcr(dcrbase_isram + DCRN_SRAM0_SB2CR,
135 mfdcr(dcrbase_isram + DCRN_SRAM0_SB2CR) & ~SRAM_SBCR_BU_MASK);
136 mtdcr(dcrbase_isram + DCRN_SRAM0_SB3CR,
137 mfdcr(dcrbase_isram + DCRN_SRAM0_SB3CR) & ~SRAM_SBCR_BU_MASK);
138
139 /* Enable L2_MODE without ICU/DCU */
140 r = mfdcr(dcrbase_l2c + DCRN_L2C0_CFG) &
141 ~(L2C_CFG_ICU | L2C_CFG_DCU | L2C_CFG_SS_MASK);
142 r |= L2C_CFG_L2M | L2C_CFG_SS_256;
143 mtdcr(dcrbase_l2c + DCRN_L2C0_CFG, r);
144
145 mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, 0);
146
147 /* Hardware Clear Command */
148 mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_HCC);
149 while (!(mfdcr(dcrbase_l2c + DCRN_L2C0_SR) & L2C_SR_CC))
150 ;
151
152 /* Clear Cache Parity and Tag Errors */
153 mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_CCP | L2C_CMD_CTE);
154
155 /* Enable 64G snoop region starting at 0 */
156 r = mfdcr(dcrbase_l2c + DCRN_L2C0_SNP0) &
157 ~(L2C_SNP_BA_MASK | L2C_SNP_SSR_MASK);
158 r |= L2C_SNP_SSR_32G | L2C_SNP_ESR;
159 mtdcr(dcrbase_l2c + DCRN_L2C0_SNP0, r);
160
161 r = mfdcr(dcrbase_l2c + DCRN_L2C0_SNP1) &
162 ~(L2C_SNP_BA_MASK | L2C_SNP_SSR_MASK);
163 r |= 0x80000000 | L2C_SNP_SSR_32G | L2C_SNP_ESR;
164 mtdcr(dcrbase_l2c + DCRN_L2C0_SNP1, r);
165
166 asm volatile ("sync" ::: "memory");
167
168 /* Enable ICU/DCU ports */
169 r = mfdcr(dcrbase_l2c + DCRN_L2C0_CFG);
170 r &= ~(L2C_CFG_DCW_MASK | L2C_CFG_PMUX_MASK | L2C_CFG_PMIM
171 | L2C_CFG_TPEI | L2C_CFG_CPEI | L2C_CFG_NAM | L2C_CFG_NBRM);
172 r |= L2C_CFG_ICU | L2C_CFG_DCU | L2C_CFG_TPC | L2C_CFG_CPC | L2C_CFG_FRAN
173 | L2C_CFG_CPIM | L2C_CFG_TPIM | L2C_CFG_LIM | L2C_CFG_SMCM;
174
175 /* Check for 460EX/GT special handling */
176 if (of_device_is_compatible(np, "ibm,l2-cache-460ex"))
177 r |= L2C_CFG_RDBW;
178
179 mtdcr(dcrbase_l2c + DCRN_L2C0_CFG, r);
180
181 asm volatile ("sync; isync" ::: "memory");
182 local_irq_restore(flags);
183
184 printk(KERN_INFO "%dk L2-cache enabled\n", l2_size >> 10);
185
186 of_node_put(np);
187 return 0;
188}
189arch_initcall(ppc4xx_l2c_probe);
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