[deliverable/linux.git] / arch / powerpc / sysdev / tsi108_pci.c

/*
 * Common routines for Tundra Semiconductor TSI108 host bridge.
 *
 * 2004-2005 (c) Tundra Semiconductor Corp.
 * Author: Alex Bounine (alexandreb@tundra.com)
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the Free
 * Software Foundation; either version 2 of the License, or (at your option)
 * any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc., 59
 * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/irq.h>
#include <linux/interrupt.h>

#include <asm/byteorder.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/uaccess.h>
#include <asm/machdep.h>
#include <asm/pci-bridge.h>
#include <asm/tsi108.h>
#include <asm/tsi108_irq.h>
#include <asm/prom.h>

#undef DEBUG
#ifdef DEBUG
#define DBG(x...) printk(x)
#else
#define DBG(x...)
#endif

#define tsi_mk_config_addr(bus, devfunc, offset) \
	((((bus)<<16) | ((devfunc)<<8) | (offset & 0xfc)) + tsi108_pci_cfg_base)

u32 tsi108_pci_cfg_base;
u32 tsi108_csr_vir_base;

extern u32 get_vir_csrbase(void);
extern u32 tsi108_read_reg(u32 reg_offset);
extern void tsi108_write_reg(u32 reg_offset, u32 val);

int
tsi108_direct_write_config(struct pci_bus *bus, unsigned int devfunc,
			   int offset, int len, u32 val)
{
	volatile unsigned char *cfg_addr;

	if (ppc_md.pci_exclude_device)
		if (ppc_md.pci_exclude_device(bus->number, devfunc))
			return PCIBIOS_DEVICE_NOT_FOUND;

	cfg_addr = (unsigned char *)(tsi_mk_config_addr(bus->number,
							devfunc, offset) |
							(offset & 0x03));

#ifdef DEBUG
	printk("PCI CFG write : ");
	printk("%d:0x%x:0x%x ", bus->number, devfunc, offset);
	printk("%d ADDR=0x%08x ", len, (uint) cfg_addr);
	printk("data = 0x%08x\n", val);
#endif

	switch (len) {
	case 1:
		out_8((u8 *) cfg_addr, val);
		break;
	case 2:
		out_le16((u16 *) cfg_addr, val);
		break;
	default:
		out_le32((u32 *) cfg_addr, val);
		break;
	}

	return PCIBIOS_SUCCESSFUL;
}

void tsi108_clear_pci_error(u32 pci_cfg_base)
{
	u32 err_stat, err_addr, pci_stat;

	/*
	 * Quietly clear PB and PCI error flags set as result
	 * of PCI/X configuration read requests.
	 */

	/* Read PB Error Log Registers */

	err_stat = tsi108_read_reg(TSI108_PB_OFFSET + TSI108_PB_ERRCS);
	err_addr = tsi108_read_reg(TSI108_PB_OFFSET + TSI108_PB_AERR);

	if (err_stat & TSI108_PB_ERRCS_ES) {
		/* Clear error flag */
		tsi108_write_reg(TSI108_PB_OFFSET + TSI108_PB_ERRCS,
				 TSI108_PB_ERRCS_ES);

		/* Clear read error reported in PB_ISR */
		tsi108_write_reg(TSI108_PB_OFFSET + TSI108_PB_ISR,
				 TSI108_PB_ISR_PBS_RD_ERR);

		/* Clear PCI/X bus cfg errors if applicable */
		if ((err_addr & 0xFF000000) == pci_cfg_base) {
			pci_stat =
			    tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_CSR);
			tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_CSR,
					 pci_stat);
		}
	}

	return;
}

#define __tsi108_read_pci_config(x, addr, op)		\
	__asm__ __volatile__(				\
		"	"op" %0,0,%1\n"		\
		"1:	eieio\n"			\
		"2:\n"					\
		".section .fixup,\"ax\"\n"		\
		"3:	li %0,-1\n"			\
		"	b 2b\n"				\
		".section __ex_table,\"a\"\n"		\
		"	.align 2\n"			\
		"	.long 1b,3b\n"			\
		".text"					\
		: "=r"(x) : "r"(addr))

int
tsi108_direct_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
			  int len, u32 * val)
{
	volatile unsigned char *cfg_addr;
	u32 temp;

	if (ppc_md.pci_exclude_device)
		if (ppc_md.pci_exclude_device(bus->number, devfn))
			return PCIBIOS_DEVICE_NOT_FOUND;

	cfg_addr = (unsigned char *)(tsi_mk_config_addr(bus->number,
							devfn,
							offset) | (offset &
								   0x03));

	switch (len) {
	case 1:
		__tsi108_read_pci_config(temp, cfg_addr, "lbzx");
		break;
	case 2:
		__tsi108_read_pci_config(temp, cfg_addr, "lhbrx");
		break;
	default:
		__tsi108_read_pci_config(temp, cfg_addr, "lwbrx");
		break;
	}

	*val = temp;

#ifdef DEBUG
	if ((0xFFFFFFFF != temp) && (0xFFFF != temp) && (0xFF != temp)) {
		printk("PCI CFG read : ");
		printk("%d:0x%x:0x%x ", bus->number, devfn, offset);
		printk("%d ADDR=0x%08x ", len, (uint) cfg_addr);
		printk("data = 0x%x\n", *val);
	}
#endif
	return PCIBIOS_SUCCESSFUL;
}

void tsi108_clear_pci_cfg_error(void)
{
	tsi108_clear_pci_error(TSI108_PCI_CFG_BASE_PHYS);
}

static struct pci_ops tsi108_direct_pci_ops = {
	tsi108_direct_read_config,
	tsi108_direct_write_config
};

int __init tsi108_setup_pci(struct device_node *dev)
{
	int len;
	struct pci_controller *hose;
	struct resource rsrc;
	const int *bus_range;
	int primary = 0, has_address = 0;

	/* PCI Config mapping */
	tsi108_pci_cfg_base = (u32)ioremap(TSI108_PCI_CFG_BASE_PHYS,
			TSI108_PCI_CFG_SIZE);
	DBG("TSI_PCI: %s tsi108_pci_cfg_base=0x%x\n", __FUNCTION__,
	    tsi108_pci_cfg_base);

	/* Fetch host bridge registers address */
	has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);

	/* Get bus range if any */
	bus_range = get_property(dev, "bus-range", &len);
	if (bus_range == NULL || len < 2 * sizeof(int)) {
		printk(KERN_WARNING "Can't get bus-range for %s, assume"
		       " bus 0\n", dev->full_name);
	}

	hose = pcibios_alloc_controller();

	if (!hose) {
		printk("PCI Host bridge init failed\n");
		return -ENOMEM;
	}
	hose->arch_data = dev;
	hose->set_cfg_type = 1;

	hose->first_busno = bus_range ? bus_range[0] : 0;
	hose->last_busno = bus_range ? bus_range[1] : 0xff;

	(hose)->ops = &tsi108_direct_pci_ops;

	printk(KERN_INFO "Found tsi108 PCI host bridge at 0x%08x. "
	       "Firmware bus number: %d->%d\n",
	       rsrc.start, hose->first_busno, hose->last_busno);

	/* Interpret the "ranges" property */
	/* This also maps the I/O region and sets isa_io/mem_base */
	pci_process_bridge_OF_ranges(hose, dev, primary);
	return 0;
}

/*
 * Low level utility functions
 */

static void tsi108_pci_int_mask(u_int irq)
{
	u_int irp_cfg;
	int int_line = (irq - IRQ_PCI_INTAD_BASE);

	irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
	mb();
	irp_cfg |= (1 << int_line);	/* INTx_DIR = output */
	irp_cfg &= ~(3 << (8 + (int_line * 2)));	/* INTx_TYPE = unused */
	tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL, irp_cfg);
	mb();
	irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
}

static void tsi108_pci_int_unmask(u_int irq)
{
	u_int irp_cfg;
	int int_line = (irq - IRQ_PCI_INTAD_BASE);

	irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
	mb();
	irp_cfg &= ~(1 << int_line);
	irp_cfg |= (3 << (8 + (int_line * 2)));
	tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL, irp_cfg);
	mb();
}

static void init_pci_source(void)
{
	tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL,
			0x0000ff00);
	tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE,
			TSI108_PCI_IRP_ENABLE_P_INT);
	mb();
}

static inline unsigned int get_pci_source(void)
{
	u_int temp = 0;
	int irq = -1;
	int i;
	u_int pci_irp_stat;
	static int mask = 0;

	/* Read PCI/X block interrupt status register */
	pci_irp_stat = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_STAT);
	mb();

	if (pci_irp_stat & TSI108_PCI_IRP_STAT_P_INT) {
		/* Process Interrupt from PCI bus INTA# - INTD# lines */
		temp =
		    tsi108_read_reg(TSI108_PCI_OFFSET +
				    TSI108_PCI_IRP_INTAD) & 0xf;
		mb();
		for (i = 0; i < 4; i++, mask++) {
			if (temp & (1 << mask % 4)) {
				irq = IRQ_PCI_INTA + mask % 4;
				mask++;
				break;
			}
		}

		/* Disable interrupts from PCI block */
		temp = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE);
		tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE,
				temp & ~TSI108_PCI_IRP_ENABLE_P_INT);
		mb();
		(void)tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE);
		mb();
	}
#ifdef DEBUG
	else {
		printk("TSI108_PIC: error in TSI108_PCI_IRP_STAT\n");
		pci_irp_stat =
		    tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_STAT);
		temp =
		    tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_INTAD);
		mb();
		printk(">> stat=0x%08x intad=0x%08x ", pci_irp_stat, temp);
		temp =
		    tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
		mb();
		printk("cfg_ctl=0x%08x ", temp);
		temp =
		    tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE);
		mb();
		printk("irp_enable=0x%08x\n", temp);
	}
#endif	/* end of DEBUG */

	return irq;
}


/*
 * Linux descriptor level callbacks
 */

static void tsi108_pci_irq_enable(u_int irq)
{
	tsi108_pci_int_unmask(irq);
}

static void tsi108_pci_irq_disable(u_int irq)
{
	tsi108_pci_int_mask(irq);
}

static void tsi108_pci_irq_ack(u_int irq)
{
	tsi108_pci_int_mask(irq);
}

static void tsi108_pci_irq_end(u_int irq)
{
	tsi108_pci_int_unmask(irq);

	/* Enable interrupts from PCI block */
	tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE,
			 tsi108_read_reg(TSI108_PCI_OFFSET +
					 TSI108_PCI_IRP_ENABLE) |
			 TSI108_PCI_IRP_ENABLE_P_INT);
	mb();
}

/*
 * Interrupt controller descriptor for cascaded PCI interrupt controller.
 */

static struct irq_chip tsi108_pci_irq = {
	.typename = "tsi108_PCI_int",
	.mask = tsi108_pci_irq_disable,
	.ack = tsi108_pci_irq_ack,
	.end = tsi108_pci_irq_end,
	.unmask = tsi108_pci_irq_enable,
};

/*
 * Exported functions
 */

/*
 * The Tsi108 PCI interrupts initialization routine.
 *
 * The INTA# - INTD# interrupts on the PCI bus are reported by the PCI block
 * to the MPIC using single interrupt source (IRQ_TSI108_PCI). Therefore the
 * PCI block has to be treated as a cascaded interrupt controller connected
 * to the MPIC.
 */

void __init tsi108_pci_int_init(void)
{
	u_int i;

	DBG("Tsi108_pci_int_init: initializing PCI interrupts\n");

	for (i = 0; i < NUM_PCI_IRQS; i++) {
		irq_desc[i + IRQ_PCI_INTAD_BASE].chip = &tsi108_pci_irq;
		irq_desc[i + IRQ_PCI_INTAD_BASE].status |= IRQ_LEVEL;
	}

	init_pci_source();
}

void tsi108_irq_cascade(unsigned int irq, struct irq_desc *desc,
			    struct pt_regs *regs)
{
	unsigned int cascade_irq = get_pci_source();
	if (cascade_irq != NO_IRQ)
		generic_handle_irq(cascade_irq);
	desc->chip->eoi(irq);
}
Commit	Line	Data
2b9d7467 ZR	1	/*
	2	* Common routines for Tundra Semiconductor TSI108 host bridge.
	3	*
	4	* 2004-2005 (c) Tundra Semiconductor Corp.
	5	* Author: Alex Bounine (alexandreb@tundra.com)
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License as published by the Free
	9	* Software Foundation; either version 2 of the License, or (at your option)
	10	* any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful, but WITHOUT
	13	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	14	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	15	* more details.
	16	*
	17	* You should have received a copy of the GNU General Public License along with
	18	* this program; if not, write to the Free Software Foundation, Inc., 59
	19	* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	20	*/
	21
	22	#include <linux/kernel.h>
	23	#include <linux/init.h>
	24	#include <linux/pci.h>
	25	#include <linux/slab.h>
	26	#include <linux/irq.h>
	27	#include <linux/interrupt.h>
	28
2b9d7467 ZR	29	#include <asm/byteorder.h>
	30	#include <asm/io.h>
	31	#include <asm/irq.h>
	32	#include <asm/uaccess.h>
	33	#include <asm/machdep.h>
	34	#include <asm/pci-bridge.h>
	35	#include <asm/tsi108.h>
	36	#include <asm/tsi108_irq.h>
	37	#include <asm/prom.h>
	38
	39	#undef DEBUG
	40	#ifdef DEBUG
	41	#define DBG(x...) printk(x)
	42	#else
	43	#define DBG(x...)
	44	#endif
	45
	46	#define tsi_mk_config_addr(bus, devfunc, offset) \
	47	((((bus)<<16) \| ((devfunc)<<8) \| (offset & 0xfc)) + tsi108_pci_cfg_base)
	48
	49	u32 tsi108_pci_cfg_base;
	50	u32 tsi108_csr_vir_base;
	51
	52	extern u32 get_vir_csrbase(void);
	53	extern u32 tsi108_read_reg(u32 reg_offset);
	54	extern void tsi108_write_reg(u32 reg_offset, u32 val);
	55
	56	int
	57	tsi108_direct_write_config(struct pci_bus *bus, unsigned int devfunc,
	58	int offset, int len, u32 val)
	59	{
	60	volatile unsigned char *cfg_addr;
	61
	62	if (ppc_md.pci_exclude_device)
	63	if (ppc_md.pci_exclude_device(bus->number, devfunc))
	64	return PCIBIOS_DEVICE_NOT_FOUND;
	65
	66	cfg_addr = (unsigned char *)(tsi_mk_config_addr(bus->number,
	67	devfunc, offset) \|
	68	(offset & 0x03));
	69
	70	#ifdef DEBUG
	71	printk("PCI CFG write : ");
	72	printk("%d:0x%x:0x%x ", bus->number, devfunc, offset);
	73	printk("%d ADDR=0x%08x ", len, (uint) cfg_addr);
	74	printk("data = 0x%08x\n", val);
	75	#endif
	76
	77	switch (len) {
	78	case 1:
	79	out_8((u8 *) cfg_addr, val);
	80	break;
	81	case 2:
	82	out_le16((u16 *) cfg_addr, val);
	83	break;
	84	default:
	85	out_le32((u32 *) cfg_addr, val);
	86	break;
	87	}
	88
	89	return PCIBIOS_SUCCESSFUL;
	90	}
	91
	92	void tsi108_clear_pci_error(u32 pci_cfg_base)
93	{
94	u32 err_stat, err_addr, pci_stat;
95
96	/*
97	* Quietly clear PB and PCI error flags set as result
98	* of PCI/X configuration read requests.
99	*/
100
101	/* Read PB Error Log Registers */
102
103	err_stat = tsi108_read_reg(TSI108_PB_OFFSET + TSI108_PB_ERRCS);
104	err_addr = tsi108_read_reg(TSI108_PB_OFFSET + TSI108_PB_AERR);
105
106	if (err_stat & TSI108_PB_ERRCS_ES) {
107	/* Clear error flag */
108	tsi108_write_reg(TSI108_PB_OFFSET + TSI108_PB_ERRCS,
109	TSI108_PB_ERRCS_ES);
110
111	/* Clear read error reported in PB_ISR */
112	tsi108_write_reg(TSI108_PB_OFFSET + TSI108_PB_ISR,
113	TSI108_PB_ISR_PBS_RD_ERR);
114
115	/* Clear PCI/X bus cfg errors if applicable */
116	if ((err_addr & 0xFF000000) == pci_cfg_base) {
117	pci_stat =
118	tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_CSR);
119	tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_CSR,
120	pci_stat);
121	}
122	}
123
124	return;
125	}
126
127	#define __tsi108_read_pci_config(x, addr, op) \
128	__asm__ __volatile__( \
129	" "op" %0,0,%1\n" \
130	"1: eieio\n" \
131	"2:\n" \
132	".section .fixup,\"ax\"\n" \
133	"3: li %0,-1\n" \
134	" b 2b\n" \
135	".section __ex_table,\"a\"\n" \
136	" .align 2\n" \
137	" .long 1b,3b\n" \
138	".text" \
139	: "=r"(x) : "r"(addr))
140
141	int
142	tsi108_direct_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
143	int len, u32 * val)
144	{
145	volatile unsigned char *cfg_addr;
146	u32 temp;
147
148	if (ppc_md.pci_exclude_device)
149	if (ppc_md.pci_exclude_device(bus->number, devfn))
150	return PCIBIOS_DEVICE_NOT_FOUND;
151
152	cfg_addr = (unsigned char *)(tsi_mk_config_addr(bus->number,
153	devfn,
154	offset) \| (offset &
155	0x03));
156
157	switch (len) {
158	case 1:
159	__tsi108_read_pci_config(temp, cfg_addr, "lbzx");
160	break;
161	case 2:
162	__tsi108_read_pci_config(temp, cfg_addr, "lhbrx");
163	break;
164	default:
165	__tsi108_read_pci_config(temp, cfg_addr, "lwbrx");
166	break;
167	}
168
169	*val = temp;
170
171	#ifdef DEBUG
172	if ((0xFFFFFFFF != temp) && (0xFFFF != temp) && (0xFF != temp)) {
173	printk("PCI CFG read : ");
174	printk("%d:0x%x:0x%x ", bus->number, devfn, offset);
175	printk("%d ADDR=0x%08x ", len, (uint) cfg_addr);
176	printk("data = 0x%x\n", *val);
177	}
178	#endif
179	return PCIBIOS_SUCCESSFUL;
180	}
181
182	void tsi108_clear_pci_cfg_error(void)
183	{
184	tsi108_clear_pci_error(TSI108_PCI_CFG_BASE_PHYS);
185	}
186
187	static struct pci_ops tsi108_direct_pci_ops = {
188	tsi108_direct_read_config,
189	tsi108_direct_write_config
190	};
191
192	int __init tsi108_setup_pci(struct device_node *dev)
193	{
194	int len;
195	struct pci_controller *hose;
196	struct resource rsrc;
88c80594	197	const int *bus_range;
2b9d7467 ZR	198	int primary = 0, has_address = 0;
	199
	200	/* PCI Config mapping */
	201	tsi108_pci_cfg_base = (u32)ioremap(TSI108_PCI_CFG_BASE_PHYS,
	202	TSI108_PCI_CFG_SIZE);
	203	DBG("TSI_PCI: %s tsi108_pci_cfg_base=0x%x\n", __FUNCTION__,
	204	tsi108_pci_cfg_base);
	205
	206	/* Fetch host bridge registers address */
	207	has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
	208
	209	/* Get bus range if any */
88c80594	210	bus_range = get_property(dev, "bus-range", &len);
2b9d7467 ZR	211	if (bus_range == NULL \|\| len < 2 * sizeof(int)) {
	212	printk(KERN_WARNING "Can't get bus-range for %s, assume"
	213	" bus 0\n", dev->full_name);
	214	}
	215
	216	hose = pcibios_alloc_controller();
	217
	218	if (!hose) {
	219	printk("PCI Host bridge init failed\n");
	220	return -ENOMEM;
	221	}
	222	hose->arch_data = dev;
	223	hose->set_cfg_type = 1;
	224
	225	hose->first_busno = bus_range ? bus_range[0] : 0;
	226	hose->last_busno = bus_range ? bus_range[1] : 0xff;
	227
	228	(hose)->ops = &tsi108_direct_pci_ops;
	229
c4342ff9	230	printk(KERN_INFO "Found tsi108 PCI host bridge at 0x%08x. "
2b9d7467 ZR	231	"Firmware bus number: %d->%d\n",
	232	rsrc.start, hose->first_busno, hose->last_busno);
	233
	234	/* Interpret the "ranges" property */
	235	/* This also maps the I/O region and sets isa_io/mem_base */
	236	pci_process_bridge_OF_ranges(hose, dev, primary);
	237	return 0;
	238	}
	239
	240	/*
	241	* Low level utility functions
	242	*/
	243
	244	static void tsi108_pci_int_mask(u_int irq)
	245	{
	246	u_int irp_cfg;
	247	int int_line = (irq - IRQ_PCI_INTAD_BASE);
	248
	249	irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
	250	mb();
	251	irp_cfg \|= (1 << int_line); /* INTx_DIR = output */
	252	irp_cfg &= ~(3 << (8 + (int_line * 2))); /* INTx_TYPE = unused */
	253	tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL, irp_cfg);
	254	mb();
	255	irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
	256	}
	257
	258	static void tsi108_pci_int_unmask(u_int irq)
	259	{
	260	u_int irp_cfg;
	261	int int_line = (irq - IRQ_PCI_INTAD_BASE);
	262
	263	irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
	264	mb();
	265	irp_cfg &= ~(1 << int_line);
	266	irp_cfg \|= (3 << (8 + (int_line * 2)));
	267	tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL, irp_cfg);
	268	mb();
	269	}
	270
	271	static void init_pci_source(void)
	272	{
	273	tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL,
	274	0x0000ff00);
	275	tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE,
	276	TSI108_PCI_IRP_ENABLE_P_INT);
	277	mb();
	278	}
	279
c4342ff9	280	static inline unsigned int get_pci_source(void)
2b9d7467 ZR	281	{
	282	u_int temp = 0;
	283	int irq = -1;
	284	int i;
	285	u_int pci_irp_stat;
	286	static int mask = 0;
	287
	288	/* Read PCI/X block interrupt status register */
	289	pci_irp_stat = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_STAT);
	290	mb();
	291
	292	if (pci_irp_stat & TSI108_PCI_IRP_STAT_P_INT) {
	293	/* Process Interrupt from PCI bus INTA# - INTD# lines */
	294	temp =
	295	tsi108_read_reg(TSI108_PCI_OFFSET +
	296	TSI108_PCI_IRP_INTAD) & 0xf;
	297	mb();
	298	for (i = 0; i < 4; i++, mask++) {
	299	if (temp & (1 << mask % 4)) {
	300	irq = IRQ_PCI_INTA + mask % 4;
	301	mask++;
	302	break;
	303	}
	304	}
	305
	306	/* Disable interrupts from PCI block */
	307	temp = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE);
	308	tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE,
	309	temp & ~TSI108_PCI_IRP_ENABLE_P_INT);
	310	mb();
	311	(void)tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE);
	312	mb();
	313	}
	314	#ifdef DEBUG
	315	else {
	316	printk("TSI108_PIC: error in TSI108_PCI_IRP_STAT\n");
	317	pci_irp_stat =
	318	tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_STAT);
	319	temp =
	320	tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_INTAD);
	321	mb();
	322	printk(">> stat=0x%08x intad=0x%08x ", pci_irp_stat, temp);
	323	temp =
	324	tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
	325	mb();
	326	printk("cfg_ctl=0x%08x ", temp);
	327	temp =
	328	tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE);
	329	mb();
	330	printk("irp_enable=0x%08x\n", temp);
	331	}
	332	#endif /* end of DEBUG */
	333
	334	return irq;
	335	}
	336
	337
	338	/*
	339	* Linux descriptor level callbacks
	340	*/
	341
	342	static void tsi108_pci_irq_enable(u_int irq)
	343	{
	344	tsi108_pci_int_unmask(irq);
345	}
346
347	static void tsi108_pci_irq_disable(u_int irq)
348	{
349	tsi108_pci_int_mask(irq);
350	}
351
352	static void tsi108_pci_irq_ack(u_int irq)
353	{
354	tsi108_pci_int_mask(irq);
355	}
356
357	static void tsi108_pci_irq_end(u_int irq)
358	{
359	tsi108_pci_int_unmask(irq);
360
361	/* Enable interrupts from PCI block */
362	tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE,
363	tsi108_read_reg(TSI108_PCI_OFFSET +
364	TSI108_PCI_IRP_ENABLE) \|
365	TSI108_PCI_IRP_ENABLE_P_INT);
366	mb();
367	}
368
369	/*
370	* Interrupt controller descriptor for cascaded PCI interrupt controller.
371	*/
372
c4342ff9	373	static struct irq_chip tsi108_pci_irq = {
2b9d7467	374	.typename = "tsi108_PCI_int",
c4342ff9	375	.mask = tsi108_pci_irq_disable,
2b9d7467 ZR	376	.ack = tsi108_pci_irq_ack,
2b9d7467 ZR	377	.end = tsi108_pci_irq_end,
c4342ff9	378	.unmask = tsi108_pci_irq_enable,
2b9d7467 ZR	379	};
	380
	381	/*
	382	* Exported functions
	383	*/
	384
	385	/*
	386	* The Tsi108 PCI interrupts initialization routine.
	387	*
	388	* The INTA# - INTD# interrupts on the PCI bus are reported by the PCI block
	389	* to the MPIC using single interrupt source (IRQ_TSI108_PCI). Therefore the
	390	* PCI block has to be treated as a cascaded interrupt controller connected
	391	* to the MPIC.
	392	*/
	393
	394	void __init tsi108_pci_int_init(void)
	395	{
	396	u_int i;
	397
	398	DBG("Tsi108_pci_int_init: initializing PCI interrupts\n");
	399
	400	for (i = 0; i < NUM_PCI_IRQS; i++) {
c4342ff9	401	irq_desc[i + IRQ_PCI_INTAD_BASE].chip = &tsi108_pci_irq;
2b9d7467 ZR	402	irq_desc[i + IRQ_PCI_INTAD_BASE].status \|= IRQ_LEVEL;
	403	}
	404
	405	init_pci_source();
	406	}
	407
c4342ff9 ZR	408	void tsi108_irq_cascade(unsigned int irq, struct irq_desc *desc,
c4342ff9 ZR	409	struct pt_regs *regs)
2b9d7467	410	{
c4342ff9 ZR	411	unsigned int cascade_irq = get_pci_source();
c4342ff9 ZR	412	if (cascade_irq != NO_IRQ)
49f19ce4	413	generic_handle_irq(cascade_irq);
c4342ff9	414	desc->chip->eoi(irq);
2b9d7467	415	}