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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * PowerPC version |
3 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
4 | * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP | |
5 | * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> | |
6 | * Low-level exception handlers and MMU support | |
7 | * rewritten by Paul Mackerras. | |
8 | * Copyright (C) 1996 Paul Mackerras. | |
9 | * MPC8xx modifications by Dan Malek | |
10 | * Copyright (C) 1997 Dan Malek (dmalek@jlc.net). | |
11 | * | |
12 | * This file contains low-level support and setup for PowerPC 8xx | |
13 | * embedded processors, including trap and interrupt dispatch. | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License | |
17 | * as published by the Free Software Foundation; either version | |
18 | * 2 of the License, or (at your option) any later version. | |
19 | * | |
20 | */ | |
21 | ||
22 | #include <linux/config.h> | |
23 | #include <asm/processor.h> | |
24 | #include <asm/page.h> | |
25 | #include <asm/mmu.h> | |
26 | #include <asm/cache.h> | |
27 | #include <asm/pgtable.h> | |
28 | #include <asm/cputable.h> | |
29 | #include <asm/thread_info.h> | |
30 | #include <asm/ppc_asm.h> | |
0013a854 | 31 | #include <asm/asm-offsets.h> |
1da177e4 LT |
32 | |
33 | /* Macro to make the code more readable. */ | |
34 | #ifdef CONFIG_8xx_CPU6 | |
35 | #define DO_8xx_CPU6(val, reg) \ | |
36 | li reg, val; \ | |
37 | stw reg, 12(r0); \ | |
38 | lwz reg, 12(r0); | |
39 | #else | |
40 | #define DO_8xx_CPU6(val, reg) | |
41 | #endif | |
42 | .text | |
43 | .globl _stext | |
44 | _stext: | |
45 | .text | |
46 | .globl _start | |
47 | _start: | |
48 | ||
49 | /* MPC8xx | |
50 | * This port was done on an MBX board with an 860. Right now I only | |
51 | * support an ELF compressed (zImage) boot from EPPC-Bug because the | |
52 | * code there loads up some registers before calling us: | |
53 | * r3: ptr to board info data | |
54 | * r4: initrd_start or if no initrd then 0 | |
55 | * r5: initrd_end - unused if r4 is 0 | |
56 | * r6: Start of command line string | |
57 | * r7: End of command line string | |
58 | * | |
59 | * I decided to use conditional compilation instead of checking PVR and | |
60 | * adding more processor specific branches around code I don't need. | |
61 | * Since this is an embedded processor, I also appreciate any memory | |
62 | * savings I can get. | |
63 | * | |
64 | * The MPC8xx does not have any BATs, but it supports large page sizes. | |
65 | * We first initialize the MMU to support 8M byte pages, then load one | |
66 | * entry into each of the instruction and data TLBs to map the first | |
67 | * 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to | |
68 | * the "internal" processor registers before MMU_init is called. | |
69 | * | |
70 | * The TLB code currently contains a major hack. Since I use the condition | |
71 | * code register, I have to save and restore it. I am out of registers, so | |
72 | * I just store it in memory location 0 (the TLB handlers are not reentrant). | |
73 | * To avoid making any decisions, I need to use the "segment" valid bit | |
74 | * in the first level table, but that would require many changes to the | |
75 | * Linux page directory/table functions that I don't want to do right now. | |
76 | * | |
77 | * I used to use SPRG2 for a temporary register in the TLB handler, but it | |
78 | * has since been put to other uses. I now use a hack to save a register | |
79 | * and the CCR at memory location 0.....Someday I'll fix this..... | |
80 | * -- Dan | |
81 | */ | |
82 | .globl __start | |
83 | __start: | |
84 | mr r31,r3 /* save parameters */ | |
85 | mr r30,r4 | |
86 | mr r29,r5 | |
87 | mr r28,r6 | |
88 | mr r27,r7 | |
89 | ||
90 | /* We have to turn on the MMU right away so we get cache modes | |
91 | * set correctly. | |
92 | */ | |
93 | bl initial_mmu | |
94 | ||
95 | /* We now have the lower 8 Meg mapped into TLB entries, and the caches | |
96 | * ready to work. | |
97 | */ | |
98 | ||
99 | turn_on_mmu: | |
100 | mfmsr r0 | |
101 | ori r0,r0,MSR_DR|MSR_IR | |
102 | mtspr SPRN_SRR1,r0 | |
103 | lis r0,start_here@h | |
104 | ori r0,r0,start_here@l | |
105 | mtspr SPRN_SRR0,r0 | |
106 | SYNC | |
107 | rfi /* enables MMU */ | |
108 | ||
109 | /* | |
110 | * Exception entry code. This code runs with address translation | |
111 | * turned off, i.e. using physical addresses. | |
112 | * We assume sprg3 has the physical address of the current | |
113 | * task's thread_struct. | |
114 | */ | |
115 | #define EXCEPTION_PROLOG \ | |
116 | mtspr SPRN_SPRG0,r10; \ | |
117 | mtspr SPRN_SPRG1,r11; \ | |
118 | mfcr r10; \ | |
119 | EXCEPTION_PROLOG_1; \ | |
120 | EXCEPTION_PROLOG_2 | |
121 | ||
122 | #define EXCEPTION_PROLOG_1 \ | |
123 | mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \ | |
124 | andi. r11,r11,MSR_PR; \ | |
125 | tophys(r11,r1); /* use tophys(r1) if kernel */ \ | |
126 | beq 1f; \ | |
127 | mfspr r11,SPRN_SPRG3; \ | |
128 | lwz r11,THREAD_INFO-THREAD(r11); \ | |
129 | addi r11,r11,THREAD_SIZE; \ | |
130 | tophys(r11,r11); \ | |
131 | 1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */ | |
132 | ||
133 | ||
134 | #define EXCEPTION_PROLOG_2 \ | |
135 | CLR_TOP32(r11); \ | |
136 | stw r10,_CCR(r11); /* save registers */ \ | |
137 | stw r12,GPR12(r11); \ | |
138 | stw r9,GPR9(r11); \ | |
139 | mfspr r10,SPRN_SPRG0; \ | |
140 | stw r10,GPR10(r11); \ | |
141 | mfspr r12,SPRN_SPRG1; \ | |
142 | stw r12,GPR11(r11); \ | |
143 | mflr r10; \ | |
144 | stw r10,_LINK(r11); \ | |
145 | mfspr r12,SPRN_SRR0; \ | |
146 | mfspr r9,SPRN_SRR1; \ | |
147 | stw r1,GPR1(r11); \ | |
148 | stw r1,0(r11); \ | |
149 | tovirt(r1,r11); /* set new kernel sp */ \ | |
150 | li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \ | |
151 | MTMSRD(r10); /* (except for mach check in rtas) */ \ | |
152 | stw r0,GPR0(r11); \ | |
153 | SAVE_4GPRS(3, r11); \ | |
154 | SAVE_2GPRS(7, r11) | |
155 | ||
156 | /* | |
157 | * Note: code which follows this uses cr0.eq (set if from kernel), | |
158 | * r11, r12 (SRR0), and r9 (SRR1). | |
159 | * | |
160 | * Note2: once we have set r1 we are in a position to take exceptions | |
161 | * again, and we could thus set MSR:RI at that point. | |
162 | */ | |
163 | ||
164 | /* | |
165 | * Exception vectors. | |
166 | */ | |
167 | #define EXCEPTION(n, label, hdlr, xfer) \ | |
168 | . = n; \ | |
169 | label: \ | |
170 | EXCEPTION_PROLOG; \ | |
171 | addi r3,r1,STACK_FRAME_OVERHEAD; \ | |
172 | xfer(n, hdlr) | |
173 | ||
174 | #define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \ | |
175 | li r10,trap; \ | |
176 | stw r10,TRAP(r11); \ | |
177 | li r10,MSR_KERNEL; \ | |
178 | copyee(r10, r9); \ | |
179 | bl tfer; \ | |
180 | i##n: \ | |
181 | .long hdlr; \ | |
182 | .long ret | |
183 | ||
184 | #define COPY_EE(d, s) rlwimi d,s,0,16,16 | |
185 | #define NOCOPY(d, s) | |
186 | ||
187 | #define EXC_XFER_STD(n, hdlr) \ | |
188 | EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \ | |
189 | ret_from_except_full) | |
190 | ||
191 | #define EXC_XFER_LITE(n, hdlr) \ | |
192 | EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \ | |
193 | ret_from_except) | |
194 | ||
195 | #define EXC_XFER_EE(n, hdlr) \ | |
196 | EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \ | |
197 | ret_from_except_full) | |
198 | ||
199 | #define EXC_XFER_EE_LITE(n, hdlr) \ | |
200 | EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \ | |
201 | ret_from_except) | |
202 | ||
203 | /* System reset */ | |
dc1c1ca3 | 204 | EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD) |
1da177e4 LT |
205 | |
206 | /* Machine check */ | |
207 | . = 0x200 | |
208 | MachineCheck: | |
209 | EXCEPTION_PROLOG | |
210 | mfspr r4,SPRN_DAR | |
211 | stw r4,_DAR(r11) | |
212 | mfspr r5,SPRN_DSISR | |
213 | stw r5,_DSISR(r11) | |
214 | addi r3,r1,STACK_FRAME_OVERHEAD | |
dc1c1ca3 | 215 | EXC_XFER_STD(0x200, machine_check_exception) |
1da177e4 LT |
216 | |
217 | /* Data access exception. | |
218 | * This is "never generated" by the MPC8xx. We jump to it for other | |
219 | * translation errors. | |
220 | */ | |
221 | . = 0x300 | |
222 | DataAccess: | |
223 | EXCEPTION_PROLOG | |
224 | mfspr r10,SPRN_DSISR | |
225 | stw r10,_DSISR(r11) | |
226 | mr r5,r10 | |
227 | mfspr r4,SPRN_DAR | |
228 | EXC_XFER_EE_LITE(0x300, handle_page_fault) | |
229 | ||
230 | /* Instruction access exception. | |
231 | * This is "never generated" by the MPC8xx. We jump to it for other | |
232 | * translation errors. | |
233 | */ | |
234 | . = 0x400 | |
235 | InstructionAccess: | |
236 | EXCEPTION_PROLOG | |
237 | mr r4,r12 | |
238 | mr r5,r9 | |
239 | EXC_XFER_EE_LITE(0x400, handle_page_fault) | |
240 | ||
241 | /* External interrupt */ | |
242 | EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE) | |
243 | ||
244 | /* Alignment exception */ | |
245 | . = 0x600 | |
246 | Alignment: | |
247 | EXCEPTION_PROLOG | |
248 | mfspr r4,SPRN_DAR | |
249 | stw r4,_DAR(r11) | |
250 | mfspr r5,SPRN_DSISR | |
251 | stw r5,_DSISR(r11) | |
252 | addi r3,r1,STACK_FRAME_OVERHEAD | |
dc1c1ca3 | 253 | EXC_XFER_EE(0x600, alignment_exception) |
1da177e4 LT |
254 | |
255 | /* Program check exception */ | |
dc1c1ca3 | 256 | EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD) |
1da177e4 LT |
257 | |
258 | /* No FPU on MPC8xx. This exception is not supposed to happen. | |
259 | */ | |
dc1c1ca3 | 260 | EXCEPTION(0x800, FPUnavailable, unknown_exception, EXC_XFER_STD) |
1da177e4 LT |
261 | |
262 | /* Decrementer */ | |
263 | EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE) | |
264 | ||
dc1c1ca3 SR |
265 | EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE) |
266 | EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE) | |
1da177e4 LT |
267 | |
268 | /* System call */ | |
269 | . = 0xc00 | |
270 | SystemCall: | |
271 | EXCEPTION_PROLOG | |
272 | EXC_XFER_EE_LITE(0xc00, DoSyscall) | |
273 | ||
274 | /* Single step - not used on 601 */ | |
dc1c1ca3 SR |
275 | EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD) |
276 | EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE) | |
277 | EXCEPTION(0xf00, Trap_0f, unknown_exception, EXC_XFER_EE) | |
1da177e4 LT |
278 | |
279 | /* On the MPC8xx, this is a software emulation interrupt. It occurs | |
280 | * for all unimplemented and illegal instructions. | |
281 | */ | |
282 | EXCEPTION(0x1000, SoftEmu, SoftwareEmulation, EXC_XFER_STD) | |
283 | ||
284 | . = 0x1100 | |
285 | /* | |
286 | * For the MPC8xx, this is a software tablewalk to load the instruction | |
287 | * TLB. It is modelled after the example in the Motorola manual. The task | |
288 | * switch loads the M_TWB register with the pointer to the first level table. | |
3a1ce8aa MT |
289 | * If we discover there is no second level table (value is zero) or if there |
290 | * is an invalid pte, we load that into the TLB, which causes another fault | |
291 | * into the TLB Error interrupt where we can handle such problems. | |
292 | * We have to use the MD_xxx registers for the tablewalk because the | |
293 | * equivalent MI_xxx registers only perform the attribute functions. | |
1da177e4 LT |
294 | */ |
295 | InstructionTLBMiss: | |
296 | #ifdef CONFIG_8xx_CPU6 | |
297 | stw r3, 8(r0) | |
298 | #endif | |
299 | DO_8xx_CPU6(0x3f80, r3) | |
300 | mtspr SPRN_M_TW, r10 /* Save a couple of working registers */ | |
301 | mfcr r10 | |
302 | stw r10, 0(r0) | |
303 | stw r11, 4(r0) | |
304 | mfspr r10, SPRN_SRR0 /* Get effective address of fault */ | |
305 | DO_8xx_CPU6(0x3780, r3) | |
306 | mtspr SPRN_MD_EPN, r10 /* Have to use MD_EPN for walk, MI_EPN can't */ | |
307 | mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */ | |
308 | ||
309 | /* If we are faulting a kernel address, we have to use the | |
310 | * kernel page tables. | |
311 | */ | |
312 | andi. r11, r10, 0x0800 /* Address >= 0x80000000 */ | |
313 | beq 3f | |
314 | lis r11, swapper_pg_dir@h | |
315 | ori r11, r11, swapper_pg_dir@l | |
316 | rlwimi r10, r11, 0, 2, 19 | |
317 | 3: | |
318 | lwz r11, 0(r10) /* Get the level 1 entry */ | |
319 | rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */ | |
320 | beq 2f /* If zero, don't try to find a pte */ | |
321 | ||
322 | /* We have a pte table, so load the MI_TWC with the attributes | |
323 | * for this "segment." | |
324 | */ | |
325 | ori r11,r11,1 /* Set valid bit */ | |
326 | DO_8xx_CPU6(0x2b80, r3) | |
327 | mtspr SPRN_MI_TWC, r11 /* Set segment attributes */ | |
328 | DO_8xx_CPU6(0x3b80, r3) | |
329 | mtspr SPRN_MD_TWC, r11 /* Load pte table base address */ | |
330 | mfspr r11, SPRN_MD_TWC /* ....and get the pte address */ | |
331 | lwz r10, 0(r11) /* Get the pte */ | |
332 | ||
333 | ori r10, r10, _PAGE_ACCESSED | |
334 | stw r10, 0(r11) | |
335 | ||
336 | /* The Linux PTE won't go exactly into the MMU TLB. | |
337 | * Software indicator bits 21, 22 and 28 must be clear. | |
338 | * Software indicator bits 24, 25, 26, and 27 must be | |
339 | * set. All other Linux PTE bits control the behavior | |
340 | * of the MMU. | |
341 | */ | |
342 | 2: li r11, 0x00f0 | |
343 | rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ | |
344 | DO_8xx_CPU6(0x2d80, r3) | |
345 | mtspr SPRN_MI_RPN, r10 /* Update TLB entry */ | |
346 | ||
347 | mfspr r10, SPRN_M_TW /* Restore registers */ | |
348 | lwz r11, 0(r0) | |
349 | mtcr r11 | |
350 | lwz r11, 4(r0) | |
351 | #ifdef CONFIG_8xx_CPU6 | |
352 | lwz r3, 8(r0) | |
353 | #endif | |
354 | rfi | |
355 | ||
356 | . = 0x1200 | |
357 | DataStoreTLBMiss: | |
358 | #ifdef CONFIG_8xx_CPU6 | |
359 | stw r3, 8(r0) | |
360 | #endif | |
361 | DO_8xx_CPU6(0x3f80, r3) | |
362 | mtspr SPRN_M_TW, r10 /* Save a couple of working registers */ | |
363 | mfcr r10 | |
364 | stw r10, 0(r0) | |
365 | stw r11, 4(r0) | |
366 | mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */ | |
367 | ||
368 | /* If we are faulting a kernel address, we have to use the | |
369 | * kernel page tables. | |
370 | */ | |
371 | andi. r11, r10, 0x0800 | |
372 | beq 3f | |
373 | lis r11, swapper_pg_dir@h | |
374 | ori r11, r11, swapper_pg_dir@l | |
375 | rlwimi r10, r11, 0, 2, 19 | |
8f069b1a MT |
376 | stw r12, 16(r0) |
377 | b LoadLargeDTLB | |
1da177e4 LT |
378 | 3: |
379 | lwz r11, 0(r10) /* Get the level 1 entry */ | |
380 | rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */ | |
381 | beq 2f /* If zero, don't try to find a pte */ | |
382 | ||
383 | /* We have a pte table, so load fetch the pte from the table. | |
384 | */ | |
385 | ori r11, r11, 1 /* Set valid bit in physical L2 page */ | |
386 | DO_8xx_CPU6(0x3b80, r3) | |
387 | mtspr SPRN_MD_TWC, r11 /* Load pte table base address */ | |
388 | mfspr r10, SPRN_MD_TWC /* ....and get the pte address */ | |
389 | lwz r10, 0(r10) /* Get the pte */ | |
390 | ||
391 | /* Insert the Guarded flag into the TWC from the Linux PTE. | |
392 | * It is bit 27 of both the Linux PTE and the TWC (at least | |
393 | * I got that right :-). It will be better when we can put | |
394 | * this into the Linux pgd/pmd and load it in the operation | |
395 | * above. | |
396 | */ | |
397 | rlwimi r11, r10, 0, 27, 27 | |
398 | DO_8xx_CPU6(0x3b80, r3) | |
399 | mtspr SPRN_MD_TWC, r11 | |
400 | ||
401 | mfspr r11, SPRN_MD_TWC /* get the pte address again */ | |
402 | ori r10, r10, _PAGE_ACCESSED | |
403 | stw r10, 0(r11) | |
404 | ||
405 | /* The Linux PTE won't go exactly into the MMU TLB. | |
406 | * Software indicator bits 21, 22 and 28 must be clear. | |
407 | * Software indicator bits 24, 25, 26, and 27 must be | |
408 | * set. All other Linux PTE bits control the behavior | |
409 | * of the MMU. | |
410 | */ | |
411 | 2: li r11, 0x00f0 | |
412 | rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ | |
413 | DO_8xx_CPU6(0x3d80, r3) | |
414 | mtspr SPRN_MD_RPN, r10 /* Update TLB entry */ | |
415 | ||
416 | mfspr r10, SPRN_M_TW /* Restore registers */ | |
417 | lwz r11, 0(r0) | |
418 | mtcr r11 | |
419 | lwz r11, 4(r0) | |
420 | #ifdef CONFIG_8xx_CPU6 | |
421 | lwz r3, 8(r0) | |
422 | #endif | |
423 | rfi | |
424 | ||
425 | /* This is an instruction TLB error on the MPC8xx. This could be due | |
426 | * to many reasons, such as executing guarded memory or illegal instruction | |
427 | * addresses. There is nothing to do but handle a big time error fault. | |
428 | */ | |
429 | . = 0x1300 | |
430 | InstructionTLBError: | |
431 | b InstructionAccess | |
432 | ||
8f069b1a MT |
433 | LoadLargeDTLB: |
434 | li r12, 0 | |
435 | lwz r11, 0(r10) /* Get the level 1 entry */ | |
436 | rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */ | |
437 | beq 3f /* If zero, don't try to find a pte */ | |
438 | ||
439 | /* We have a pte table, so load fetch the pte from the table. | |
440 | */ | |
441 | ori r11, r11, 1 /* Set valid bit in physical L2 page */ | |
442 | DO_8xx_CPU6(0x3b80, r3) | |
443 | mtspr SPRN_MD_TWC, r11 /* Load pte table base address */ | |
444 | mfspr r10, SPRN_MD_TWC /* ....and get the pte address */ | |
445 | lwz r10, 0(r10) /* Get the pte */ | |
446 | ||
447 | /* Insert the Guarded flag into the TWC from the Linux PTE. | |
448 | * It is bit 27 of both the Linux PTE and the TWC (at least | |
449 | * I got that right :-). It will be better when we can put | |
450 | * this into the Linux pgd/pmd and load it in the operation | |
451 | * above. | |
452 | */ | |
453 | rlwimi r11, r10, 0, 27, 27 | |
454 | ||
455 | rlwimi r12, r10, 0, 0, 9 /* extract phys. addr */ | |
456 | mfspr r3, SPRN_MD_EPN | |
457 | rlwinm r3, r3, 0, 0, 9 /* extract virtual address */ | |
458 | tophys(r3, r3) | |
459 | cmpw r3, r12 /* only use 8M page if it is a direct | |
460 | kernel mapping */ | |
461 | bne 1f | |
462 | ori r11, r11, MD_PS8MEG | |
463 | li r12, 1 | |
464 | b 2f | |
465 | 1: | |
466 | li r12, 0 /* can't use 8MB TLB, so zero r12. */ | |
467 | 2: | |
468 | DO_8xx_CPU6(0x3b80, r3) | |
469 | mtspr SPRN_MD_TWC, r11 | |
470 | ||
471 | /* The Linux PTE won't go exactly into the MMU TLB. | |
472 | * Software indicator bits 21, 22 and 28 must be clear. | |
473 | * Software indicator bits 24, 25, 26, and 27 must be | |
474 | * set. All other Linux PTE bits control the behavior | |
475 | * of the MMU. | |
476 | */ | |
477 | 3: li r11, 0x00f0 | |
478 | rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ | |
479 | cmpwi r12, 1 | |
480 | bne 4f | |
481 | ori r10, r10, 0x8 | |
482 | ||
483 | mfspr r12, SPRN_MD_EPN | |
484 | lis r3, 0xff80 /* 10-19 must be clear for 8MB TLB */ | |
485 | ori r3, r3, 0x0fff | |
486 | and r12, r3, r12 | |
487 | DO_8xx_CPU6(0x3780, r3) | |
488 | mtspr SPRN_MD_EPN, r12 | |
489 | ||
490 | lis r3, 0xff80 /* 10-19 must be clear for 8MB TLB */ | |
491 | ori r3, r3, 0x0fff | |
492 | and r10, r3, r10 | |
493 | 4: | |
494 | DO_8xx_CPU6(0x3d80, r3) | |
495 | mtspr SPRN_MD_RPN, r10 /* Update TLB entry */ | |
496 | ||
497 | mfspr r10, SPRN_M_TW /* Restore registers */ | |
498 | lwz r11, 0(r0) | |
499 | mtcr r11 | |
500 | lwz r11, 4(r0) | |
501 | ||
502 | lwz r12, 16(r0) | |
503 | #ifdef CONFIG_8xx_CPU6 | |
504 | lwz r3, 8(r0) | |
505 | #endif | |
506 | rfi | |
507 | ||
1da177e4 LT |
508 | /* This is the data TLB error on the MPC8xx. This could be due to |
509 | * many reasons, including a dirty update to a pte. We can catch that | |
510 | * one here, but anything else is an error. First, we track down the | |
511 | * Linux pte. If it is valid, write access is allowed, but the | |
512 | * page dirty bit is not set, we will set it and reload the TLB. For | |
513 | * any other case, we bail out to a higher level function that can | |
514 | * handle it. | |
515 | */ | |
516 | . = 0x1400 | |
517 | DataTLBError: | |
518 | #ifdef CONFIG_8xx_CPU6 | |
519 | stw r3, 8(r0) | |
520 | #endif | |
521 | DO_8xx_CPU6(0x3f80, r3) | |
522 | mtspr SPRN_M_TW, r10 /* Save a couple of working registers */ | |
523 | mfcr r10 | |
524 | stw r10, 0(r0) | |
525 | stw r11, 4(r0) | |
526 | ||
527 | /* First, make sure this was a store operation. | |
528 | */ | |
529 | mfspr r10, SPRN_DSISR | |
530 | andis. r11, r10, 0x0200 /* If set, indicates store op */ | |
531 | beq 2f | |
532 | ||
533 | /* The EA of a data TLB miss is automatically stored in the MD_EPN | |
534 | * register. The EA of a data TLB error is automatically stored in | |
535 | * the DAR, but not the MD_EPN register. We must copy the 20 most | |
536 | * significant bits of the EA from the DAR to MD_EPN before we | |
537 | * start walking the page tables. We also need to copy the CASID | |
538 | * value from the M_CASID register. | |
539 | * Addendum: The EA of a data TLB error is _supposed_ to be stored | |
540 | * in DAR, but it seems that this doesn't happen in some cases, such | |
541 | * as when the error is due to a dcbi instruction to a page with a | |
542 | * TLB that doesn't have the changed bit set. In such cases, there | |
543 | * does not appear to be any way to recover the EA of the error | |
544 | * since it is neither in DAR nor MD_EPN. As a workaround, the | |
545 | * _PAGE_HWWRITE bit is set for all kernel data pages when the PTEs | |
546 | * are initialized in mapin_ram(). This will avoid the problem, | |
547 | * assuming we only use the dcbi instruction on kernel addresses. | |
548 | */ | |
549 | mfspr r10, SPRN_DAR | |
550 | rlwinm r11, r10, 0, 0, 19 | |
551 | ori r11, r11, MD_EVALID | |
552 | mfspr r10, SPRN_M_CASID | |
553 | rlwimi r11, r10, 0, 28, 31 | |
554 | DO_8xx_CPU6(0x3780, r3) | |
555 | mtspr SPRN_MD_EPN, r11 | |
556 | ||
557 | mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */ | |
558 | ||
559 | /* If we are faulting a kernel address, we have to use the | |
560 | * kernel page tables. | |
561 | */ | |
562 | andi. r11, r10, 0x0800 | |
563 | beq 3f | |
564 | lis r11, swapper_pg_dir@h | |
565 | ori r11, r11, swapper_pg_dir@l | |
566 | rlwimi r10, r11, 0, 2, 19 | |
567 | 3: | |
568 | lwz r11, 0(r10) /* Get the level 1 entry */ | |
569 | rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */ | |
570 | beq 2f /* If zero, bail */ | |
571 | ||
572 | /* We have a pte table, so fetch the pte from the table. | |
573 | */ | |
574 | ori r11, r11, 1 /* Set valid bit in physical L2 page */ | |
575 | DO_8xx_CPU6(0x3b80, r3) | |
576 | mtspr SPRN_MD_TWC, r11 /* Load pte table base address */ | |
577 | mfspr r11, SPRN_MD_TWC /* ....and get the pte address */ | |
578 | lwz r10, 0(r11) /* Get the pte */ | |
579 | ||
580 | andi. r11, r10, _PAGE_RW /* Is it writeable? */ | |
581 | beq 2f /* Bail out if not */ | |
582 | ||
583 | /* Update 'changed', among others. | |
584 | */ | |
585 | ori r10, r10, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE | |
586 | mfspr r11, SPRN_MD_TWC /* Get pte address again */ | |
587 | stw r10, 0(r11) /* and update pte in table */ | |
588 | ||
589 | /* The Linux PTE won't go exactly into the MMU TLB. | |
590 | * Software indicator bits 21, 22 and 28 must be clear. | |
591 | * Software indicator bits 24, 25, 26, and 27 must be | |
592 | * set. All other Linux PTE bits control the behavior | |
593 | * of the MMU. | |
594 | */ | |
595 | li r11, 0x00f0 | |
596 | rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ | |
597 | DO_8xx_CPU6(0x3d80, r3) | |
598 | mtspr SPRN_MD_RPN, r10 /* Update TLB entry */ | |
599 | ||
600 | mfspr r10, SPRN_M_TW /* Restore registers */ | |
601 | lwz r11, 0(r0) | |
602 | mtcr r11 | |
603 | lwz r11, 4(r0) | |
604 | #ifdef CONFIG_8xx_CPU6 | |
605 | lwz r3, 8(r0) | |
606 | #endif | |
607 | rfi | |
608 | 2: | |
609 | mfspr r10, SPRN_M_TW /* Restore registers */ | |
610 | lwz r11, 0(r0) | |
611 | mtcr r11 | |
612 | lwz r11, 4(r0) | |
613 | #ifdef CONFIG_8xx_CPU6 | |
614 | lwz r3, 8(r0) | |
615 | #endif | |
616 | b DataAccess | |
617 | ||
dc1c1ca3 SR |
618 | EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE) |
619 | EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE) | |
620 | EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE) | |
621 | EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE) | |
622 | EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE) | |
623 | EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE) | |
624 | EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE) | |
1da177e4 LT |
625 | |
626 | /* On the MPC8xx, these next four traps are used for development | |
627 | * support of breakpoints and such. Someday I will get around to | |
628 | * using them. | |
629 | */ | |
dc1c1ca3 SR |
630 | EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE) |
631 | EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE) | |
632 | EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE) | |
633 | EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE) | |
1da177e4 LT |
634 | |
635 | . = 0x2000 | |
636 | ||
637 | .globl giveup_fpu | |
638 | giveup_fpu: | |
639 | blr | |
640 | ||
641 | /* | |
642 | * This is where the main kernel code starts. | |
643 | */ | |
644 | start_here: | |
645 | /* ptr to current */ | |
646 | lis r2,init_task@h | |
647 | ori r2,r2,init_task@l | |
648 | ||
649 | /* ptr to phys current thread */ | |
650 | tophys(r4,r2) | |
651 | addi r4,r4,THREAD /* init task's THREAD */ | |
652 | mtspr SPRN_SPRG3,r4 | |
653 | li r3,0 | |
654 | mtspr SPRN_SPRG2,r3 /* 0 => r1 has kernel sp */ | |
655 | ||
656 | /* stack */ | |
657 | lis r1,init_thread_union@ha | |
658 | addi r1,r1,init_thread_union@l | |
659 | li r0,0 | |
660 | stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) | |
661 | ||
662 | bl early_init /* We have to do this with MMU on */ | |
663 | ||
664 | /* | |
665 | * Decide what sort of machine this is and initialize the MMU. | |
666 | */ | |
667 | mr r3,r31 | |
668 | mr r4,r30 | |
669 | mr r5,r29 | |
670 | mr r6,r28 | |
671 | mr r7,r27 | |
672 | bl machine_init | |
673 | bl MMU_init | |
674 | ||
675 | /* | |
676 | * Go back to running unmapped so we can load up new values | |
677 | * and change to using our exception vectors. | |
678 | * On the 8xx, all we have to do is invalidate the TLB to clear | |
679 | * the old 8M byte TLB mappings and load the page table base register. | |
680 | */ | |
681 | /* The right way to do this would be to track it down through | |
682 | * init's THREAD like the context switch code does, but this is | |
683 | * easier......until someone changes init's static structures. | |
684 | */ | |
685 | lis r6, swapper_pg_dir@h | |
686 | ori r6, r6, swapper_pg_dir@l | |
687 | tophys(r6,r6) | |
688 | #ifdef CONFIG_8xx_CPU6 | |
689 | lis r4, cpu6_errata_word@h | |
690 | ori r4, r4, cpu6_errata_word@l | |
691 | li r3, 0x3980 | |
692 | stw r3, 12(r4) | |
693 | lwz r3, 12(r4) | |
694 | #endif | |
695 | mtspr SPRN_M_TWB, r6 | |
696 | lis r4,2f@h | |
697 | ori r4,r4,2f@l | |
698 | tophys(r4,r4) | |
699 | li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR) | |
700 | mtspr SPRN_SRR0,r4 | |
701 | mtspr SPRN_SRR1,r3 | |
702 | rfi | |
703 | /* Load up the kernel context */ | |
704 | 2: | |
705 | SYNC /* Force all PTE updates to finish */ | |
706 | tlbia /* Clear all TLB entries */ | |
707 | sync /* wait for tlbia/tlbie to finish */ | |
708 | TLBSYNC /* ... on all CPUs */ | |
709 | ||
710 | /* set up the PTE pointers for the Abatron bdiGDB. | |
711 | */ | |
712 | tovirt(r6,r6) | |
713 | lis r5, abatron_pteptrs@h | |
714 | ori r5, r5, abatron_pteptrs@l | |
715 | stw r5, 0xf0(r0) /* Must match your Abatron config file */ | |
716 | tophys(r5,r5) | |
717 | stw r6, 0(r5) | |
718 | ||
719 | /* Now turn on the MMU for real! */ | |
720 | li r4,MSR_KERNEL | |
721 | lis r3,start_kernel@h | |
722 | ori r3,r3,start_kernel@l | |
723 | mtspr SPRN_SRR0,r3 | |
724 | mtspr SPRN_SRR1,r4 | |
725 | rfi /* enable MMU and jump to start_kernel */ | |
726 | ||
727 | /* Set up the initial MMU state so we can do the first level of | |
728 | * kernel initialization. This maps the first 8 MBytes of memory 1:1 | |
729 | * virtual to physical. Also, set the cache mode since that is defined | |
730 | * by TLB entries and perform any additional mapping (like of the IMMR). | |
731 | * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel, | |
732 | * 24 Mbytes of data, and the 8M IMMR space. Anything not covered by | |
733 | * these mappings is mapped by page tables. | |
734 | */ | |
735 | initial_mmu: | |
736 | tlbia /* Invalidate all TLB entries */ | |
737 | #ifdef CONFIG_PIN_TLB | |
738 | lis r8, MI_RSV4I@h | |
739 | ori r8, r8, 0x1c00 | |
740 | #else | |
741 | li r8, 0 | |
742 | #endif | |
743 | mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */ | |
744 | ||
745 | #ifdef CONFIG_PIN_TLB | |
746 | lis r10, (MD_RSV4I | MD_RESETVAL)@h | |
747 | ori r10, r10, 0x1c00 | |
748 | mr r8, r10 | |
749 | #else | |
750 | lis r10, MD_RESETVAL@h | |
751 | #endif | |
752 | #ifndef CONFIG_8xx_COPYBACK | |
753 | oris r10, r10, MD_WTDEF@h | |
754 | #endif | |
755 | mtspr SPRN_MD_CTR, r10 /* Set data TLB control */ | |
756 | ||
757 | /* Now map the lower 8 Meg into the TLBs. For this quick hack, | |
758 | * we can load the instruction and data TLB registers with the | |
759 | * same values. | |
760 | */ | |
761 | lis r8, KERNELBASE@h /* Create vaddr for TLB */ | |
762 | ori r8, r8, MI_EVALID /* Mark it valid */ | |
763 | mtspr SPRN_MI_EPN, r8 | |
764 | mtspr SPRN_MD_EPN, r8 | |
765 | li r8, MI_PS8MEG /* Set 8M byte page */ | |
766 | ori r8, r8, MI_SVALID /* Make it valid */ | |
767 | mtspr SPRN_MI_TWC, r8 | |
768 | mtspr SPRN_MD_TWC, r8 | |
769 | li r8, MI_BOOTINIT /* Create RPN for address 0 */ | |
770 | mtspr SPRN_MI_RPN, r8 /* Store TLB entry */ | |
771 | mtspr SPRN_MD_RPN, r8 | |
772 | lis r8, MI_Kp@h /* Set the protection mode */ | |
773 | mtspr SPRN_MI_AP, r8 | |
774 | mtspr SPRN_MD_AP, r8 | |
775 | ||
776 | /* Map another 8 MByte at the IMMR to get the processor | |
777 | * internal registers (among other things). | |
778 | */ | |
779 | #ifdef CONFIG_PIN_TLB | |
780 | addi r10, r10, 0x0100 | |
781 | mtspr SPRN_MD_CTR, r10 | |
782 | #endif | |
783 | mfspr r9, 638 /* Get current IMMR */ | |
784 | andis. r9, r9, 0xff80 /* Get 8Mbyte boundary */ | |
785 | ||
786 | mr r8, r9 /* Create vaddr for TLB */ | |
787 | ori r8, r8, MD_EVALID /* Mark it valid */ | |
788 | mtspr SPRN_MD_EPN, r8 | |
789 | li r8, MD_PS8MEG /* Set 8M byte page */ | |
790 | ori r8, r8, MD_SVALID /* Make it valid */ | |
791 | mtspr SPRN_MD_TWC, r8 | |
792 | mr r8, r9 /* Create paddr for TLB */ | |
793 | ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */ | |
794 | mtspr SPRN_MD_RPN, r8 | |
795 | ||
796 | #ifdef CONFIG_PIN_TLB | |
797 | /* Map two more 8M kernel data pages. | |
798 | */ | |
799 | addi r10, r10, 0x0100 | |
800 | mtspr SPRN_MD_CTR, r10 | |
801 | ||
802 | lis r8, KERNELBASE@h /* Create vaddr for TLB */ | |
803 | addis r8, r8, 0x0080 /* Add 8M */ | |
804 | ori r8, r8, MI_EVALID /* Mark it valid */ | |
805 | mtspr SPRN_MD_EPN, r8 | |
806 | li r9, MI_PS8MEG /* Set 8M byte page */ | |
807 | ori r9, r9, MI_SVALID /* Make it valid */ | |
808 | mtspr SPRN_MD_TWC, r9 | |
809 | li r11, MI_BOOTINIT /* Create RPN for address 0 */ | |
810 | addis r11, r11, 0x0080 /* Add 8M */ | |
3ea4807d MT |
811 | mtspr SPRN_MD_RPN, r11 |
812 | ||
813 | addi r10, r10, 0x0100 | |
814 | mtspr SPRN_MD_CTR, r10 | |
1da177e4 LT |
815 | |
816 | addis r8, r8, 0x0080 /* Add 8M */ | |
817 | mtspr SPRN_MD_EPN, r8 | |
818 | mtspr SPRN_MD_TWC, r9 | |
819 | addis r11, r11, 0x0080 /* Add 8M */ | |
3ea4807d | 820 | mtspr SPRN_MD_RPN, r11 |
1da177e4 LT |
821 | #endif |
822 | ||
823 | /* Since the cache is enabled according to the information we | |
824 | * just loaded into the TLB, invalidate and enable the caches here. | |
825 | * We should probably check/set other modes....later. | |
826 | */ | |
827 | lis r8, IDC_INVALL@h | |
828 | mtspr SPRN_IC_CST, r8 | |
829 | mtspr SPRN_DC_CST, r8 | |
830 | lis r8, IDC_ENABLE@h | |
831 | mtspr SPRN_IC_CST, r8 | |
832 | #ifdef CONFIG_8xx_COPYBACK | |
833 | mtspr SPRN_DC_CST, r8 | |
834 | #else | |
835 | /* For a debug option, I left this here to easily enable | |
836 | * the write through cache mode | |
837 | */ | |
838 | lis r8, DC_SFWT@h | |
839 | mtspr SPRN_DC_CST, r8 | |
840 | lis r8, IDC_ENABLE@h | |
841 | mtspr SPRN_DC_CST, r8 | |
842 | #endif | |
843 | blr | |
844 | ||
845 | ||
846 | /* | |
847 | * Set up to use a given MMU context. | |
848 | * r3 is context number, r4 is PGD pointer. | |
849 | * | |
850 | * We place the physical address of the new task page directory loaded | |
851 | * into the MMU base register, and set the ASID compare register with | |
852 | * the new "context." | |
853 | */ | |
854 | _GLOBAL(set_context) | |
855 | ||
856 | #ifdef CONFIG_BDI_SWITCH | |
857 | /* Context switch the PTE pointer for the Abatron BDI2000. | |
858 | * The PGDIR is passed as second argument. | |
859 | */ | |
860 | lis r5, KERNELBASE@h | |
861 | lwz r5, 0xf0(r5) | |
862 | stw r4, 0x4(r5) | |
863 | #endif | |
864 | ||
865 | #ifdef CONFIG_8xx_CPU6 | |
866 | lis r6, cpu6_errata_word@h | |
867 | ori r6, r6, cpu6_errata_word@l | |
868 | tophys (r4, r4) | |
869 | li r7, 0x3980 | |
870 | stw r7, 12(r6) | |
871 | lwz r7, 12(r6) | |
872 | mtspr SPRN_M_TWB, r4 /* Update MMU base address */ | |
873 | li r7, 0x3380 | |
874 | stw r7, 12(r6) | |
875 | lwz r7, 12(r6) | |
876 | mtspr SPRN_M_CASID, r3 /* Update context */ | |
877 | #else | |
878 | mtspr SPRN_M_CASID,r3 /* Update context */ | |
879 | tophys (r4, r4) | |
880 | mtspr SPRN_M_TWB, r4 /* and pgd */ | |
881 | #endif | |
882 | SYNC | |
883 | blr | |
884 | ||
885 | #ifdef CONFIG_8xx_CPU6 | |
886 | /* It's here because it is unique to the 8xx. | |
887 | * It is important we get called with interrupts disabled. I used to | |
888 | * do that, but it appears that all code that calls this already had | |
889 | * interrupt disabled. | |
890 | */ | |
891 | .globl set_dec_cpu6 | |
892 | set_dec_cpu6: | |
893 | lis r7, cpu6_errata_word@h | |
894 | ori r7, r7, cpu6_errata_word@l | |
895 | li r4, 0x2c00 | |
896 | stw r4, 8(r7) | |
897 | lwz r4, 8(r7) | |
898 | mtspr 22, r3 /* Update Decrementer */ | |
899 | SYNC | |
900 | blr | |
901 | #endif | |
902 | ||
903 | /* | |
904 | * We put a few things here that have to be page-aligned. | |
905 | * This stuff goes at the beginning of the data segment, | |
906 | * which is page-aligned. | |
907 | */ | |
908 | .data | |
909 | .globl sdata | |
910 | sdata: | |
911 | .globl empty_zero_page | |
912 | empty_zero_page: | |
913 | .space 4096 | |
914 | ||
915 | .globl swapper_pg_dir | |
916 | swapper_pg_dir: | |
917 | .space 4096 | |
918 | ||
919 | /* | |
920 | * This space gets a copy of optional info passed to us by the bootstrap | |
921 | * Used to pass parameters into the kernel like root=/dev/sda1, etc. | |
922 | */ | |
923 | .globl cmd_line | |
924 | cmd_line: | |
925 | .space 512 | |
926 | ||
927 | /* Room for two PTE table poiners, usually the kernel and current user | |
928 | * pointer to their respective root page table (pgdir). | |
929 | */ | |
930 | abatron_pteptrs: | |
931 | .space 8 | |
932 | ||
933 | #ifdef CONFIG_8xx_CPU6 | |
934 | .globl cpu6_errata_word | |
935 | cpu6_errata_word: | |
936 | .space 16 | |
937 | #endif | |
938 |