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[PATCH] powerpc: trivial: modify comments to refer to new location of files
[deliverable/linux.git] / arch / ppc / platforms / 4xx / walnut.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Architecture- / platform-specific boot-time initialization code for
3 * IBM PowerPC 4xx based boards. Adapted from original
4 * code by Gary Thomas, Cort Dougan <cort@fsmlabs.com>, and Dan Malek
5 * <dan@net4x.com>.
6 *
7 * Copyright(c) 1999-2000 Grant Erickson <grant@lcse.umn.edu>
8 *
9 * 2002 (c) MontaVista, Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
14#include <linux/config.h>
15#include <linux/init.h>
16#include <linux/smp.h>
17#include <linux/threads.h>
18#include <linux/param.h>
19#include <linux/string.h>
20#include <linux/pci.h>
21#include <linux/rtc.h>
22
23#include <asm/system.h>
24#include <asm/pci-bridge.h>
25#include <asm/machdep.h>
26#include <asm/page.h>
27#include <asm/time.h>
28#include <asm/io.h>
29#include <asm/ocp.h>
30#include <asm/ibm_ocp_pci.h>
31#include <asm/todc.h>
32
33#undef DEBUG
34
35#ifdef DEBUG
36#define DBG(x...) printk(x)
37#else
38#define DBG(x...)
39#endif
40
41void *kb_cs;
42void *kb_data;
43void *walnut_rtc_base;
44
45/* Some IRQs unique to Walnut.
46 * Used by the generic 405 PCI setup functions in ppc4xx_pci.c
47 */
48int __init
49ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
50{
51 static char pci_irq_table[][4] =
52 /*
53 * PCI IDSEL/INTPIN->INTLINE
54 * A B C D
55 */
56 {
57 {28, 28, 28, 28}, /* IDSEL 1 - PCI slot 1 */
58 {29, 29, 29, 29}, /* IDSEL 2 - PCI slot 2 */
59 {30, 30, 30, 30}, /* IDSEL 3 - PCI slot 3 */
60 {31, 31, 31, 31}, /* IDSEL 4 - PCI slot 4 */
61 };
62
63 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
64 return PCI_IRQ_TABLE_LOOKUP;
65};
66
67void __init
68walnut_setup_arch(void)
69{
70
71 void *fpga_brdc;
72 unsigned char fpga_brdc_data;
73 void *fpga_enable;
74 void *fpga_polarity;
75 void *fpga_status;
76 void *fpga_trigger;
77
78 ppc4xx_setup_arch();
79
80 ibm_ocp_set_emac(0, 0);
81
82 kb_data = ioremap(WALNUT_PS2_BASE, 8);
83 if (!kb_data) {
84 printk(KERN_CRIT
85 "walnut_setup_arch() kb_data ioremap failed\n");
86 return;
87 }
88
89 kb_cs = kb_data + 1;
90
3e9e7c1d 91 fpga_status = ioremap(PPC40x_FPGA_BASE, 8);
1da177e4
LT		 92 if (!fpga_status) {
93 printk(KERN_CRIT
94 "walnut_setup_arch() fpga_status ioremap failed\n");
95 return;
96 }
97
98 fpga_enable = fpga_status + 1;
99 fpga_polarity = fpga_status + 2;
100 fpga_trigger = fpga_status + 3;
101 fpga_brdc = fpga_status + 4;
102
103 /* split the keyboard and mouse interrupts */
104 fpga_brdc_data = readb(fpga_brdc);
105 fpga_brdc_data |= 0x80;
106 writeb(fpga_brdc_data, fpga_brdc);
107
108 writeb(0x3, fpga_enable);
109
110 writeb(0x3, fpga_polarity);
111
112 writeb(0x3, fpga_trigger);
113
114 /* RTC step for the walnut */
115 walnut_rtc_base = (void *) WALNUT_RTC_VADDR;
116 TODC_INIT(TODC_TYPE_DS1743, walnut_rtc_base, walnut_rtc_base,
117 walnut_rtc_base, 8);
118 /* Identify the system */
119 printk("IBM Walnut port (C) 2000-2002 MontaVista Software, Inc. (source@mvista.com)\n");
120}
121
122void __init
123bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
124{
125#ifdef CONFIG_PCI
126 unsigned int bar_response, bar;
127 /*
128 * Expected PCI mapping:
129 *
130 * PLB addr PCI memory addr
131 * --------------------- ---------------------
132 * 0000'0000 - 7fff'ffff <--- 0000'0000 - 7fff'ffff
133 * 8000'0000 - Bfff'ffff ---> 8000'0000 - Bfff'ffff
134 *
135 * PLB addr PCI io addr
136 * --------------------- ---------------------
137 * e800'0000 - e800'ffff ---> 0000'0000 - 0001'0000
138 *
139 * The following code is simplified by assuming that the bootrom
140 * has been well behaved in following this mapping.
141 */
142
143#ifdef DEBUG
144 int i;
145
146 printk("ioremap PCLIO_BASE = 0x%x\n", pcip);
147 printk("PCI bridge regs before fixup \n");
148 for (i = 0; i <= 3; i++) {
149 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
150 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
151 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
152 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
153 }
154 printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
155 printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
156 printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
157 printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
158
159#endif
160
161 /* added for IBM boot rom version 1.15 bios bar changes -AK */
162
163 /* Disable region first */
164 out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
165 /* PLB starting addr, PCI: 0x80000000 */
166 out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
167 /* PCI start addr, 0x80000000 */
168 out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
169 /* 512MB range of PLB to PCI */
170 out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
171 /* Enable no pre-fetch, enable region */
172 out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
173 (PPC405_PCI_UPPER_MEM -
174 PPC405_PCI_MEM_BASE)) | 0x01));
175
176 /* Disable region one */
177 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
178 out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
179 out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
180 out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
181 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
182 out_le32((void *) &(pcip->ptm1ms), 0x00000000);
183
184 /* Disable region two */
185 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
186 out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
187 out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
188 out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
189 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
190 out_le32((void *) &(pcip->ptm2ms), 0x00000000);
191
192 /* Zero config bars */
193 for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
194 early_write_config_dword(hose, hose->first_busno,
195 PCI_FUNC(hose->first_busno), bar,
196 0x00000000);
197 early_read_config_dword(hose, hose->first_busno,
198 PCI_FUNC(hose->first_busno), bar,
199 &bar_response);
200 DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
201 hose->first_busno, PCI_SLOT(hose->first_busno),
202 PCI_FUNC(hose->first_busno), bar, bar_response);
203 }
204 /* end work arround */
205
206#ifdef DEBUG
207 printk("PCI bridge regs after fixup \n");
208 for (i = 0; i <= 3; i++) {
209 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
210 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
211 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
212 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
213 }
214 printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
215 printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
216 printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
217 printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
218
219#endif
220#endif
221}
222
223void __init
224walnut_map_io(void)
225{
226 ppc4xx_map_io();
227 io_block_mapping(WALNUT_RTC_VADDR,
228 WALNUT_RTC_PADDR, WALNUT_RTC_SIZE, _PAGE_IO);
229}
230
231void __init
232platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
233 unsigned long r6, unsigned long r7)
234{
235 ppc4xx_init(r3, r4, r5, r6, r7);
236
237 ppc_md.setup_arch = walnut_setup_arch;
238 ppc_md.setup_io_mappings = walnut_map_io;
239
240#ifdef CONFIG_GEN_RTC
241 ppc_md.time_init = todc_time_init;
242 ppc_md.set_rtc_time = todc_set_rtc_time;
243 ppc_md.get_rtc_time = todc_get_rtc_time;
244 ppc_md.nvram_read_val = todc_direct_read_val;
245 ppc_md.nvram_write_val = todc_direct_write_val;
246#endif
247}
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