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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Header file for IBM CPC700 Host Bridge, et. al. |
3 | * | |
4 | * Author: Mark A. Greer | |
5 | * mgreer@mvista.com | |
6 | * | |
7 | * 2000-2002 (c) MontaVista, Software, Inc. This file is licensed under | |
8 | * the terms of the GNU General Public License version 2. This program | |
9 | * is licensed "as is" without any warranty of any kind, whether express | |
10 | * or implied. | |
11 | */ | |
12 | ||
13 | /* | |
14 | * This file contains the defines and macros for the IBM CPC700 host bridge, | |
15 | * memory controller, PIC, UARTs, IIC, and Timers. | |
16 | */ | |
17 | ||
18 | #ifndef __PPC_SYSLIB_CPC700_H__ | |
19 | #define __PPC_SYSLIB_CPC700_H__ | |
20 | ||
21 | #include <linux/stddef.h> | |
22 | #include <linux/types.h> | |
23 | #include <linux/init.h> | |
24 | ||
25 | /* XXX no barriers? not even any volatiles? -- paulus */ | |
26 | #define CPC700_OUT_32(a,d) (*(u_int *)a = d) | |
27 | #define CPC700_IN_32(a) (*(u_int *)a) | |
28 | ||
29 | /* | |
30 | * PCI Section | |
31 | */ | |
32 | #define CPC700_PCI_CONFIG_ADDR 0xfec00000 | |
33 | #define CPC700_PCI_CONFIG_DATA 0xfec00004 | |
34 | ||
35 | /* CPU -> PCI memory window 0 */ | |
36 | #define CPC700_PMM0_LOCAL 0xff400000 /* CPU physical addr */ | |
37 | #define CPC700_PMM0_MASK_ATTR 0xff400004 /* size and attrs */ | |
38 | #define CPC700_PMM0_PCI_LOW 0xff400008 /* PCI addr, low word */ | |
39 | #define CPC700_PMM0_PCI_HIGH 0xff40000c /* PCI addr, high wd */ | |
40 | /* CPU -> PCI memory window 1 */ | |
41 | #define CPC700_PMM1_LOCAL 0xff400010 | |
42 | #define CPC700_PMM1_MASK_ATTR 0xff400014 | |
43 | #define CPC700_PMM1_PCI_LOW 0xff400018 | |
44 | #define CPC700_PMM1_PCI_HIGH 0xff40001c | |
45 | /* CPU -> PCI memory window 2 */ | |
46 | #define CPC700_PMM2_LOCAL 0xff400020 | |
47 | #define CPC700_PMM2_MASK_ATTR 0xff400024 | |
48 | #define CPC700_PMM2_PCI_LOW 0xff400028 | |
49 | #define CPC700_PMM2_PCI_HIGH 0xff40002c | |
50 | /* PCI memory -> CPU window 1 */ | |
51 | #define CPC700_PTM1_MEMSIZE 0xff400030 /* window size */ | |
52 | #define CPC700_PTM1_LOCAL 0xff400034 /* CPU phys addr */ | |
53 | /* PCI memory -> CPU window 2 */ | |
54 | #define CPC700_PTM2_MEMSIZE 0xff400038 /* size and enable */ | |
55 | #define CPC700_PTM2_LOCAL 0xff40003c | |
56 | ||
57 | /* | |
58 | * PIC Section | |
59 | * | |
60 | * IBM calls the CPC700's programmable interrupt controller the Universal | |
61 | * Interrupt Controller or UIC. | |
62 | */ | |
63 | ||
64 | /* | |
65 | * UIC Register Addresses. | |
66 | */ | |
67 | #define CPC700_UIC_UICSR 0xff500880 /* Status Reg (Rd/Clr)*/ | |
68 | #define CPC700_UIC_UICSRS 0xff500884 /* Status Reg (Set) */ | |
69 | #define CPC700_UIC_UICER 0xff500888 /* Enable Reg */ | |
70 | #define CPC700_UIC_UICCR 0xff50088c /* Critical Reg */ | |
71 | #define CPC700_UIC_UICPR 0xff500890 /* Polarity Reg */ | |
72 | #define CPC700_UIC_UICTR 0xff500894 /* Trigger Reg */ | |
73 | #define CPC700_UIC_UICMSR 0xff500898 /* Masked Status Reg */ | |
74 | #define CPC700_UIC_UICVR 0xff50089c /* Vector Reg */ | |
75 | #define CPC700_UIC_UICVCR 0xff5008a0 /* Vector Config Reg */ | |
76 | ||
77 | #define CPC700_UIC_UICER_ENABLE 0x00000001 /* Enable an IRQ */ | |
78 | ||
79 | #define CPC700_UIC_UICVCR_31_HI 0x00000000 /* IRQ 31 hi priority */ | |
80 | #define CPC700_UIC_UICVCR_0_HI 0x00000001 /* IRQ 0 hi priority */ | |
81 | #define CPC700_UIC_UICVCR_BASE_MASK 0xfffffffc | |
82 | #define CPC700_UIC_UICVCR_ORDER_MASK 0x00000001 | |
83 | ||
84 | /* Specify value of a bit for an IRQ. */ | |
85 | #define CPC700_UIC_IRQ_BIT(i) ((0x00000001) << (31 - (i))) | |
86 | ||
87 | /* | |
88 | * UIC Exports... | |
89 | */ | |
90 | extern struct hw_interrupt_type cpc700_pic; | |
91 | extern unsigned int cpc700_irq_assigns[32][2]; | |
92 | ||
93 | extern void __init cpc700_init_IRQ(void); | |
39e3eb72 | 94 | extern int cpc700_get_irq(void); |
1da177e4 LT |
95 | |
96 | #endif /* __PPC_SYSLIB_CPC700_H__ */ |