Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Common Motorola PowerPlus Platform--really Falcon/Raven or HAWK. |
3 | * | |
4 | * Author: Mark A. Greer | |
5 | * mgreer@mvista.com | |
6 | * | |
7 | * 2001 (c) MontaVista, Software, Inc. This file is licensed under | |
8 | * the terms of the GNU General Public License version 2. This program | |
9 | * is licensed "as is" without any warranty of any kind, whether express | |
10 | * or implied. | |
11 | */ | |
12 | #include <linux/kernel.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/pci.h> | |
15 | ||
16 | #include <asm/byteorder.h> | |
17 | #include <asm/io.h> | |
18 | #include <asm/irq.h> | |
19 | #include <asm/pci.h> | |
20 | #include <asm/pci-bridge.h> | |
21 | #include <asm/open_pic.h> | |
22 | #include <asm/hawk.h> | |
23 | ||
24 | /* | |
25 | * The Falcon/Raven and HAWK has 4 sets of registers: | |
26 | * 1) PPC Registers which define the mappings from PPC bus to PCI bus, | |
27 | * etc. | |
28 | * 2) PCI Registers which define the mappings from PCI bus to PPC bus and the | |
29 | * MPIC base address. | |
30 | * 3) MPIC registers. | |
31 | * 4) System Memory Controller (SMC) registers. | |
32 | */ | |
33 | ||
34 | /* | |
35 | * Initialize the Motorola MCG Raven or HAWK host bridge. | |
36 | * | |
37 | * This means setting up the PPC bus to PCI memory and I/O space mappings, | |
38 | * setting the PCI memory space address of the MPIC (mapped straight | |
39 | * through), and ioremap'ing the mpic registers. | |
40 | * This routine will set the PCI_CONFIG_ADDR or PCI_CONFIG_DATA | |
41 | * addresses based on the PCI I/O address that is passed in. | |
42 | * 'OpenPIC_Addr' will be set correctly by this routine. | |
43 | */ | |
44 | int __init | |
45 | hawk_init(struct pci_controller *hose, | |
46 | uint ppc_reg_base, | |
47 | ulong processor_pci_mem_start, | |
48 | ulong processor_pci_mem_end, | |
49 | ulong processor_pci_io_start, | |
50 | ulong processor_pci_io_end, | |
51 | ulong processor_mpic_base) | |
52 | { | |
53 | uint addr, offset; | |
54 | ||
55 | /* | |
56 | * Some sanity checks... | |
57 | */ | |
58 | if (((processor_pci_mem_start&0xffff0000) != processor_pci_mem_start) || | |
59 | ((processor_pci_io_start &0xffff0000) != processor_pci_io_start)) { | |
60 | printk("hawk_init: %s\n", | |
61 | "PPC to PCI mappings must start on 64 KB boundaries"); | |
62 | return -1; | |
63 | } | |
64 | ||
65 | if (((processor_pci_mem_end &0x0000ffff) != 0x0000ffff) || | |
66 | ((processor_pci_io_end &0x0000ffff) != 0x0000ffff)) { | |
67 | printk("hawk_init: PPC to PCI mappings %s\n", | |
68 | "must end just before a 64 KB boundaries"); | |
69 | return -1; | |
70 | } | |
71 | ||
72 | if (((processor_pci_mem_end - processor_pci_mem_start) != | |
73 | (hose->mem_space.end - hose->mem_space.start)) || | |
74 | ((processor_pci_io_end - processor_pci_io_start) != | |
75 | (hose->io_space.end - hose->io_space.start))) { | |
76 | printk("hawk_init: %s\n", | |
77 | "PPC and PCI memory or I/O space sizes don't match"); | |
78 | return -1; | |
79 | } | |
80 | ||
81 | if ((processor_mpic_base & 0xfffc0000) != processor_mpic_base) { | |
82 | printk("hawk_init: %s\n", | |
83 | "MPIC address must start on 256 MB boundary"); | |
84 | return -1; | |
85 | } | |
86 | ||
87 | if ((pci_dram_offset & 0xffff0000) != pci_dram_offset) { | |
88 | printk("hawk_init: %s\n", | |
89 | "pci_dram_offset must be multiple of 64 KB"); | |
90 | return -1; | |
91 | } | |
92 | ||
93 | /* | |
94 | * Disable previous PPC->PCI mappings. | |
95 | */ | |
96 | out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF0_OFF), 0x00000000); | |
97 | out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF1_OFF), 0x00000000); | |
98 | out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF2_OFF), 0x00000000); | |
99 | out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF3_OFF), 0x00000000); | |
100 | ||
101 | /* | |
102 | * Program the XSADD/XSOFF registers to set up the PCI Mem & I/O | |
103 | * space mappings. These are the mappings going from the processor to | |
104 | * the PCI bus. | |
105 | * | |
106 | * Note: Don't need to 'AND' start/end addresses with 0xffff0000 | |
107 | * because sanity check above ensures that they are properly | |
108 | * aligned. | |
109 | */ | |
110 | ||
111 | /* Set up PPC->PCI Mem mapping */ | |
112 | addr = processor_pci_mem_start | (processor_pci_mem_end >> 16); | |
113 | offset = (hose->mem_space.start - processor_pci_mem_start) | 0xd2; | |
114 | out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSADD0_OFF), addr); | |
115 | out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF0_OFF), offset); | |
116 | ||
117 | /* Set up PPC->MPIC mapping on the bridge */ | |
118 | addr = processor_mpic_base | | |
119 | (((processor_mpic_base + HAWK_MPIC_SIZE) >> 16) - 1); | |
120 | /* No write posting for this PCI Mem space */ | |
121 | offset = (hose->mem_space.start - processor_pci_mem_start) | 0xc2; | |
122 | ||
123 | out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSADD1_OFF), addr); | |
124 | out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF1_OFF), offset); | |
125 | ||
126 | /* Set up PPC->PCI I/O mapping -- Contiguous I/O space */ | |
127 | addr = processor_pci_io_start | (processor_pci_io_end >> 16); | |
128 | offset = (hose->io_space.start - processor_pci_io_start) | 0xc0; | |
129 | out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSADD3_OFF), addr); | |
130 | out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF3_OFF), offset); | |
131 | ||
132 | hose->io_base_virt = (void *)ioremap(processor_pci_io_start, | |
133 | (processor_pci_io_end - processor_pci_io_start + 1)); | |
134 | ||
135 | /* | |
136 | * Set up the indirect method of accessing PCI config space. | |
137 | * The PCI config addr/data pair based on start addr of PCI I/O space. | |
138 | */ | |
139 | setup_indirect_pci(hose, | |
140 | processor_pci_io_start + HAWK_PCI_CONFIG_ADDR_OFF, | |
141 | processor_pci_io_start + HAWK_PCI_CONFIG_DATA_OFF); | |
142 | ||
143 | /* | |
144 | * Disable previous PCI->PPC mappings. | |
145 | */ | |
146 | ||
147 | /* XXXX Put in mappings from PCI bus to processor bus XXXX */ | |
148 | ||
149 | /* | |
150 | * Disable MPIC response to PCI I/O space (BAR 0). | |
151 | * Make MPIC respond to PCI Mem space at specified address. | |
152 | * (BAR 1). | |
153 | */ | |
154 | early_write_config_dword(hose, | |
155 | 0, | |
156 | PCI_DEVFN(0,0), | |
157 | PCI_BASE_ADDRESS_0, | |
158 | 0x00000000 | 0x1); | |
159 | ||
160 | early_write_config_dword(hose, | |
161 | 0, | |
162 | PCI_DEVFN(0,0), | |
163 | PCI_BASE_ADDRESS_1, | |
164 | (processor_mpic_base - | |
165 | processor_pci_mem_start + | |
166 | hose->mem_space.start) | 0x0); | |
167 | ||
168 | /* Map MPIC into vitual memory */ | |
169 | OpenPIC_Addr = ioremap(processor_mpic_base, HAWK_MPIC_SIZE); | |
170 | ||
171 | return 0; | |
172 | } | |
173 | ||
174 | /* | |
175 | * Find the amount of RAM present. | |
176 | * This assumes that PPCBug has initialized the memory controller (SMC) | |
177 | * on the Falcon/HAWK correctly (i.e., it does no sanity checking). | |
178 | * It also assumes that the memory base registers are set to configure the | |
179 | * memory as contigous starting with "RAM A BASE", "RAM B BASE", etc. | |
180 | * however, RAM base registers can be skipped (e.g. A, B, C are set, | |
181 | * D is skipped but E is set is okay). | |
182 | */ | |
183 | #define MB (1024*1024) | |
184 | ||
185 | static uint reg_offset_table[] __initdata = { | |
186 | HAWK_SMC_RAM_A_SIZE_REG_OFF, | |
187 | HAWK_SMC_RAM_B_SIZE_REG_OFF, | |
188 | HAWK_SMC_RAM_C_SIZE_REG_OFF, | |
189 | HAWK_SMC_RAM_D_SIZE_REG_OFF, | |
190 | HAWK_SMC_RAM_E_SIZE_REG_OFF, | |
191 | HAWK_SMC_RAM_F_SIZE_REG_OFF, | |
192 | HAWK_SMC_RAM_G_SIZE_REG_OFF, | |
193 | HAWK_SMC_RAM_H_SIZE_REG_OFF | |
194 | }; | |
195 | ||
196 | static uint falcon_size_table[] __initdata = { | |
197 | 0 * MB, /* 0 ==> 0 MB */ | |
198 | 16 * MB, /* 1 ==> 16 MB */ | |
199 | 32 * MB, /* 2 ==> 32 MB */ | |
200 | 64 * MB, /* 3 ==> 64 MB */ | |
201 | 128 * MB, /* 4 ==> 128 MB */ | |
202 | 256 * MB, /* 5 ==> 256 MB */ | |
203 | 1024 * MB, /* 6 ==> 1024 MB (1 GB) */ | |
204 | }; | |
205 | ||
206 | static uint hawk_size_table[] __initdata = { | |
207 | 0 * MB, /* 0 ==> 0 MB */ | |
208 | 32 * MB, /* 1 ==> 32 MB */ | |
209 | 64 * MB, /* 2 ==> 64 MB */ | |
210 | 64 * MB, /* 3 ==> 64 MB */ | |
211 | 128 * MB, /* 4 ==> 128 MB */ | |
212 | 128 * MB, /* 5 ==> 128 MB */ | |
213 | 128 * MB, /* 6 ==> 128 MB */ | |
214 | 256 * MB, /* 7 ==> 256 MB */ | |
215 | 256 * MB, /* 8 ==> 256 MB */ | |
216 | 512 * MB, /* 9 ==> 512 MB */ | |
217 | }; | |
218 | ||
219 | /* | |
220 | * *** WARNING: You MUST have a BAT set up to map in the SMC regs *** | |
221 | * | |
222 | * Read the memory controller's registers to determine the amount of system | |
223 | * memory. Assumes that the memory controller registers are already mapped | |
224 | * into virtual memory--too early to use ioremap(). | |
225 | */ | |
226 | unsigned long __init | |
227 | hawk_get_mem_size(uint smc_base) | |
228 | { | |
229 | unsigned long total; | |
230 | int i, size_table_entries, reg_limit; | |
231 | uint vend_dev_id; | |
232 | uint *size_table; | |
233 | u_char val; | |
234 | ||
235 | ||
236 | vend_dev_id = in_be32((uint *)smc_base + PCI_VENDOR_ID); | |
237 | ||
238 | if (((vend_dev_id & 0xffff0000) >> 16) != PCI_VENDOR_ID_MOTOROLA) { | |
239 | printk("hawk_get_mem_size: %s (0x%x)\n", | |
240 | "Not a Motorola Memory Controller", vend_dev_id); | |
241 | return 0; | |
242 | } | |
243 | ||
244 | vend_dev_id &= 0x0000ffff; | |
245 | ||
246 | if (vend_dev_id == PCI_DEVICE_ID_MOTOROLA_FALCON) { | |
247 | size_table = falcon_size_table; | |
248 | size_table_entries = sizeof(falcon_size_table) / | |
249 | sizeof(falcon_size_table[0]); | |
250 | ||
251 | reg_limit = FALCON_SMC_REG_COUNT; | |
252 | } | |
253 | else if (vend_dev_id == PCI_DEVICE_ID_MOTOROLA_HAWK) { | |
254 | size_table = hawk_size_table; | |
255 | size_table_entries = sizeof(hawk_size_table) / | |
256 | sizeof(hawk_size_table[0]); | |
257 | reg_limit = HAWK_SMC_REG_COUNT; | |
258 | } | |
259 | else { | |
260 | printk("hawk_get_mem_size: %s (0x%x)\n", | |
261 | "Not a Falcon or HAWK", vend_dev_id); | |
262 | return 0; | |
263 | } | |
264 | ||
265 | total = 0; | |
266 | ||
267 | /* Check every reg because PPCBug may skip some */ | |
268 | for (i=0; i<reg_limit; i++) { | |
269 | val = in_8((u_char *)(smc_base + reg_offset_table[i])); | |
270 | ||
271 | if (val & 0x80) { /* If enabled */ | |
272 | val &= 0x0f; | |
273 | ||
274 | /* Don't go past end of size_table */ | |
275 | if (val < size_table_entries) { | |
276 | total += size_table[val]; | |
277 | } | |
278 | else { /* Register not set correctly */ | |
279 | break; | |
280 | } | |
281 | } | |
282 | } | |
283 | ||
284 | return total; | |
285 | } | |
286 | ||
287 | int __init | |
288 | hawk_mpic_init(unsigned int pci_mem_offset) | |
289 | { | |
290 | unsigned short devid; | |
291 | unsigned int pci_membase; | |
292 | ||
293 | /* Check the first PCI device to see if it is a Raven or Hawk. */ | |
294 | early_read_config_word(0, 0, 0, PCI_DEVICE_ID, &devid); | |
295 | ||
296 | switch (devid) { | |
297 | case PCI_DEVICE_ID_MOTOROLA_RAVEN: | |
298 | case PCI_DEVICE_ID_MOTOROLA_HAWK: | |
299 | break; | |
300 | default: | |
301 | OpenPIC_Addr = NULL; | |
302 | return 1; | |
303 | } | |
304 | ||
305 | /* Read the memory base register. */ | |
306 | early_read_config_dword(0, 0, 0, PCI_BASE_ADDRESS_1, &pci_membase); | |
307 | ||
308 | if (pci_membase == 0) { | |
309 | OpenPIC_Addr = NULL; | |
310 | return 1; | |
311 | } | |
312 | ||
313 | /* Map the MPIC registers to virtual memory. */ | |
314 | OpenPIC_Addr = ioremap(pci_membase + pci_mem_offset, 0x22000); | |
315 | ||
316 | return 0; | |
317 | } |