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1da177e4 LT |
1 | /* |
2 | * arch/ppc/kernel/open_pic.c -- OpenPIC Interrupt Handling | |
3 | * | |
4 | * Copyright (C) 1997 Geert Uytterhoeven | |
5 | * | |
6 | * This file is subject to the terms and conditions of the GNU General Public | |
7 | * License. See the file COPYING in the main directory of this archive | |
8 | * for more details. | |
9 | * | |
10 | * This is a duplicate of open_pic.c that deals with U3s MPIC on | |
11 | * G5 PowerMacs. It's the same file except it's using big endian | |
12 | * register accesses | |
13 | */ | |
14 | ||
15 | #include <linux/config.h> | |
16 | #include <linux/types.h> | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/sched.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/irq.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/sysdev.h> | |
23 | #include <linux/errno.h> | |
24 | #include <asm/ptrace.h> | |
25 | #include <asm/signal.h> | |
26 | #include <asm/io.h> | |
27 | #include <asm/irq.h> | |
1da177e4 LT |
28 | #include <asm/sections.h> |
29 | #include <asm/open_pic.h> | |
30 | #include <asm/i8259.h> | |
31 | ||
32 | #include "open_pic_defs.h" | |
33 | ||
34 | void *OpenPIC2_Addr; | |
35 | static volatile struct OpenPIC *OpenPIC2 = NULL; | |
36 | /* | |
37 | * We define OpenPIC_InitSenses table thusly: | |
38 | * bit 0x1: sense, 0 for edge and 1 for level. | |
39 | * bit 0x2: polarity, 0 for negative, 1 for positive. | |
40 | */ | |
41 | extern u_int OpenPIC_NumInitSenses; | |
42 | extern u_char *OpenPIC_InitSenses; | |
43 | extern int use_of_interrupt_tree; | |
44 | ||
45 | static u_int NumProcessors; | |
46 | static u_int NumSources; | |
47 | static int open_pic2_irq_offset; | |
48 | static volatile OpenPIC_Source *ISR[NR_IRQS]; | |
49 | ||
50 | /* Global Operations */ | |
51 | static void openpic2_disable_8259_pass_through(void); | |
52 | static void openpic2_set_priority(u_int pri); | |
53 | static void openpic2_set_spurious(u_int vector); | |
54 | ||
55 | /* Timer Interrupts */ | |
56 | static void openpic2_inittimer(u_int timer, u_int pri, u_int vector); | |
57 | static void openpic2_maptimer(u_int timer, u_int cpumask); | |
58 | ||
59 | /* Interrupt Sources */ | |
60 | static void openpic2_enable_irq(u_int irq); | |
61 | static void openpic2_disable_irq(u_int irq); | |
62 | static void openpic2_initirq(u_int irq, u_int pri, u_int vector, int polarity, | |
63 | int is_level); | |
64 | static void openpic2_mapirq(u_int irq, u_int cpumask, u_int keepmask); | |
65 | ||
66 | /* | |
67 | * These functions are not used but the code is kept here | |
68 | * for completeness and future reference. | |
69 | */ | |
70 | static void openpic2_reset(void); | |
71 | #ifdef notused | |
72 | static void openpic2_enable_8259_pass_through(void); | |
73 | static u_int openpic2_get_priority(void); | |
74 | static u_int openpic2_get_spurious(void); | |
75 | static void openpic2_set_sense(u_int irq, int sense); | |
76 | #endif /* notused */ | |
77 | ||
78 | /* | |
79 | * Description of the openpic for the higher-level irq code | |
80 | */ | |
81 | static void openpic2_end_irq(unsigned int irq_nr); | |
82 | static void openpic2_ack_irq(unsigned int irq_nr); | |
83 | ||
84 | struct hw_interrupt_type open_pic2 = { | |
85 | " OpenPIC2 ", | |
86 | NULL, | |
87 | NULL, | |
88 | openpic2_enable_irq, | |
89 | openpic2_disable_irq, | |
90 | openpic2_ack_irq, | |
91 | openpic2_end_irq, | |
92 | }; | |
93 | ||
94 | /* | |
95 | * Accesses to the current processor's openpic registers | |
96 | * On cascaded controller, this is only CPU 0 | |
97 | */ | |
98 | #define THIS_CPU Processor[0] | |
99 | #define DECL_THIS_CPU | |
100 | #define CHECK_THIS_CPU | |
101 | ||
102 | #if 1 | |
103 | #define check_arg_ipi(ipi) \ | |
104 | if (ipi < 0 || ipi >= OPENPIC_NUM_IPI) \ | |
105 | printk("open_pic.c:%d: illegal ipi %d\n", __LINE__, ipi); | |
106 | #define check_arg_timer(timer) \ | |
107 | if (timer < 0 || timer >= OPENPIC_NUM_TIMERS) \ | |
108 | printk("open_pic.c:%d: illegal timer %d\n", __LINE__, timer); | |
109 | #define check_arg_vec(vec) \ | |
110 | if (vec < 0 || vec >= OPENPIC_NUM_VECTORS) \ | |
111 | printk("open_pic.c:%d: illegal vector %d\n", __LINE__, vec); | |
112 | #define check_arg_pri(pri) \ | |
113 | if (pri < 0 || pri >= OPENPIC_NUM_PRI) \ | |
114 | printk("open_pic.c:%d: illegal priority %d\n", __LINE__, pri); | |
115 | /* | |
116 | * Print out a backtrace if it's out of range, since if it's larger than NR_IRQ's | |
117 | * data has probably been corrupted and we're going to panic or deadlock later | |
118 | * anyway --Troy | |
119 | */ | |
120 | extern unsigned long* _get_SP(void); | |
121 | #define check_arg_irq(irq) \ | |
122 | if (irq < open_pic2_irq_offset || irq >= NumSources+open_pic2_irq_offset \ | |
123 | || ISR[irq - open_pic2_irq_offset] == 0) { \ | |
124 | printk("open_pic.c:%d: illegal irq %d\n", __LINE__, irq); \ | |
125 | /*print_backtrace(_get_SP());*/ } | |
126 | #define check_arg_cpu(cpu) \ | |
127 | if (cpu < 0 || cpu >= NumProcessors){ \ | |
128 | printk("open_pic2.c:%d: illegal cpu %d\n", __LINE__, cpu); \ | |
129 | /*print_backtrace(_get_SP());*/ } | |
130 | #else | |
131 | #define check_arg_ipi(ipi) do {} while (0) | |
132 | #define check_arg_timer(timer) do {} while (0) | |
133 | #define check_arg_vec(vec) do {} while (0) | |
134 | #define check_arg_pri(pri) do {} while (0) | |
135 | #define check_arg_irq(irq) do {} while (0) | |
136 | #define check_arg_cpu(cpu) do {} while (0) | |
137 | #endif | |
138 | ||
139 | static u_int openpic2_read(volatile u_int *addr) | |
140 | { | |
141 | u_int val; | |
142 | ||
143 | val = in_be32(addr); | |
144 | return val; | |
145 | } | |
146 | ||
147 | static inline void openpic2_write(volatile u_int *addr, u_int val) | |
148 | { | |
149 | out_be32(addr, val); | |
150 | } | |
151 | ||
152 | static inline u_int openpic2_readfield(volatile u_int *addr, u_int mask) | |
153 | { | |
154 | u_int val = openpic2_read(addr); | |
155 | return val & mask; | |
156 | } | |
157 | ||
158 | inline void openpic2_writefield(volatile u_int *addr, u_int mask, | |
159 | u_int field) | |
160 | { | |
161 | u_int val = openpic2_read(addr); | |
162 | openpic2_write(addr, (val & ~mask) | (field & mask)); | |
163 | } | |
164 | ||
165 | static inline void openpic2_clearfield(volatile u_int *addr, u_int mask) | |
166 | { | |
167 | openpic2_writefield(addr, mask, 0); | |
168 | } | |
169 | ||
170 | static inline void openpic2_setfield(volatile u_int *addr, u_int mask) | |
171 | { | |
172 | openpic2_writefield(addr, mask, mask); | |
173 | } | |
174 | ||
175 | static void openpic2_safe_writefield(volatile u_int *addr, u_int mask, | |
176 | u_int field) | |
177 | { | |
178 | openpic2_setfield(addr, OPENPIC_MASK); | |
179 | while (openpic2_read(addr) & OPENPIC_ACTIVITY); | |
180 | openpic2_writefield(addr, mask | OPENPIC_MASK, field | OPENPIC_MASK); | |
181 | } | |
182 | ||
183 | static void openpic2_reset(void) | |
184 | { | |
185 | openpic2_setfield(&OpenPIC2->Global.Global_Configuration0, | |
186 | OPENPIC_CONFIG_RESET); | |
187 | while (openpic2_readfield(&OpenPIC2->Global.Global_Configuration0, | |
188 | OPENPIC_CONFIG_RESET)) | |
189 | mb(); | |
190 | } | |
191 | ||
192 | void __init openpic2_set_sources(int first_irq, int num_irqs, void *first_ISR) | |
193 | { | |
194 | volatile OpenPIC_Source *src = first_ISR; | |
195 | int i, last_irq; | |
196 | ||
197 | last_irq = first_irq + num_irqs; | |
198 | if (last_irq > NumSources) | |
199 | NumSources = last_irq; | |
200 | if (src == 0) | |
201 | src = &((struct OpenPIC *)OpenPIC2_Addr)->Source[first_irq]; | |
202 | for (i = first_irq; i < last_irq; ++i, ++src) | |
203 | ISR[i] = src; | |
204 | } | |
205 | ||
206 | /* | |
207 | * The `offset' parameter defines where the interrupts handled by the | |
208 | * OpenPIC start in the space of interrupt numbers that the kernel knows | |
209 | * about. In other words, the OpenPIC's IRQ0 is numbered `offset' in the | |
210 | * kernel's interrupt numbering scheme. | |
211 | * We assume there is only one OpenPIC. | |
212 | */ | |
213 | void __init openpic2_init(int offset) | |
214 | { | |
215 | u_int t, i; | |
216 | u_int timerfreq; | |
217 | const char *version; | |
218 | ||
219 | if (!OpenPIC2_Addr) { | |
220 | printk("No OpenPIC2 found !\n"); | |
221 | return; | |
222 | } | |
223 | OpenPIC2 = (volatile struct OpenPIC *)OpenPIC2_Addr; | |
224 | ||
225 | if (ppc_md.progress) ppc_md.progress("openpic: enter", 0x122); | |
226 | ||
227 | t = openpic2_read(&OpenPIC2->Global.Feature_Reporting0); | |
228 | switch (t & OPENPIC_FEATURE_VERSION_MASK) { | |
229 | case 1: | |
230 | version = "1.0"; | |
231 | break; | |
232 | case 2: | |
233 | version = "1.2"; | |
234 | break; | |
235 | case 3: | |
236 | version = "1.3"; | |
237 | break; | |
238 | default: | |
239 | version = "?"; | |
240 | break; | |
241 | } | |
242 | NumProcessors = ((t & OPENPIC_FEATURE_LAST_PROCESSOR_MASK) >> | |
243 | OPENPIC_FEATURE_LAST_PROCESSOR_SHIFT) + 1; | |
244 | if (NumSources == 0) | |
245 | openpic2_set_sources(0, | |
246 | ((t & OPENPIC_FEATURE_LAST_SOURCE_MASK) >> | |
247 | OPENPIC_FEATURE_LAST_SOURCE_SHIFT) + 1, | |
248 | NULL); | |
249 | printk("OpenPIC (2) Version %s (%d CPUs and %d IRQ sources) at %p\n", | |
250 | version, NumProcessors, NumSources, OpenPIC2); | |
251 | timerfreq = openpic2_read(&OpenPIC2->Global.Timer_Frequency); | |
252 | if (timerfreq) | |
253 | printk("OpenPIC timer frequency is %d.%06d MHz\n", | |
254 | timerfreq / 1000000, timerfreq % 1000000); | |
255 | ||
256 | open_pic2_irq_offset = offset; | |
257 | ||
258 | /* Initialize timer interrupts */ | |
259 | if ( ppc_md.progress ) ppc_md.progress("openpic2: timer",0x3ba); | |
260 | for (i = 0; i < OPENPIC_NUM_TIMERS; i++) { | |
261 | /* Disabled, Priority 0 */ | |
262 | openpic2_inittimer(i, 0, OPENPIC2_VEC_TIMER+i+offset); | |
263 | /* No processor */ | |
264 | openpic2_maptimer(i, 0); | |
265 | } | |
266 | ||
267 | /* Initialize external interrupts */ | |
268 | if (ppc_md.progress) ppc_md.progress("openpic2: external",0x3bc); | |
269 | ||
270 | openpic2_set_priority(0xf); | |
271 | ||
272 | /* Init all external sources, including possibly the cascade. */ | |
273 | for (i = 0; i < NumSources; i++) { | |
274 | int sense; | |
275 | ||
276 | if (ISR[i] == 0) | |
277 | continue; | |
278 | ||
279 | /* the bootloader may have left it enabled (bad !) */ | |
280 | openpic2_disable_irq(i+offset); | |
281 | ||
282 | sense = (i < OpenPIC_NumInitSenses)? OpenPIC_InitSenses[i]: \ | |
283 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE); | |
284 | ||
285 | if (sense & IRQ_SENSE_MASK) | |
286 | irq_desc[i+offset].status = IRQ_LEVEL; | |
287 | ||
288 | /* Enabled, Priority 8 */ | |
289 | openpic2_initirq(i, 8, i+offset, (sense & IRQ_POLARITY_MASK), | |
290 | (sense & IRQ_SENSE_MASK)); | |
291 | /* Processor 0 */ | |
292 | openpic2_mapirq(i, 1<<0, 0); | |
293 | } | |
294 | ||
295 | /* Init descriptors */ | |
296 | for (i = offset; i < NumSources + offset; i++) | |
297 | irq_desc[i].handler = &open_pic2; | |
298 | ||
299 | /* Initialize the spurious interrupt */ | |
300 | if (ppc_md.progress) ppc_md.progress("openpic2: spurious",0x3bd); | |
301 | openpic2_set_spurious(OPENPIC2_VEC_SPURIOUS+offset); | |
302 | ||
303 | openpic2_disable_8259_pass_through(); | |
304 | openpic2_set_priority(0); | |
305 | ||
306 | if (ppc_md.progress) ppc_md.progress("openpic2: exit",0x222); | |
307 | } | |
308 | ||
309 | #ifdef notused | |
310 | static void openpic2_enable_8259_pass_through(void) | |
311 | { | |
312 | openpic2_clearfield(&OpenPIC2->Global.Global_Configuration0, | |
313 | OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE); | |
314 | } | |
315 | #endif /* notused */ | |
316 | ||
317 | /* This can't be __init, it is used in openpic_sleep_restore_intrs */ | |
318 | static void openpic2_disable_8259_pass_through(void) | |
319 | { | |
320 | openpic2_setfield(&OpenPIC2->Global.Global_Configuration0, | |
321 | OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE); | |
322 | } | |
323 | ||
324 | /* | |
325 | * Find out the current interrupt | |
326 | */ | |
327 | u_int openpic2_irq(void) | |
328 | { | |
329 | u_int vec; | |
330 | DECL_THIS_CPU; | |
331 | ||
332 | CHECK_THIS_CPU; | |
333 | vec = openpic2_readfield(&OpenPIC2->THIS_CPU.Interrupt_Acknowledge, | |
334 | OPENPIC_VECTOR_MASK); | |
335 | return vec; | |
336 | } | |
337 | ||
338 | void openpic2_eoi(void) | |
339 | { | |
340 | DECL_THIS_CPU; | |
341 | ||
342 | CHECK_THIS_CPU; | |
343 | openpic2_write(&OpenPIC2->THIS_CPU.EOI, 0); | |
344 | /* Handle PCI write posting */ | |
345 | (void)openpic2_read(&OpenPIC2->THIS_CPU.EOI); | |
346 | } | |
347 | ||
348 | #ifdef notused | |
349 | static u_int openpic2_get_priority(void) | |
350 | { | |
351 | DECL_THIS_CPU; | |
352 | ||
353 | CHECK_THIS_CPU; | |
354 | return openpic2_readfield(&OpenPIC2->THIS_CPU.Current_Task_Priority, | |
355 | OPENPIC_CURRENT_TASK_PRIORITY_MASK); | |
356 | } | |
357 | #endif /* notused */ | |
358 | ||
359 | static void __init openpic2_set_priority(u_int pri) | |
360 | { | |
361 | DECL_THIS_CPU; | |
362 | ||
363 | CHECK_THIS_CPU; | |
364 | check_arg_pri(pri); | |
365 | openpic2_writefield(&OpenPIC2->THIS_CPU.Current_Task_Priority, | |
366 | OPENPIC_CURRENT_TASK_PRIORITY_MASK, pri); | |
367 | } | |
368 | ||
369 | /* | |
370 | * Get/set the spurious vector | |
371 | */ | |
372 | #ifdef notused | |
373 | static u_int openpic2_get_spurious(void) | |
374 | { | |
375 | return openpic2_readfield(&OpenPIC2->Global.Spurious_Vector, | |
376 | OPENPIC_VECTOR_MASK); | |
377 | } | |
378 | #endif /* notused */ | |
379 | ||
380 | /* This can't be __init, it is used in openpic_sleep_restore_intrs */ | |
381 | static void openpic2_set_spurious(u_int vec) | |
382 | { | |
383 | check_arg_vec(vec); | |
384 | openpic2_writefield(&OpenPIC2->Global.Spurious_Vector, OPENPIC_VECTOR_MASK, | |
385 | vec); | |
386 | } | |
387 | ||
388 | static DEFINE_SPINLOCK(openpic2_setup_lock); | |
389 | ||
390 | /* | |
391 | * Initialize a timer interrupt (and disable it) | |
392 | * | |
393 | * timer: OpenPIC timer number | |
394 | * pri: interrupt source priority | |
395 | * vec: the vector it will produce | |
396 | */ | |
397 | static void __init openpic2_inittimer(u_int timer, u_int pri, u_int vec) | |
398 | { | |
399 | check_arg_timer(timer); | |
400 | check_arg_pri(pri); | |
401 | check_arg_vec(vec); | |
402 | openpic2_safe_writefield(&OpenPIC2->Global.Timer[timer].Vector_Priority, | |
403 | OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK, | |
404 | (pri << OPENPIC_PRIORITY_SHIFT) | vec); | |
405 | } | |
406 | ||
407 | /* | |
408 | * Map a timer interrupt to one or more CPUs | |
409 | */ | |
410 | static void __init openpic2_maptimer(u_int timer, u_int cpumask) | |
411 | { | |
412 | check_arg_timer(timer); | |
413 | openpic2_write(&OpenPIC2->Global.Timer[timer].Destination, | |
414 | cpumask); | |
415 | } | |
416 | ||
417 | /* | |
418 | * Initalize the interrupt source which will generate an NMI. | |
419 | * This raises the interrupt's priority from 8 to 9. | |
420 | * | |
421 | * irq: The logical IRQ which generates an NMI. | |
422 | */ | |
423 | void __init | |
424 | openpic2_init_nmi_irq(u_int irq) | |
425 | { | |
426 | check_arg_irq(irq); | |
427 | openpic2_safe_writefield(&ISR[irq - open_pic2_irq_offset]->Vector_Priority, | |
428 | OPENPIC_PRIORITY_MASK, | |
429 | 9 << OPENPIC_PRIORITY_SHIFT); | |
430 | } | |
431 | ||
432 | /* | |
433 | * | |
434 | * All functions below take an offset'ed irq argument | |
435 | * | |
436 | */ | |
437 | ||
438 | ||
439 | /* | |
440 | * Enable/disable an external interrupt source | |
441 | * | |
442 | * Externally called, irq is an offseted system-wide interrupt number | |
443 | */ | |
444 | static void openpic2_enable_irq(u_int irq) | |
445 | { | |
446 | volatile u_int *vpp; | |
447 | ||
448 | check_arg_irq(irq); | |
449 | vpp = &ISR[irq - open_pic2_irq_offset]->Vector_Priority; | |
450 | openpic2_clearfield(vpp, OPENPIC_MASK); | |
451 | /* make sure mask gets to controller before we return to user */ | |
452 | do { | |
453 | mb(); /* sync is probably useless here */ | |
454 | } while (openpic2_readfield(vpp, OPENPIC_MASK)); | |
455 | } | |
456 | ||
457 | static void openpic2_disable_irq(u_int irq) | |
458 | { | |
459 | volatile u_int *vpp; | |
460 | u32 vp; | |
461 | ||
462 | check_arg_irq(irq); | |
463 | vpp = &ISR[irq - open_pic2_irq_offset]->Vector_Priority; | |
464 | openpic2_setfield(vpp, OPENPIC_MASK); | |
465 | /* make sure mask gets to controller before we return to user */ | |
466 | do { | |
467 | mb(); /* sync is probably useless here */ | |
468 | vp = openpic2_readfield(vpp, OPENPIC_MASK | OPENPIC_ACTIVITY); | |
469 | } while((vp & OPENPIC_ACTIVITY) && !(vp & OPENPIC_MASK)); | |
470 | } | |
471 | ||
472 | ||
473 | /* | |
474 | * Initialize an interrupt source (and disable it!) | |
475 | * | |
476 | * irq: OpenPIC interrupt number | |
477 | * pri: interrupt source priority | |
478 | * vec: the vector it will produce | |
479 | * pol: polarity (1 for positive, 0 for negative) | |
480 | * sense: 1 for level, 0 for edge | |
481 | */ | |
482 | static void __init | |
483 | openpic2_initirq(u_int irq, u_int pri, u_int vec, int pol, int sense) | |
484 | { | |
485 | openpic2_safe_writefield(&ISR[irq]->Vector_Priority, | |
486 | OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK | | |
487 | OPENPIC_SENSE_MASK | OPENPIC_POLARITY_MASK, | |
488 | (pri << OPENPIC_PRIORITY_SHIFT) | vec | | |
489 | (pol ? OPENPIC_POLARITY_POSITIVE : | |
490 | OPENPIC_POLARITY_NEGATIVE) | | |
491 | (sense ? OPENPIC_SENSE_LEVEL : OPENPIC_SENSE_EDGE)); | |
492 | } | |
493 | ||
494 | /* | |
495 | * Map an interrupt source to one or more CPUs | |
496 | */ | |
497 | static void openpic2_mapirq(u_int irq, u_int physmask, u_int keepmask) | |
498 | { | |
499 | if (ISR[irq] == 0) | |
500 | return; | |
501 | if (keepmask != 0) | |
502 | physmask |= openpic2_read(&ISR[irq]->Destination) & keepmask; | |
503 | openpic2_write(&ISR[irq]->Destination, physmask); | |
504 | } | |
505 | ||
506 | #ifdef notused | |
507 | /* | |
508 | * Set the sense for an interrupt source (and disable it!) | |
509 | * | |
510 | * sense: 1 for level, 0 for edge | |
511 | */ | |
512 | static void openpic2_set_sense(u_int irq, int sense) | |
513 | { | |
514 | if (ISR[irq] != 0) | |
515 | openpic2_safe_writefield(&ISR[irq]->Vector_Priority, | |
516 | OPENPIC_SENSE_LEVEL, | |
517 | (sense ? OPENPIC_SENSE_LEVEL : 0)); | |
518 | } | |
519 | #endif /* notused */ | |
520 | ||
521 | /* No spinlocks, should not be necessary with the OpenPIC | |
522 | * (1 register = 1 interrupt and we have the desc lock). | |
523 | */ | |
524 | static void openpic2_ack_irq(unsigned int irq_nr) | |
525 | { | |
526 | openpic2_disable_irq(irq_nr); | |
527 | openpic2_eoi(); | |
528 | } | |
529 | ||
530 | static void openpic2_end_irq(unsigned int irq_nr) | |
531 | { | |
532 | if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))) | |
533 | openpic2_enable_irq(irq_nr); | |
534 | } | |
535 | ||
536 | int | |
537 | openpic2_get_irq(struct pt_regs *regs) | |
538 | { | |
539 | int irq = openpic2_irq(); | |
540 | ||
541 | if (irq == (OPENPIC2_VEC_SPURIOUS + open_pic2_irq_offset)) | |
542 | irq = -1; | |
543 | return irq; | |
544 | } | |
545 | ||
546 | #ifdef CONFIG_PM | |
547 | ||
548 | /* | |
549 | * We implement the IRQ controller as a sysdev and put it | |
550 | * to sleep at powerdown stage (the callback is named suspend, | |
551 | * but it's old semantics, for the Device Model, it's really | |
552 | * powerdown). The possible problem is that another sysdev that | |
553 | * happens to be suspend after this one will have interrupts off, | |
554 | * that may be an issue... For now, this isn't an issue on pmac | |
555 | * though... | |
556 | */ | |
557 | ||
558 | static u32 save_ipi_vp[OPENPIC_NUM_IPI]; | |
559 | static u32 save_irq_src_vp[OPENPIC_MAX_SOURCES]; | |
560 | static u32 save_irq_src_dest[OPENPIC_MAX_SOURCES]; | |
561 | static u32 save_cpu_task_pri[OPENPIC_MAX_PROCESSORS]; | |
562 | static int openpic_suspend_count; | |
563 | ||
564 | static void openpic2_cached_enable_irq(u_int irq) | |
565 | { | |
566 | check_arg_irq(irq); | |
567 | save_irq_src_vp[irq - open_pic2_irq_offset] &= ~OPENPIC_MASK; | |
568 | } | |
569 | ||
570 | static void openpic2_cached_disable_irq(u_int irq) | |
571 | { | |
572 | check_arg_irq(irq); | |
573 | save_irq_src_vp[irq - open_pic2_irq_offset] |= OPENPIC_MASK; | |
574 | } | |
575 | ||
576 | /* WARNING: Can be called directly by the cpufreq code with NULL parameter, | |
577 | * we need something better to deal with that... Maybe switch to S1 for | |
578 | * cpufreq changes | |
579 | */ | |
580 | int openpic2_suspend(struct sys_device *sysdev, u32 state) | |
581 | { | |
582 | int i; | |
583 | unsigned long flags; | |
584 | ||
585 | spin_lock_irqsave(&openpic2_setup_lock, flags); | |
586 | ||
587 | if (openpic_suspend_count++ > 0) { | |
588 | spin_unlock_irqrestore(&openpic2_setup_lock, flags); | |
589 | return 0; | |
590 | } | |
591 | ||
592 | open_pic2.enable = openpic2_cached_enable_irq; | |
593 | open_pic2.disable = openpic2_cached_disable_irq; | |
594 | ||
595 | for (i=0; i<NumProcessors; i++) { | |
596 | save_cpu_task_pri[i] = openpic2_read(&OpenPIC2->Processor[i].Current_Task_Priority); | |
597 | openpic2_writefield(&OpenPIC2->Processor[i].Current_Task_Priority, | |
598 | OPENPIC_CURRENT_TASK_PRIORITY_MASK, 0xf); | |
599 | } | |
600 | ||
601 | for (i=0; i<OPENPIC_NUM_IPI; i++) | |
602 | save_ipi_vp[i] = openpic2_read(&OpenPIC2->Global.IPI_Vector_Priority(i)); | |
603 | for (i=0; i<NumSources; i++) { | |
604 | if (ISR[i] == 0) | |
605 | continue; | |
606 | save_irq_src_vp[i] = openpic2_read(&ISR[i]->Vector_Priority) & ~OPENPIC_ACTIVITY; | |
607 | save_irq_src_dest[i] = openpic2_read(&ISR[i]->Destination); | |
608 | } | |
609 | ||
610 | spin_unlock_irqrestore(&openpic2_setup_lock, flags); | |
611 | ||
612 | return 0; | |
613 | } | |
614 | ||
615 | /* WARNING: Can be called directly by the cpufreq code with NULL parameter, | |
616 | * we need something better to deal with that... Maybe switch to S1 for | |
617 | * cpufreq changes | |
618 | */ | |
619 | int openpic2_resume(struct sys_device *sysdev) | |
620 | { | |
621 | int i; | |
622 | unsigned long flags; | |
623 | u32 vppmask = OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK | | |
624 | OPENPIC_SENSE_MASK | OPENPIC_POLARITY_MASK | | |
625 | OPENPIC_MASK; | |
626 | ||
627 | spin_lock_irqsave(&openpic2_setup_lock, flags); | |
628 | ||
629 | if ((--openpic_suspend_count) > 0) { | |
630 | spin_unlock_irqrestore(&openpic2_setup_lock, flags); | |
631 | return 0; | |
632 | } | |
633 | ||
634 | openpic2_reset(); | |
635 | ||
636 | /* OpenPIC sometimes seem to need some time to be fully back up... */ | |
637 | do { | |
638 | openpic2_set_spurious(OPENPIC2_VEC_SPURIOUS+open_pic2_irq_offset); | |
639 | } while(openpic2_readfield(&OpenPIC2->Global.Spurious_Vector, OPENPIC_VECTOR_MASK) | |
640 | != (OPENPIC2_VEC_SPURIOUS + open_pic2_irq_offset)); | |
641 | ||
642 | openpic2_disable_8259_pass_through(); | |
643 | ||
644 | for (i=0; i<OPENPIC_NUM_IPI; i++) | |
645 | openpic2_write(&OpenPIC2->Global.IPI_Vector_Priority(i), | |
646 | save_ipi_vp[i]); | |
647 | for (i=0; i<NumSources; i++) { | |
648 | if (ISR[i] == 0) | |
649 | continue; | |
650 | openpic2_write(&ISR[i]->Destination, save_irq_src_dest[i]); | |
651 | openpic2_write(&ISR[i]->Vector_Priority, save_irq_src_vp[i]); | |
652 | /* make sure mask gets to controller before we return to user */ | |
653 | do { | |
654 | openpic2_write(&ISR[i]->Vector_Priority, save_irq_src_vp[i]); | |
655 | } while (openpic2_readfield(&ISR[i]->Vector_Priority, vppmask) | |
656 | != (save_irq_src_vp[i] & vppmask)); | |
657 | } | |
658 | for (i=0; i<NumProcessors; i++) | |
659 | openpic2_write(&OpenPIC2->Processor[i].Current_Task_Priority, | |
660 | save_cpu_task_pri[i]); | |
661 | ||
662 | open_pic2.enable = openpic2_enable_irq; | |
663 | open_pic2.disable = openpic2_disable_irq; | |
664 | ||
665 | spin_unlock_irqrestore(&openpic2_setup_lock, flags); | |
666 | ||
667 | return 0; | |
668 | } | |
669 | ||
670 | #endif /* CONFIG_PM */ | |
671 | ||
672 | /* HACK ALERT */ | |
673 | static struct sysdev_class openpic2_sysclass = { | |
674 | set_kset_name("openpic2"), | |
675 | }; | |
676 | ||
677 | static struct sys_device device_openpic2 = { | |
678 | .id = 0, | |
679 | .cls = &openpic2_sysclass, | |
680 | }; | |
681 | ||
682 | static struct sysdev_driver driver_openpic2 = { | |
683 | #ifdef CONFIG_PM | |
684 | .suspend = &openpic2_suspend, | |
685 | .resume = &openpic2_resume, | |
686 | #endif /* CONFIG_PM */ | |
687 | }; | |
688 | ||
689 | static int __init init_openpic2_sysfs(void) | |
690 | { | |
691 | int rc; | |
692 | ||
693 | if (!OpenPIC2_Addr) | |
694 | return -ENODEV; | |
695 | printk(KERN_DEBUG "Registering openpic2 with sysfs...\n"); | |
696 | rc = sysdev_class_register(&openpic2_sysclass); | |
697 | if (rc) { | |
698 | printk(KERN_ERR "Failed registering openpic sys class\n"); | |
699 | return -ENODEV; | |
700 | } | |
701 | rc = sysdev_register(&device_openpic2); | |
702 | if (rc) { | |
703 | printk(KERN_ERR "Failed registering openpic sys device\n"); | |
704 | return -ENODEV; | |
705 | } | |
706 | rc = sysdev_driver_register(&openpic2_sysclass, &driver_openpic2); | |
707 | if (rc) { | |
708 | printk(KERN_ERR "Failed registering openpic sys driver\n"); | |
709 | return -ENODEV; | |
710 | } | |
711 | return 0; | |
712 | } | |
713 | ||
714 | subsys_initcall(init_openpic2_sysfs); | |
715 |