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1da177e4 LT |
1 | /* |
2 | * eeh.c | |
3 | * Copyright (C) 2001 Dave Engebretsen & Todd Inglett IBM Corporation | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/bootmem.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/list.h> | |
23 | #include <linux/mm.h> | |
24 | #include <linux/notifier.h> | |
25 | #include <linux/pci.h> | |
26 | #include <linux/proc_fs.h> | |
27 | #include <linux/rbtree.h> | |
28 | #include <linux/seq_file.h> | |
29 | #include <linux/spinlock.h> | |
30 | #include <asm/eeh.h> | |
31 | #include <asm/io.h> | |
32 | #include <asm/machdep.h> | |
33 | #include <asm/rtas.h> | |
34 | #include <asm/atomic.h> | |
35 | #include <asm/systemcfg.h> | |
36 | #include "pci.h" | |
37 | ||
38 | #undef DEBUG | |
39 | ||
40 | /** Overview: | |
41 | * EEH, or "Extended Error Handling" is a PCI bridge technology for | |
42 | * dealing with PCI bus errors that can't be dealt with within the | |
43 | * usual PCI framework, except by check-stopping the CPU. Systems | |
44 | * that are designed for high-availability/reliability cannot afford | |
45 | * to crash due to a "mere" PCI error, thus the need for EEH. | |
46 | * An EEH-capable bridge operates by converting a detected error | |
47 | * into a "slot freeze", taking the PCI adapter off-line, making | |
48 | * the slot behave, from the OS'es point of view, as if the slot | |
49 | * were "empty": all reads return 0xff's and all writes are silently | |
50 | * ignored. EEH slot isolation events can be triggered by parity | |
51 | * errors on the address or data busses (e.g. during posted writes), | |
52 | * which in turn might be caused by dust, vibration, humidity, | |
53 | * radioactivity or plain-old failed hardware. | |
54 | * | |
55 | * Note, however, that one of the leading causes of EEH slot | |
56 | * freeze events are buggy device drivers, buggy device microcode, | |
57 | * or buggy device hardware. This is because any attempt by the | |
58 | * device to bus-master data to a memory address that is not | |
59 | * assigned to the device will trigger a slot freeze. (The idea | |
60 | * is to prevent devices-gone-wild from corrupting system memory). | |
61 | * Buggy hardware/drivers will have a miserable time co-existing | |
62 | * with EEH. | |
63 | * | |
64 | * Ideally, a PCI device driver, when suspecting that an isolation | |
65 | * event has occured (e.g. by reading 0xff's), will then ask EEH | |
66 | * whether this is the case, and then take appropriate steps to | |
67 | * reset the PCI slot, the PCI device, and then resume operations. | |
68 | * However, until that day, the checking is done here, with the | |
69 | * eeh_check_failure() routine embedded in the MMIO macros. If | |
70 | * the slot is found to be isolated, an "EEH Event" is synthesized | |
71 | * and sent out for processing. | |
72 | */ | |
73 | ||
74 | /** Bus Unit ID macros; get low and hi 32-bits of the 64-bit BUID */ | |
75 | #define BUID_HI(buid) ((buid) >> 32) | |
76 | #define BUID_LO(buid) ((buid) & 0xffffffff) | |
77 | ||
78 | /* EEH event workqueue setup. */ | |
79 | static DEFINE_SPINLOCK(eeh_eventlist_lock); | |
80 | LIST_HEAD(eeh_eventlist); | |
81 | static void eeh_event_handler(void *); | |
82 | DECLARE_WORK(eeh_event_wq, eeh_event_handler, NULL); | |
83 | ||
84 | static struct notifier_block *eeh_notifier_chain; | |
85 | ||
86 | /* | |
87 | * If a device driver keeps reading an MMIO register in an interrupt | |
88 | * handler after a slot isolation event has occurred, we assume it | |
89 | * is broken and panic. This sets the threshold for how many read | |
90 | * attempts we allow before panicking. | |
91 | */ | |
92 | #define EEH_MAX_FAILS 1000 | |
93 | static atomic_t eeh_fail_count; | |
94 | ||
95 | /* RTAS tokens */ | |
96 | static int ibm_set_eeh_option; | |
97 | static int ibm_set_slot_reset; | |
98 | static int ibm_read_slot_reset_state; | |
99 | static int ibm_read_slot_reset_state2; | |
100 | static int ibm_slot_error_detail; | |
101 | ||
102 | static int eeh_subsystem_enabled; | |
103 | ||
104 | /* Buffer for reporting slot-error-detail rtas calls */ | |
105 | static unsigned char slot_errbuf[RTAS_ERROR_LOG_MAX]; | |
106 | static DEFINE_SPINLOCK(slot_errbuf_lock); | |
107 | static int eeh_error_buf_size; | |
108 | ||
109 | /* System monitoring statistics */ | |
110 | static DEFINE_PER_CPU(unsigned long, total_mmio_ffs); | |
111 | static DEFINE_PER_CPU(unsigned long, false_positives); | |
112 | static DEFINE_PER_CPU(unsigned long, ignored_failures); | |
113 | static DEFINE_PER_CPU(unsigned long, slot_resets); | |
114 | ||
115 | /** | |
116 | * The pci address cache subsystem. This subsystem places | |
117 | * PCI device address resources into a red-black tree, sorted | |
118 | * according to the address range, so that given only an i/o | |
119 | * address, the corresponding PCI device can be **quickly** | |
120 | * found. It is safe to perform an address lookup in an interrupt | |
121 | * context; this ability is an important feature. | |
122 | * | |
123 | * Currently, the only customer of this code is the EEH subsystem; | |
124 | * thus, this code has been somewhat tailored to suit EEH better. | |
125 | * In particular, the cache does *not* hold the addresses of devices | |
126 | * for which EEH is not enabled. | |
127 | * | |
128 | * (Implementation Note: The RB tree seems to be better/faster | |
129 | * than any hash algo I could think of for this problem, even | |
130 | * with the penalty of slow pointer chases for d-cache misses). | |
131 | */ | |
132 | struct pci_io_addr_range | |
133 | { | |
134 | struct rb_node rb_node; | |
135 | unsigned long addr_lo; | |
136 | unsigned long addr_hi; | |
137 | struct pci_dev *pcidev; | |
138 | unsigned int flags; | |
139 | }; | |
140 | ||
141 | static struct pci_io_addr_cache | |
142 | { | |
143 | struct rb_root rb_root; | |
144 | spinlock_t piar_lock; | |
145 | } pci_io_addr_cache_root; | |
146 | ||
147 | static inline struct pci_dev *__pci_get_device_by_addr(unsigned long addr) | |
148 | { | |
149 | struct rb_node *n = pci_io_addr_cache_root.rb_root.rb_node; | |
150 | ||
151 | while (n) { | |
152 | struct pci_io_addr_range *piar; | |
153 | piar = rb_entry(n, struct pci_io_addr_range, rb_node); | |
154 | ||
155 | if (addr < piar->addr_lo) { | |
156 | n = n->rb_left; | |
157 | } else { | |
158 | if (addr > piar->addr_hi) { | |
159 | n = n->rb_right; | |
160 | } else { | |
161 | pci_dev_get(piar->pcidev); | |
162 | return piar->pcidev; | |
163 | } | |
164 | } | |
165 | } | |
166 | ||
167 | return NULL; | |
168 | } | |
169 | ||
170 | /** | |
171 | * pci_get_device_by_addr - Get device, given only address | |
172 | * @addr: mmio (PIO) phys address or i/o port number | |
173 | * | |
174 | * Given an mmio phys address, or a port number, find a pci device | |
175 | * that implements this address. Be sure to pci_dev_put the device | |
176 | * when finished. I/O port numbers are assumed to be offset | |
177 | * from zero (that is, they do *not* have pci_io_addr added in). | |
178 | * It is safe to call this function within an interrupt. | |
179 | */ | |
180 | static struct pci_dev *pci_get_device_by_addr(unsigned long addr) | |
181 | { | |
182 | struct pci_dev *dev; | |
183 | unsigned long flags; | |
184 | ||
185 | spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags); | |
186 | dev = __pci_get_device_by_addr(addr); | |
187 | spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags); | |
188 | return dev; | |
189 | } | |
190 | ||
191 | #ifdef DEBUG | |
192 | /* | |
193 | * Handy-dandy debug print routine, does nothing more | |
194 | * than print out the contents of our addr cache. | |
195 | */ | |
196 | static void pci_addr_cache_print(struct pci_io_addr_cache *cache) | |
197 | { | |
198 | struct rb_node *n; | |
199 | int cnt = 0; | |
200 | ||
201 | n = rb_first(&cache->rb_root); | |
202 | while (n) { | |
203 | struct pci_io_addr_range *piar; | |
204 | piar = rb_entry(n, struct pci_io_addr_range, rb_node); | |
982245f0 | 205 | printk(KERN_DEBUG "PCI: %s addr range %d [%lx-%lx]: %s\n", |
1da177e4 | 206 | (piar->flags & IORESOURCE_IO) ? "i/o" : "mem", cnt, |
982245f0 | 207 | piar->addr_lo, piar->addr_hi, pci_name(piar->pcidev)); |
1da177e4 LT |
208 | cnt++; |
209 | n = rb_next(n); | |
210 | } | |
211 | } | |
212 | #endif | |
213 | ||
214 | /* Insert address range into the rb tree. */ | |
215 | static struct pci_io_addr_range * | |
216 | pci_addr_cache_insert(struct pci_dev *dev, unsigned long alo, | |
217 | unsigned long ahi, unsigned int flags) | |
218 | { | |
219 | struct rb_node **p = &pci_io_addr_cache_root.rb_root.rb_node; | |
220 | struct rb_node *parent = NULL; | |
221 | struct pci_io_addr_range *piar; | |
222 | ||
223 | /* Walk tree, find a place to insert into tree */ | |
224 | while (*p) { | |
225 | parent = *p; | |
226 | piar = rb_entry(parent, struct pci_io_addr_range, rb_node); | |
227 | if (alo < piar->addr_lo) { | |
228 | p = &parent->rb_left; | |
229 | } else if (ahi > piar->addr_hi) { | |
230 | p = &parent->rb_right; | |
231 | } else { | |
232 | if (dev != piar->pcidev || | |
233 | alo != piar->addr_lo || ahi != piar->addr_hi) { | |
234 | printk(KERN_WARNING "PIAR: overlapping address range\n"); | |
235 | } | |
236 | return piar; | |
237 | } | |
238 | } | |
239 | piar = (struct pci_io_addr_range *)kmalloc(sizeof(struct pci_io_addr_range), GFP_ATOMIC); | |
240 | if (!piar) | |
241 | return NULL; | |
242 | ||
243 | piar->addr_lo = alo; | |
244 | piar->addr_hi = ahi; | |
245 | piar->pcidev = dev; | |
246 | piar->flags = flags; | |
247 | ||
248 | rb_link_node(&piar->rb_node, parent, p); | |
249 | rb_insert_color(&piar->rb_node, &pci_io_addr_cache_root.rb_root); | |
250 | ||
251 | return piar; | |
252 | } | |
253 | ||
254 | static void __pci_addr_cache_insert_device(struct pci_dev *dev) | |
255 | { | |
256 | struct device_node *dn; | |
1635317f | 257 | struct pci_dn *pdn; |
1da177e4 LT |
258 | int i; |
259 | int inserted = 0; | |
260 | ||
261 | dn = pci_device_to_OF_node(dev); | |
262 | if (!dn) { | |
982245f0 AB |
263 | printk(KERN_WARNING "PCI: no pci dn found for dev=%s\n", |
264 | pci_name(dev)); | |
1da177e4 LT |
265 | return; |
266 | } | |
267 | ||
268 | /* Skip any devices for which EEH is not enabled. */ | |
1635317f PM |
269 | pdn = dn->data; |
270 | if (!(pdn->eeh_mode & EEH_MODE_SUPPORTED) || | |
271 | pdn->eeh_mode & EEH_MODE_NOCHECK) { | |
1da177e4 | 272 | #ifdef DEBUG |
982245f0 AB |
273 | printk(KERN_INFO "PCI: skip building address cache for=%s\n", |
274 | pci_name(dev)); | |
1da177e4 LT |
275 | #endif |
276 | return; | |
277 | } | |
278 | ||
279 | /* The cache holds a reference to the device... */ | |
280 | pci_dev_get(dev); | |
281 | ||
282 | /* Walk resources on this device, poke them into the tree */ | |
283 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
284 | unsigned long start = pci_resource_start(dev,i); | |
285 | unsigned long end = pci_resource_end(dev,i); | |
286 | unsigned int flags = pci_resource_flags(dev,i); | |
287 | ||
288 | /* We are interested only bus addresses, not dma or other stuff */ | |
289 | if (0 == (flags & (IORESOURCE_IO | IORESOURCE_MEM))) | |
290 | continue; | |
291 | if (start == 0 || ~start == 0 || end == 0 || ~end == 0) | |
292 | continue; | |
293 | pci_addr_cache_insert(dev, start, end, flags); | |
294 | inserted = 1; | |
295 | } | |
296 | ||
297 | /* If there was nothing to add, the cache has no reference... */ | |
298 | if (!inserted) | |
299 | pci_dev_put(dev); | |
300 | } | |
301 | ||
302 | /** | |
303 | * pci_addr_cache_insert_device - Add a device to the address cache | |
304 | * @dev: PCI device whose I/O addresses we are interested in. | |
305 | * | |
306 | * In order to support the fast lookup of devices based on addresses, | |
307 | * we maintain a cache of devices that can be quickly searched. | |
308 | * This routine adds a device to that cache. | |
309 | */ | |
310 | void pci_addr_cache_insert_device(struct pci_dev *dev) | |
311 | { | |
312 | unsigned long flags; | |
313 | ||
314 | spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags); | |
315 | __pci_addr_cache_insert_device(dev); | |
316 | spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags); | |
317 | } | |
318 | ||
319 | static inline void __pci_addr_cache_remove_device(struct pci_dev *dev) | |
320 | { | |
321 | struct rb_node *n; | |
322 | int removed = 0; | |
323 | ||
324 | restart: | |
325 | n = rb_first(&pci_io_addr_cache_root.rb_root); | |
326 | while (n) { | |
327 | struct pci_io_addr_range *piar; | |
328 | piar = rb_entry(n, struct pci_io_addr_range, rb_node); | |
329 | ||
330 | if (piar->pcidev == dev) { | |
331 | rb_erase(n, &pci_io_addr_cache_root.rb_root); | |
332 | removed = 1; | |
333 | kfree(piar); | |
334 | goto restart; | |
335 | } | |
336 | n = rb_next(n); | |
337 | } | |
338 | ||
339 | /* The cache no longer holds its reference to this device... */ | |
340 | if (removed) | |
341 | pci_dev_put(dev); | |
342 | } | |
343 | ||
344 | /** | |
345 | * pci_addr_cache_remove_device - remove pci device from addr cache | |
346 | * @dev: device to remove | |
347 | * | |
348 | * Remove a device from the addr-cache tree. | |
349 | * This is potentially expensive, since it will walk | |
350 | * the tree multiple times (once per resource). | |
351 | * But so what; device removal doesn't need to be that fast. | |
352 | */ | |
353 | void pci_addr_cache_remove_device(struct pci_dev *dev) | |
354 | { | |
355 | unsigned long flags; | |
356 | ||
357 | spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags); | |
358 | __pci_addr_cache_remove_device(dev); | |
359 | spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags); | |
360 | } | |
361 | ||
362 | /** | |
363 | * pci_addr_cache_build - Build a cache of I/O addresses | |
364 | * | |
365 | * Build a cache of pci i/o addresses. This cache will be used to | |
366 | * find the pci device that corresponds to a given address. | |
367 | * This routine scans all pci busses to build the cache. | |
368 | * Must be run late in boot process, after the pci controllers | |
369 | * have been scaned for devices (after all device resources are known). | |
370 | */ | |
371 | void __init pci_addr_cache_build(void) | |
372 | { | |
373 | struct pci_dev *dev = NULL; | |
374 | ||
375 | spin_lock_init(&pci_io_addr_cache_root.piar_lock); | |
376 | ||
377 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
378 | /* Ignore PCI bridges ( XXX why ??) */ | |
379 | if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE) { | |
380 | continue; | |
381 | } | |
382 | pci_addr_cache_insert_device(dev); | |
383 | } | |
384 | ||
385 | #ifdef DEBUG | |
386 | /* Verify tree built up above, echo back the list of addrs. */ | |
387 | pci_addr_cache_print(&pci_io_addr_cache_root); | |
388 | #endif | |
389 | } | |
390 | ||
391 | /* --------------------------------------------------------------- */ | |
392 | /* Above lies the PCI Address Cache. Below lies the EEH event infrastructure */ | |
393 | ||
394 | /** | |
395 | * eeh_register_notifier - Register to find out about EEH events. | |
396 | * @nb: notifier block to callback on events | |
397 | */ | |
398 | int eeh_register_notifier(struct notifier_block *nb) | |
399 | { | |
400 | return notifier_chain_register(&eeh_notifier_chain, nb); | |
401 | } | |
402 | ||
403 | /** | |
404 | * eeh_unregister_notifier - Unregister to an EEH event notifier. | |
405 | * @nb: notifier block to callback on events | |
406 | */ | |
407 | int eeh_unregister_notifier(struct notifier_block *nb) | |
408 | { | |
409 | return notifier_chain_unregister(&eeh_notifier_chain, nb); | |
410 | } | |
411 | ||
412 | /** | |
413 | * read_slot_reset_state - Read the reset state of a device node's slot | |
414 | * @dn: device node to read | |
415 | * @rets: array to return results in | |
416 | */ | |
417 | static int read_slot_reset_state(struct device_node *dn, int rets[]) | |
418 | { | |
419 | int token, outputs; | |
1635317f | 420 | struct pci_dn *pdn = dn->data; |
1da177e4 LT |
421 | |
422 | if (ibm_read_slot_reset_state2 != RTAS_UNKNOWN_SERVICE) { | |
423 | token = ibm_read_slot_reset_state2; | |
424 | outputs = 4; | |
425 | } else { | |
426 | token = ibm_read_slot_reset_state; | |
427 | outputs = 3; | |
428 | } | |
429 | ||
1635317f PM |
430 | return rtas_call(token, 3, outputs, rets, pdn->eeh_config_addr, |
431 | BUID_HI(pdn->phb->buid), BUID_LO(pdn->phb->buid)); | |
1da177e4 LT |
432 | } |
433 | ||
434 | /** | |
435 | * eeh_panic - call panic() for an eeh event that cannot be handled. | |
436 | * The philosophy of this routine is that it is better to panic and | |
437 | * halt the OS than it is to risk possible data corruption by | |
438 | * oblivious device drivers that don't know better. | |
439 | * | |
440 | * @dev pci device that had an eeh event | |
441 | * @reset_state current reset state of the device slot | |
442 | */ | |
443 | static void eeh_panic(struct pci_dev *dev, int reset_state) | |
444 | { | |
445 | /* | |
446 | * XXX We should create a separate sysctl for this. | |
447 | * | |
448 | * Since the panic_on_oops sysctl is used to halt the system | |
449 | * in light of potential corruption, we can use it here. | |
450 | */ | |
451 | if (panic_on_oops) | |
982245f0 AB |
452 | panic("EEH: MMIO failure (%d) on device:%s\n", reset_state, |
453 | pci_name(dev)); | |
1da177e4 LT |
454 | else { |
455 | __get_cpu_var(ignored_failures)++; | |
982245f0 AB |
456 | printk(KERN_INFO "EEH: Ignored MMIO failure (%d) on device:%s\n", |
457 | reset_state, pci_name(dev)); | |
1da177e4 LT |
458 | } |
459 | } | |
460 | ||
461 | /** | |
462 | * eeh_event_handler - dispatch EEH events. The detection of a frozen | |
463 | * slot can occur inside an interrupt, where it can be hard to do | |
464 | * anything about it. The goal of this routine is to pull these | |
465 | * detection events out of the context of the interrupt handler, and | |
466 | * re-dispatch them for processing at a later time in a normal context. | |
467 | * | |
468 | * @dummy - unused | |
469 | */ | |
470 | static void eeh_event_handler(void *dummy) | |
471 | { | |
472 | unsigned long flags; | |
473 | struct eeh_event *event; | |
474 | ||
475 | while (1) { | |
476 | spin_lock_irqsave(&eeh_eventlist_lock, flags); | |
477 | event = NULL; | |
478 | if (!list_empty(&eeh_eventlist)) { | |
479 | event = list_entry(eeh_eventlist.next, struct eeh_event, list); | |
480 | list_del(&event->list); | |
481 | } | |
482 | spin_unlock_irqrestore(&eeh_eventlist_lock, flags); | |
483 | if (event == NULL) | |
484 | break; | |
485 | ||
486 | printk(KERN_INFO "EEH: MMIO failure (%d), notifiying device " | |
982245f0 AB |
487 | "%s\n", event->reset_state, |
488 | pci_name(event->dev)); | |
1da177e4 LT |
489 | |
490 | atomic_set(&eeh_fail_count, 0); | |
491 | notifier_call_chain (&eeh_notifier_chain, | |
492 | EEH_NOTIFY_FREEZE, event); | |
493 | ||
494 | __get_cpu_var(slot_resets)++; | |
495 | ||
496 | pci_dev_put(event->dev); | |
497 | kfree(event); | |
498 | } | |
499 | } | |
500 | ||
501 | /** | |
502 | * eeh_token_to_phys - convert EEH address token to phys address | |
503 | * @token i/o token, should be address in the form 0xE.... | |
504 | */ | |
505 | static inline unsigned long eeh_token_to_phys(unsigned long token) | |
506 | { | |
507 | pte_t *ptep; | |
508 | unsigned long pa; | |
509 | ||
20cee16c | 510 | ptep = find_linux_pte(init_mm.pgd, token); |
1da177e4 LT |
511 | if (!ptep) |
512 | return token; | |
513 | pa = pte_pfn(*ptep) << PAGE_SHIFT; | |
514 | ||
515 | return pa | (token & (PAGE_SIZE-1)); | |
516 | } | |
517 | ||
518 | /** | |
519 | * eeh_dn_check_failure - check if all 1's data is due to EEH slot freeze | |
520 | * @dn device node | |
521 | * @dev pci device, if known | |
522 | * | |
523 | * Check for an EEH failure for the given device node. Call this | |
524 | * routine if the result of a read was all 0xff's and you want to | |
525 | * find out if this is due to an EEH slot freeze. This routine | |
526 | * will query firmware for the EEH status. | |
527 | * | |
528 | * Returns 0 if there has not been an EEH error; otherwise returns | |
529 | * a non-zero value and queues up a solt isolation event notification. | |
530 | * | |
531 | * It is safe to call this routine in an interrupt context. | |
532 | */ | |
533 | int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev) | |
534 | { | |
535 | int ret; | |
536 | int rets[3]; | |
537 | unsigned long flags; | |
538 | int rc, reset_state; | |
539 | struct eeh_event *event; | |
1635317f | 540 | struct pci_dn *pdn; |
1da177e4 LT |
541 | |
542 | __get_cpu_var(total_mmio_ffs)++; | |
543 | ||
544 | if (!eeh_subsystem_enabled) | |
545 | return 0; | |
546 | ||
547 | if (!dn) | |
548 | return 0; | |
1635317f | 549 | pdn = dn->data; |
1da177e4 LT |
550 | |
551 | /* Access to IO BARs might get this far and still not want checking. */ | |
1635317f PM |
552 | if (!pdn->eeh_capable || !(pdn->eeh_mode & EEH_MODE_SUPPORTED) || |
553 | pdn->eeh_mode & EEH_MODE_NOCHECK) { | |
1da177e4 LT |
554 | return 0; |
555 | } | |
556 | ||
1635317f | 557 | if (!pdn->eeh_config_addr) { |
1da177e4 LT |
558 | return 0; |
559 | } | |
560 | ||
561 | /* | |
562 | * If we already have a pending isolation event for this | |
563 | * slot, we know it's bad already, we don't need to check... | |
564 | */ | |
1635317f | 565 | if (pdn->eeh_mode & EEH_MODE_ISOLATED) { |
1da177e4 LT |
566 | atomic_inc(&eeh_fail_count); |
567 | if (atomic_read(&eeh_fail_count) >= EEH_MAX_FAILS) { | |
568 | /* re-read the slot reset state */ | |
569 | if (read_slot_reset_state(dn, rets) != 0) | |
570 | rets[0] = -1; /* reset state unknown */ | |
571 | eeh_panic(dev, rets[0]); | |
572 | } | |
573 | return 0; | |
574 | } | |
575 | ||
576 | /* | |
577 | * Now test for an EEH failure. This is VERY expensive. | |
578 | * Note that the eeh_config_addr may be a parent device | |
579 | * in the case of a device behind a bridge, or it may be | |
580 | * function zero of a multi-function device. | |
581 | * In any case they must share a common PHB. | |
582 | */ | |
583 | ret = read_slot_reset_state(dn, rets); | |
584 | if (!(ret == 0 && rets[1] == 1 && (rets[0] == 2 || rets[0] == 4))) { | |
585 | __get_cpu_var(false_positives)++; | |
586 | return 0; | |
587 | } | |
588 | ||
589 | /* prevent repeated reports of this failure */ | |
1635317f | 590 | pdn->eeh_mode |= EEH_MODE_ISOLATED; |
1da177e4 LT |
591 | |
592 | reset_state = rets[0]; | |
593 | ||
594 | spin_lock_irqsave(&slot_errbuf_lock, flags); | |
595 | memset(slot_errbuf, 0, eeh_error_buf_size); | |
596 | ||
597 | rc = rtas_call(ibm_slot_error_detail, | |
1635317f PM |
598 | 8, 1, NULL, pdn->eeh_config_addr, |
599 | BUID_HI(pdn->phb->buid), | |
600 | BUID_LO(pdn->phb->buid), NULL, 0, | |
1da177e4 LT |
601 | virt_to_phys(slot_errbuf), |
602 | eeh_error_buf_size, | |
603 | 1 /* Temporary Error */); | |
604 | ||
605 | if (rc == 0) | |
606 | log_error(slot_errbuf, ERR_TYPE_RTAS_LOG, 0); | |
607 | spin_unlock_irqrestore(&slot_errbuf_lock, flags); | |
608 | ||
609 | printk(KERN_INFO "EEH: MMIO failure (%d) on device: %s %s\n", | |
610 | rets[0], dn->name, dn->full_name); | |
611 | event = kmalloc(sizeof(*event), GFP_ATOMIC); | |
612 | if (event == NULL) { | |
613 | eeh_panic(dev, reset_state); | |
614 | return 1; | |
615 | } | |
616 | ||
617 | event->dev = dev; | |
618 | event->dn = dn; | |
619 | event->reset_state = reset_state; | |
620 | ||
621 | /* We may or may not be called in an interrupt context */ | |
622 | spin_lock_irqsave(&eeh_eventlist_lock, flags); | |
623 | list_add(&event->list, &eeh_eventlist); | |
624 | spin_unlock_irqrestore(&eeh_eventlist_lock, flags); | |
625 | ||
626 | /* Most EEH events are due to device driver bugs. Having | |
627 | * a stack trace will help the device-driver authors figure | |
628 | * out what happened. So print that out. */ | |
629 | dump_stack(); | |
630 | schedule_work(&eeh_event_wq); | |
631 | ||
632 | return 0; | |
633 | } | |
634 | ||
635 | EXPORT_SYMBOL(eeh_dn_check_failure); | |
636 | ||
637 | /** | |
638 | * eeh_check_failure - check if all 1's data is due to EEH slot freeze | |
639 | * @token i/o token, should be address in the form 0xA.... | |
640 | * @val value, should be all 1's (XXX why do we need this arg??) | |
641 | * | |
642 | * Check for an eeh failure at the given token address. | |
643 | * Check for an EEH failure at the given token address. Call this | |
644 | * routine if the result of a read was all 0xff's and you want to | |
645 | * find out if this is due to an EEH slot freeze event. This routine | |
646 | * will query firmware for the EEH status. | |
647 | * | |
648 | * Note this routine is safe to call in an interrupt context. | |
649 | */ | |
650 | unsigned long eeh_check_failure(const volatile void __iomem *token, unsigned long val) | |
651 | { | |
652 | unsigned long addr; | |
653 | struct pci_dev *dev; | |
654 | struct device_node *dn; | |
655 | ||
656 | /* Finding the phys addr + pci device; this is pretty quick. */ | |
657 | addr = eeh_token_to_phys((unsigned long __force) token); | |
658 | dev = pci_get_device_by_addr(addr); | |
659 | if (!dev) | |
660 | return val; | |
661 | ||
662 | dn = pci_device_to_OF_node(dev); | |
663 | eeh_dn_check_failure (dn, dev); | |
664 | ||
665 | pci_dev_put(dev); | |
666 | return val; | |
667 | } | |
668 | ||
669 | EXPORT_SYMBOL(eeh_check_failure); | |
670 | ||
671 | struct eeh_early_enable_info { | |
672 | unsigned int buid_hi; | |
673 | unsigned int buid_lo; | |
674 | }; | |
675 | ||
676 | /* Enable eeh for the given device node. */ | |
677 | static void *early_enable_eeh(struct device_node *dn, void *data) | |
678 | { | |
679 | struct eeh_early_enable_info *info = data; | |
680 | int ret; | |
681 | char *status = get_property(dn, "status", NULL); | |
682 | u32 *class_code = (u32 *)get_property(dn, "class-code", NULL); | |
683 | u32 *vendor_id = (u32 *)get_property(dn, "vendor-id", NULL); | |
684 | u32 *device_id = (u32 *)get_property(dn, "device-id", NULL); | |
685 | u32 *regs; | |
686 | int enable; | |
1635317f | 687 | struct pci_dn *pdn = dn->data; |
1da177e4 | 688 | |
1635317f | 689 | pdn->eeh_mode = 0; |
1da177e4 LT |
690 | |
691 | if (status && strcmp(status, "ok") != 0) | |
692 | return NULL; /* ignore devices with bad status */ | |
693 | ||
694 | /* Ignore bad nodes. */ | |
695 | if (!class_code || !vendor_id || !device_id) | |
696 | return NULL; | |
697 | ||
698 | /* There is nothing to check on PCI to ISA bridges */ | |
699 | if (dn->type && !strcmp(dn->type, "isa")) { | |
1635317f | 700 | pdn->eeh_mode |= EEH_MODE_NOCHECK; |
1da177e4 LT |
701 | return NULL; |
702 | } | |
703 | ||
704 | /* | |
705 | * Now decide if we are going to "Disable" EEH checking | |
706 | * for this device. We still run with the EEH hardware active, | |
707 | * but we won't be checking for ff's. This means a driver | |
708 | * could return bad data (very bad!), an interrupt handler could | |
709 | * hang waiting on status bits that won't change, etc. | |
710 | * But there are a few cases like display devices that make sense. | |
711 | */ | |
712 | enable = 1; /* i.e. we will do checking */ | |
713 | if ((*class_code >> 16) == PCI_BASE_CLASS_DISPLAY) | |
714 | enable = 0; | |
715 | ||
716 | if (!enable) | |
1635317f | 717 | pdn->eeh_mode |= EEH_MODE_NOCHECK; |
1da177e4 LT |
718 | |
719 | /* Ok... see if this device supports EEH. Some do, some don't, | |
720 | * and the only way to find out is to check each and every one. */ | |
721 | regs = (u32 *)get_property(dn, "reg", NULL); | |
722 | if (regs) { | |
723 | /* First register entry is addr (00BBSS00) */ | |
724 | /* Try to enable eeh */ | |
725 | ret = rtas_call(ibm_set_eeh_option, 4, 1, NULL, | |
726 | regs[0], info->buid_hi, info->buid_lo, | |
727 | EEH_ENABLE); | |
728 | if (ret == 0) { | |
729 | eeh_subsystem_enabled = 1; | |
1635317f PM |
730 | pdn->eeh_mode |= EEH_MODE_SUPPORTED; |
731 | pdn->eeh_config_addr = regs[0]; | |
1da177e4 LT |
732 | #ifdef DEBUG |
733 | printk(KERN_DEBUG "EEH: %s: eeh enabled\n", dn->full_name); | |
734 | #endif | |
735 | } else { | |
736 | ||
737 | /* This device doesn't support EEH, but it may have an | |
738 | * EEH parent, in which case we mark it as supported. */ | |
1635317f PM |
739 | if (dn->parent && dn->parent->data |
740 | && (PCI_DN(dn->parent)->eeh_mode & EEH_MODE_SUPPORTED)) { | |
1da177e4 | 741 | /* Parent supports EEH. */ |
1635317f PM |
742 | pdn->eeh_mode |= EEH_MODE_SUPPORTED; |
743 | pdn->eeh_config_addr = PCI_DN(dn->parent)->eeh_config_addr; | |
1da177e4 LT |
744 | return NULL; |
745 | } | |
746 | } | |
747 | } else { | |
748 | printk(KERN_WARNING "EEH: %s: unable to get reg property.\n", | |
749 | dn->full_name); | |
750 | } | |
751 | ||
752 | return NULL; | |
753 | } | |
754 | ||
755 | /* | |
756 | * Initialize EEH by trying to enable it for all of the adapters in the system. | |
757 | * As a side effect we can determine here if eeh is supported at all. | |
758 | * Note that we leave EEH on so failed config cycles won't cause a machine | |
759 | * check. If a user turns off EEH for a particular adapter they are really | |
760 | * telling Linux to ignore errors. Some hardware (e.g. POWER5) won't | |
761 | * grant access to a slot if EEH isn't enabled, and so we always enable | |
762 | * EEH for all slots/all devices. | |
763 | * | |
764 | * The eeh-force-off option disables EEH checking globally, for all slots. | |
765 | * Even if force-off is set, the EEH hardware is still enabled, so that | |
766 | * newer systems can boot. | |
767 | */ | |
768 | void __init eeh_init(void) | |
769 | { | |
770 | struct device_node *phb, *np; | |
771 | struct eeh_early_enable_info info; | |
772 | ||
773 | np = of_find_node_by_path("/rtas"); | |
774 | if (np == NULL) | |
775 | return; | |
776 | ||
777 | ibm_set_eeh_option = rtas_token("ibm,set-eeh-option"); | |
778 | ibm_set_slot_reset = rtas_token("ibm,set-slot-reset"); | |
779 | ibm_read_slot_reset_state2 = rtas_token("ibm,read-slot-reset-state2"); | |
780 | ibm_read_slot_reset_state = rtas_token("ibm,read-slot-reset-state"); | |
781 | ibm_slot_error_detail = rtas_token("ibm,slot-error-detail"); | |
782 | ||
783 | if (ibm_set_eeh_option == RTAS_UNKNOWN_SERVICE) | |
784 | return; | |
785 | ||
786 | eeh_error_buf_size = rtas_token("rtas-error-log-max"); | |
787 | if (eeh_error_buf_size == RTAS_UNKNOWN_SERVICE) { | |
788 | eeh_error_buf_size = 1024; | |
789 | } | |
790 | if (eeh_error_buf_size > RTAS_ERROR_LOG_MAX) { | |
791 | printk(KERN_WARNING "EEH: rtas-error-log-max is bigger than allocated " | |
792 | "buffer ! (%d vs %d)", eeh_error_buf_size, RTAS_ERROR_LOG_MAX); | |
793 | eeh_error_buf_size = RTAS_ERROR_LOG_MAX; | |
794 | } | |
795 | ||
796 | /* Enable EEH for all adapters. Note that eeh requires buid's */ | |
797 | for (phb = of_find_node_by_name(NULL, "pci"); phb; | |
798 | phb = of_find_node_by_name(phb, "pci")) { | |
799 | unsigned long buid; | |
1635317f | 800 | struct pci_dn *pci; |
1da177e4 LT |
801 | |
802 | buid = get_phb_buid(phb); | |
1635317f | 803 | if (buid == 0 || phb->data == NULL) |
1da177e4 LT |
804 | continue; |
805 | ||
1635317f | 806 | pci = phb->data; |
1da177e4 LT |
807 | info.buid_lo = BUID_LO(buid); |
808 | info.buid_hi = BUID_HI(buid); | |
809 | traverse_pci_devices(phb, early_enable_eeh, &info); | |
810 | } | |
811 | ||
812 | if (eeh_subsystem_enabled) | |
813 | printk(KERN_INFO "EEH: PCI Enhanced I/O Error Handling Enabled\n"); | |
814 | else | |
815 | printk(KERN_WARNING "EEH: No capable adapters found\n"); | |
816 | } | |
817 | ||
818 | /** | |
819 | * eeh_add_device_early - enable EEH for the indicated device_node | |
820 | * @dn: device node for which to set up EEH | |
821 | * | |
822 | * This routine must be used to perform EEH initialization for PCI | |
823 | * devices that were added after system boot (e.g. hotplug, dlpar). | |
824 | * This routine must be called before any i/o is performed to the | |
825 | * adapter (inluding any config-space i/o). | |
826 | * Whether this actually enables EEH or not for this device depends | |
827 | * on the CEC architecture, type of the device, on earlier boot | |
828 | * command-line arguments & etc. | |
829 | */ | |
830 | void eeh_add_device_early(struct device_node *dn) | |
831 | { | |
832 | struct pci_controller *phb; | |
833 | struct eeh_early_enable_info info; | |
834 | ||
1635317f | 835 | if (!dn || !dn->data) |
1da177e4 | 836 | return; |
1635317f | 837 | phb = PCI_DN(dn)->phb; |
1da177e4 LT |
838 | if (NULL == phb || 0 == phb->buid) { |
839 | printk(KERN_WARNING "EEH: Expected buid but found none\n"); | |
840 | return; | |
841 | } | |
842 | ||
843 | info.buid_hi = BUID_HI(phb->buid); | |
844 | info.buid_lo = BUID_LO(phb->buid); | |
845 | early_enable_eeh(dn, &info); | |
846 | } | |
847 | EXPORT_SYMBOL(eeh_add_device_early); | |
848 | ||
849 | /** | |
850 | * eeh_add_device_late - perform EEH initialization for the indicated pci device | |
851 | * @dev: pci device for which to set up EEH | |
852 | * | |
853 | * This routine must be used to complete EEH initialization for PCI | |
854 | * devices that were added after system boot (e.g. hotplug, dlpar). | |
855 | */ | |
856 | void eeh_add_device_late(struct pci_dev *dev) | |
857 | { | |
858 | if (!dev || !eeh_subsystem_enabled) | |
859 | return; | |
860 | ||
861 | #ifdef DEBUG | |
982245f0 | 862 | printk(KERN_DEBUG "EEH: adding device %s\n", pci_name(dev)); |
1da177e4 LT |
863 | #endif |
864 | ||
865 | pci_addr_cache_insert_device (dev); | |
866 | } | |
867 | EXPORT_SYMBOL(eeh_add_device_late); | |
868 | ||
869 | /** | |
870 | * eeh_remove_device - undo EEH setup for the indicated pci device | |
871 | * @dev: pci device to be removed | |
872 | * | |
873 | * This routine should be when a device is removed from a running | |
874 | * system (e.g. by hotplug or dlpar). | |
875 | */ | |
876 | void eeh_remove_device(struct pci_dev *dev) | |
877 | { | |
878 | if (!dev || !eeh_subsystem_enabled) | |
879 | return; | |
880 | ||
881 | /* Unregister the device with the EEH/PCI address search system */ | |
882 | #ifdef DEBUG | |
982245f0 | 883 | printk(KERN_DEBUG "EEH: remove device %s\n", pci_name(dev)); |
1da177e4 LT |
884 | #endif |
885 | pci_addr_cache_remove_device(dev); | |
886 | } | |
887 | EXPORT_SYMBOL(eeh_remove_device); | |
888 | ||
889 | static int proc_eeh_show(struct seq_file *m, void *v) | |
890 | { | |
891 | unsigned int cpu; | |
892 | unsigned long ffs = 0, positives = 0, failures = 0; | |
893 | unsigned long resets = 0; | |
894 | ||
895 | for_each_cpu(cpu) { | |
896 | ffs += per_cpu(total_mmio_ffs, cpu); | |
897 | positives += per_cpu(false_positives, cpu); | |
898 | failures += per_cpu(ignored_failures, cpu); | |
899 | resets += per_cpu(slot_resets, cpu); | |
900 | } | |
901 | ||
902 | if (0 == eeh_subsystem_enabled) { | |
903 | seq_printf(m, "EEH Subsystem is globally disabled\n"); | |
904 | seq_printf(m, "eeh_total_mmio_ffs=%ld\n", ffs); | |
905 | } else { | |
906 | seq_printf(m, "EEH Subsystem is enabled\n"); | |
907 | seq_printf(m, "eeh_total_mmio_ffs=%ld\n" | |
908 | "eeh_false_positives=%ld\n" | |
909 | "eeh_ignored_failures=%ld\n" | |
910 | "eeh_slot_resets=%ld\n" | |
911 | "eeh_fail_count=%d\n", | |
912 | ffs, positives, failures, resets, | |
913 | eeh_fail_count.counter); | |
914 | } | |
915 | ||
916 | return 0; | |
917 | } | |
918 | ||
919 | static int proc_eeh_open(struct inode *inode, struct file *file) | |
920 | { | |
921 | return single_open(file, proc_eeh_show, NULL); | |
922 | } | |
923 | ||
924 | static struct file_operations proc_eeh_operations = { | |
925 | .open = proc_eeh_open, | |
926 | .read = seq_read, | |
927 | .llseek = seq_lseek, | |
928 | .release = single_release, | |
929 | }; | |
930 | ||
931 | static int __init eeh_init_proc(void) | |
932 | { | |
933 | struct proc_dir_entry *e; | |
934 | ||
935 | if (systemcfg->platform & PLATFORM_PSERIES) { | |
936 | e = create_proc_entry("ppc64/eeh", 0, NULL); | |
937 | if (e) | |
938 | e->proc_fops = &proc_eeh_operations; | |
939 | } | |
940 | ||
941 | return 0; | |
942 | } | |
943 | __initcall(eeh_init_proc); |