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1da177e4 LT |
1 | /* |
2 | * arch/ppc64/kernel/pSeries_iommu.c | |
3 | * | |
4 | * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation | |
5 | * | |
6 | * Rewrite, cleanup: | |
7 | * | |
8 | * Copyright (C) 2004 Olof Johansson <olof@austin.ibm.com>, IBM Corporation | |
9 | * | |
10 | * Dynamic DMA mapping support, pSeries-specific parts, both SMP and LPAR. | |
11 | * | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License as published by | |
15 | * the Free Software Foundation; either version 2 of the License, or | |
16 | * (at your option) any later version. | |
17 | * | |
18 | * This program is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public License | |
24 | * along with this program; if not, write to the Free Software | |
25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
26 | */ | |
27 | ||
28 | #include <linux/config.h> | |
29 | #include <linux/init.h> | |
30 | #include <linux/types.h> | |
31 | #include <linux/slab.h> | |
32 | #include <linux/mm.h> | |
33 | #include <linux/spinlock.h> | |
34 | #include <linux/string.h> | |
35 | #include <linux/pci.h> | |
36 | #include <linux/dma-mapping.h> | |
37 | #include <asm/io.h> | |
38 | #include <asm/prom.h> | |
39 | #include <asm/rtas.h> | |
40 | #include <asm/ppcdebug.h> | |
41 | #include <asm/iommu.h> | |
42 | #include <asm/pci-bridge.h> | |
43 | #include <asm/machdep.h> | |
44 | #include <asm/abs_addr.h> | |
45 | #include <asm/plpar_wrappers.h> | |
46 | #include <asm/pSeries_reconfig.h> | |
47 | #include <asm/systemcfg.h> | |
1ababe11 | 48 | #include <asm/firmware.h> |
1da177e4 LT |
49 | #include "pci.h" |
50 | ||
51 | #define DBG(fmt...) | |
52 | ||
53 | extern int is_python(struct device_node *); | |
54 | ||
55 | static void tce_build_pSeries(struct iommu_table *tbl, long index, | |
56 | long npages, unsigned long uaddr, | |
57 | enum dma_data_direction direction) | |
58 | { | |
59 | union tce_entry t; | |
60 | union tce_entry *tp; | |
61 | ||
62 | t.te_word = 0; | |
63 | t.te_rdwr = 1; // Read allowed | |
64 | ||
65 | if (direction != DMA_TO_DEVICE) | |
66 | t.te_pciwr = 1; | |
67 | ||
68 | tp = ((union tce_entry *)tbl->it_base) + index; | |
69 | ||
70 | while (npages--) { | |
71 | /* can't move this out since we might cross LMB boundary */ | |
72 | t.te_rpn = (virt_to_abs(uaddr)) >> PAGE_SHIFT; | |
73 | ||
74 | tp->te_word = t.te_word; | |
75 | ||
76 | uaddr += PAGE_SIZE; | |
77 | tp++; | |
78 | } | |
79 | } | |
80 | ||
81 | ||
82 | static void tce_free_pSeries(struct iommu_table *tbl, long index, long npages) | |
83 | { | |
84 | union tce_entry t; | |
85 | union tce_entry *tp; | |
86 | ||
87 | t.te_word = 0; | |
88 | tp = ((union tce_entry *)tbl->it_base) + index; | |
89 | ||
90 | while (npages--) { | |
91 | tp->te_word = t.te_word; | |
92 | ||
93 | tp++; | |
94 | } | |
95 | } | |
96 | ||
97 | ||
98 | static void tce_build_pSeriesLP(struct iommu_table *tbl, long tcenum, | |
99 | long npages, unsigned long uaddr, | |
100 | enum dma_data_direction direction) | |
101 | { | |
102 | u64 rc; | |
103 | union tce_entry tce; | |
104 | ||
105 | tce.te_word = 0; | |
106 | tce.te_rpn = (virt_to_abs(uaddr)) >> PAGE_SHIFT; | |
107 | tce.te_rdwr = 1; | |
108 | if (direction != DMA_TO_DEVICE) | |
109 | tce.te_pciwr = 1; | |
110 | ||
111 | while (npages--) { | |
112 | rc = plpar_tce_put((u64)tbl->it_index, | |
113 | (u64)tcenum << 12, | |
114 | tce.te_word ); | |
115 | ||
116 | if (rc && printk_ratelimit()) { | |
117 | printk("tce_build_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc); | |
118 | printk("\tindex = 0x%lx\n", (u64)tbl->it_index); | |
119 | printk("\ttcenum = 0x%lx\n", (u64)tcenum); | |
120 | printk("\ttce val = 0x%lx\n", tce.te_word ); | |
121 | show_stack(current, (unsigned long *)__get_SP()); | |
122 | } | |
123 | ||
124 | tcenum++; | |
125 | tce.te_rpn++; | |
126 | } | |
127 | } | |
128 | ||
129 | static DEFINE_PER_CPU(void *, tce_page) = NULL; | |
130 | ||
131 | static void tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum, | |
132 | long npages, unsigned long uaddr, | |
133 | enum dma_data_direction direction) | |
134 | { | |
135 | u64 rc; | |
136 | union tce_entry tce, *tcep; | |
137 | long l, limit; | |
138 | ||
139 | if (npages == 1) | |
140 | return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr, | |
141 | direction); | |
142 | ||
143 | tcep = __get_cpu_var(tce_page); | |
144 | ||
145 | /* This is safe to do since interrupts are off when we're called | |
146 | * from iommu_alloc{,_sg}() | |
147 | */ | |
148 | if (!tcep) { | |
149 | tcep = (void *)__get_free_page(GFP_ATOMIC); | |
150 | /* If allocation fails, fall back to the loop implementation */ | |
151 | if (!tcep) | |
152 | return tce_build_pSeriesLP(tbl, tcenum, npages, | |
153 | uaddr, direction); | |
154 | __get_cpu_var(tce_page) = tcep; | |
155 | } | |
156 | ||
157 | tce.te_word = 0; | |
158 | tce.te_rpn = (virt_to_abs(uaddr)) >> PAGE_SHIFT; | |
159 | tce.te_rdwr = 1; | |
160 | if (direction != DMA_TO_DEVICE) | |
161 | tce.te_pciwr = 1; | |
162 | ||
163 | /* We can map max one pageful of TCEs at a time */ | |
164 | do { | |
165 | /* | |
166 | * Set up the page with TCE data, looping through and setting | |
167 | * the values. | |
168 | */ | |
169 | limit = min_t(long, npages, PAGE_SIZE/sizeof(union tce_entry)); | |
170 | ||
171 | for (l = 0; l < limit; l++) { | |
172 | tcep[l] = tce; | |
173 | tce.te_rpn++; | |
174 | } | |
175 | ||
176 | rc = plpar_tce_put_indirect((u64)tbl->it_index, | |
177 | (u64)tcenum << 12, | |
178 | (u64)virt_to_abs(tcep), | |
179 | limit); | |
180 | ||
181 | npages -= limit; | |
182 | tcenum += limit; | |
183 | } while (npages > 0 && !rc); | |
184 | ||
185 | if (rc && printk_ratelimit()) { | |
186 | printk("tce_buildmulti_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc); | |
187 | printk("\tindex = 0x%lx\n", (u64)tbl->it_index); | |
188 | printk("\tnpages = 0x%lx\n", (u64)npages); | |
189 | printk("\ttce[0] val = 0x%lx\n", tcep[0].te_word); | |
190 | show_stack(current, (unsigned long *)__get_SP()); | |
191 | } | |
192 | } | |
193 | ||
194 | static void tce_free_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages) | |
195 | { | |
196 | u64 rc; | |
197 | union tce_entry tce; | |
198 | ||
199 | tce.te_word = 0; | |
200 | ||
201 | while (npages--) { | |
202 | rc = plpar_tce_put((u64)tbl->it_index, | |
203 | (u64)tcenum << 12, | |
204 | tce.te_word); | |
205 | ||
206 | if (rc && printk_ratelimit()) { | |
207 | printk("tce_free_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc); | |
208 | printk("\tindex = 0x%lx\n", (u64)tbl->it_index); | |
209 | printk("\ttcenum = 0x%lx\n", (u64)tcenum); | |
210 | printk("\ttce val = 0x%lx\n", tce.te_word ); | |
211 | show_stack(current, (unsigned long *)__get_SP()); | |
212 | } | |
213 | ||
214 | tcenum++; | |
215 | } | |
216 | } | |
217 | ||
218 | ||
219 | static void tce_freemulti_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages) | |
220 | { | |
221 | u64 rc; | |
222 | union tce_entry tce; | |
223 | ||
224 | tce.te_word = 0; | |
225 | ||
226 | rc = plpar_tce_stuff((u64)tbl->it_index, | |
227 | (u64)tcenum << 12, | |
228 | tce.te_word, | |
229 | npages); | |
230 | ||
231 | if (rc && printk_ratelimit()) { | |
232 | printk("tce_freemulti_pSeriesLP: plpar_tce_stuff failed\n"); | |
233 | printk("\trc = %ld\n", rc); | |
234 | printk("\tindex = 0x%lx\n", (u64)tbl->it_index); | |
235 | printk("\tnpages = 0x%lx\n", (u64)npages); | |
236 | printk("\ttce val = 0x%lx\n", tce.te_word ); | |
237 | show_stack(current, (unsigned long *)__get_SP()); | |
238 | } | |
239 | } | |
240 | ||
241 | static void iommu_table_setparms(struct pci_controller *phb, | |
242 | struct device_node *dn, | |
243 | struct iommu_table *tbl) | |
244 | { | |
245 | struct device_node *node; | |
246 | unsigned long *basep; | |
247 | unsigned int *sizep; | |
248 | ||
249 | node = (struct device_node *)phb->arch_data; | |
250 | ||
251 | basep = (unsigned long *)get_property(node, "linux,tce-base", NULL); | |
252 | sizep = (unsigned int *)get_property(node, "linux,tce-size", NULL); | |
253 | if (basep == NULL || sizep == NULL) { | |
254 | printk(KERN_ERR "PCI_DMA: iommu_table_setparms: %s has " | |
255 | "missing tce entries !\n", dn->full_name); | |
256 | return; | |
257 | } | |
258 | ||
259 | tbl->it_base = (unsigned long)__va(*basep); | |
260 | memset((void *)tbl->it_base, 0, *sizep); | |
261 | ||
262 | tbl->it_busno = phb->bus->number; | |
263 | ||
264 | /* Units of tce entries */ | |
265 | tbl->it_offset = phb->dma_window_base_cur >> PAGE_SHIFT; | |
266 | ||
267 | /* Test if we are going over 2GB of DMA space */ | |
268 | if (phb->dma_window_base_cur + phb->dma_window_size > (1L << 31)) | |
269 | panic("PCI_DMA: Unexpected number of IOAs under this PHB.\n"); | |
270 | ||
271 | phb->dma_window_base_cur += phb->dma_window_size; | |
272 | ||
273 | /* Set the tce table size - measured in entries */ | |
274 | tbl->it_size = phb->dma_window_size >> PAGE_SHIFT; | |
275 | ||
276 | tbl->it_index = 0; | |
277 | tbl->it_blocksize = 16; | |
278 | tbl->it_type = TCE_PCI; | |
279 | } | |
280 | ||
281 | /* | |
282 | * iommu_table_setparms_lpar | |
283 | * | |
284 | * Function: On pSeries LPAR systems, return TCE table info, given a pci bus. | |
285 | * | |
286 | * ToDo: properly interpret the ibm,dma-window property. The definition is: | |
287 | * logical-bus-number (1 word) | |
288 | * phys-address (#address-cells words) | |
289 | * size (#cell-size words) | |
290 | * | |
291 | * Currently we hard code these sizes (more or less). | |
292 | */ | |
293 | static void iommu_table_setparms_lpar(struct pci_controller *phb, | |
294 | struct device_node *dn, | |
295 | struct iommu_table *tbl, | |
296 | unsigned int *dma_window) | |
297 | { | |
1635317f | 298 | tbl->it_busno = PCI_DN(dn)->bussubno; |
1da177e4 LT |
299 | |
300 | /* TODO: Parse field size properties properly. */ | |
301 | tbl->it_size = (((unsigned long)dma_window[4] << 32) | | |
302 | (unsigned long)dma_window[5]) >> PAGE_SHIFT; | |
303 | tbl->it_offset = (((unsigned long)dma_window[2] << 32) | | |
304 | (unsigned long)dma_window[3]) >> PAGE_SHIFT; | |
305 | tbl->it_base = 0; | |
306 | tbl->it_index = dma_window[0]; | |
307 | tbl->it_blocksize = 16; | |
308 | tbl->it_type = TCE_PCI; | |
309 | } | |
310 | ||
311 | static void iommu_bus_setup_pSeries(struct pci_bus *bus) | |
312 | { | |
313 | struct device_node *dn, *pdn; | |
1635317f | 314 | struct pci_dn *pci; |
1da177e4 LT |
315 | struct iommu_table *tbl; |
316 | ||
317 | DBG("iommu_bus_setup_pSeries, bus %p, bus->self %p\n", bus, bus->self); | |
318 | ||
319 | /* For each (root) bus, we carve up the available DMA space in 256MB | |
320 | * pieces. Since each piece is used by one (sub) bus/device, that would | |
321 | * give a maximum of 7 devices per PHB. In most cases, this is plenty. | |
322 | * | |
323 | * The exception is on Python PHBs (pre-POWER4). Here we don't have EADS | |
324 | * bridges below the PHB to allocate the sectioned tables to, so instead | |
325 | * we allocate a 1GB table at the PHB level. | |
326 | */ | |
327 | ||
328 | dn = pci_bus_to_OF_node(bus); | |
1635317f | 329 | pci = dn->data; |
1da177e4 LT |
330 | |
331 | if (!bus->self) { | |
332 | /* Root bus */ | |
333 | if (is_python(dn)) { | |
334 | unsigned int *iohole; | |
335 | ||
336 | DBG("Python root bus %s\n", bus->name); | |
337 | ||
338 | iohole = (unsigned int *)get_property(dn, "io-hole", 0); | |
339 | ||
340 | if (iohole) { | |
341 | /* On first bus we need to leave room for the | |
342 | * ISA address space. Just skip the first 256MB | |
343 | * alltogether. This leaves 768MB for the window. | |
344 | */ | |
345 | DBG("PHB has io-hole, reserving 256MB\n"); | |
1635317f PM |
346 | pci->phb->dma_window_size = 3 << 28; |
347 | pci->phb->dma_window_base_cur = 1 << 28; | |
1da177e4 LT |
348 | } else { |
349 | /* 1GB window by default */ | |
1635317f PM |
350 | pci->phb->dma_window_size = 1 << 30; |
351 | pci->phb->dma_window_base_cur = 0; | |
1da177e4 LT |
352 | } |
353 | ||
354 | tbl = kmalloc(sizeof(struct iommu_table), GFP_KERNEL); | |
355 | ||
1635317f PM |
356 | iommu_table_setparms(pci->phb, dn, tbl); |
357 | pci->iommu_table = iommu_init_table(tbl); | |
1da177e4 LT |
358 | } else { |
359 | /* Do a 128MB table at root. This is used for the IDE | |
360 | * controller on some SMP-mode POWER4 machines. It | |
361 | * doesn't hurt to allocate it on other machines | |
362 | * -- it'll just be unused since new tables are | |
363 | * allocated on the EADS level. | |
364 | * | |
365 | * Allocate at offset 128MB to avoid having to deal | |
366 | * with ISA holes; 128MB table for IDE is plenty. | |
367 | */ | |
1635317f PM |
368 | pci->phb->dma_window_size = 1 << 27; |
369 | pci->phb->dma_window_base_cur = 1 << 27; | |
1da177e4 LT |
370 | |
371 | tbl = kmalloc(sizeof(struct iommu_table), GFP_KERNEL); | |
372 | ||
1635317f PM |
373 | iommu_table_setparms(pci->phb, dn, tbl); |
374 | pci->iommu_table = iommu_init_table(tbl); | |
1da177e4 LT |
375 | |
376 | /* All child buses have 256MB tables */ | |
1635317f | 377 | pci->phb->dma_window_size = 1 << 28; |
1da177e4 LT |
378 | } |
379 | } else { | |
380 | pdn = pci_bus_to_OF_node(bus->parent); | |
381 | ||
382 | if (!bus->parent->self && !is_python(pdn)) { | |
383 | struct iommu_table *tbl; | |
384 | /* First child and not python means this is the EADS | |
385 | * level. Allocate new table for this slot with 256MB | |
386 | * window. | |
387 | */ | |
388 | ||
389 | tbl = kmalloc(sizeof(struct iommu_table), GFP_KERNEL); | |
390 | ||
1635317f | 391 | iommu_table_setparms(pci->phb, dn, tbl); |
1da177e4 | 392 | |
1635317f | 393 | pci->iommu_table = iommu_init_table(tbl); |
1da177e4 LT |
394 | } else { |
395 | /* Lower than first child or under python, use parent table */ | |
1635317f | 396 | pci->iommu_table = PCI_DN(pdn)->iommu_table; |
1da177e4 LT |
397 | } |
398 | } | |
399 | } | |
400 | ||
401 | ||
402 | static void iommu_bus_setup_pSeriesLP(struct pci_bus *bus) | |
403 | { | |
404 | struct iommu_table *tbl; | |
405 | struct device_node *dn, *pdn; | |
1635317f | 406 | struct pci_dn *ppci; |
1da177e4 LT |
407 | unsigned int *dma_window = NULL; |
408 | ||
409 | DBG("iommu_bus_setup_pSeriesLP, bus %p, bus->self %p\n", bus, bus->self); | |
410 | ||
411 | dn = pci_bus_to_OF_node(bus); | |
412 | ||
413 | /* Find nearest ibm,dma-window, walking up the device tree */ | |
414 | for (pdn = dn; pdn != NULL; pdn = pdn->parent) { | |
415 | dma_window = (unsigned int *)get_property(pdn, "ibm,dma-window", NULL); | |
416 | if (dma_window != NULL) | |
417 | break; | |
418 | } | |
419 | ||
420 | if (dma_window == NULL) { | |
421 | DBG("iommu_bus_setup_pSeriesLP: bus %s seems to have no ibm,dma-window property\n", dn->full_name); | |
422 | return; | |
423 | } | |
424 | ||
1635317f PM |
425 | ppci = pdn->data; |
426 | if (!ppci->iommu_table) { | |
1da177e4 LT |
427 | /* Bussubno hasn't been copied yet. |
428 | * Do it now because iommu_table_setparms_lpar needs it. | |
429 | */ | |
1635317f PM |
430 | |
431 | ppci->bussubno = bus->number; | |
1da177e4 LT |
432 | |
433 | tbl = (struct iommu_table *)kmalloc(sizeof(struct iommu_table), | |
434 | GFP_KERNEL); | |
435 | ||
1635317f | 436 | iommu_table_setparms_lpar(ppci->phb, pdn, tbl, dma_window); |
1da177e4 | 437 | |
1635317f | 438 | ppci->iommu_table = iommu_init_table(tbl); |
1da177e4 LT |
439 | } |
440 | ||
441 | if (pdn != dn) | |
1635317f | 442 | PCI_DN(dn)->iommu_table = ppci->iommu_table; |
1da177e4 LT |
443 | } |
444 | ||
445 | ||
446 | static void iommu_dev_setup_pSeries(struct pci_dev *dev) | |
447 | { | |
448 | struct device_node *dn, *mydn; | |
449 | ||
450 | DBG("iommu_dev_setup_pSeries, dev %p (%s)\n", dev, dev->pretty_name); | |
451 | /* Now copy the iommu_table ptr from the bus device down to the | |
452 | * pci device_node. This means get_iommu_table() won't need to search | |
453 | * up the device tree to find it. | |
454 | */ | |
455 | mydn = dn = pci_device_to_OF_node(dev); | |
456 | ||
1635317f | 457 | while (dn && dn->data && PCI_DN(dn)->iommu_table == NULL) |
1da177e4 LT |
458 | dn = dn->parent; |
459 | ||
1635317f PM |
460 | if (dn && dn->data) { |
461 | PCI_DN(mydn)->iommu_table = PCI_DN(dn)->iommu_table; | |
1da177e4 LT |
462 | } else { |
463 | DBG("iommu_dev_setup_pSeries, dev %p (%s) has no iommu table\n", dev, dev->pretty_name); | |
464 | } | |
465 | } | |
466 | ||
467 | static int iommu_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *node) | |
468 | { | |
469 | int err = NOTIFY_OK; | |
470 | struct device_node *np = node; | |
1635317f | 471 | struct pci_dn *pci = np->data; |
1da177e4 LT |
472 | |
473 | switch (action) { | |
474 | case PSERIES_RECONFIG_REMOVE: | |
1635317f | 475 | if (pci->iommu_table && |
1da177e4 LT |
476 | get_property(np, "ibm,dma-window", NULL)) |
477 | iommu_free_table(np); | |
478 | break; | |
479 | default: | |
480 | err = NOTIFY_DONE; | |
481 | break; | |
482 | } | |
483 | return err; | |
484 | } | |
485 | ||
486 | static struct notifier_block iommu_reconfig_nb = { | |
487 | .notifier_call = iommu_reconfig_notifier, | |
488 | }; | |
489 | ||
490 | static void iommu_dev_setup_pSeriesLP(struct pci_dev *dev) | |
491 | { | |
492 | struct device_node *pdn, *dn; | |
493 | struct iommu_table *tbl; | |
494 | int *dma_window = NULL; | |
1635317f | 495 | struct pci_dn *pci; |
1da177e4 LT |
496 | |
497 | DBG("iommu_dev_setup_pSeriesLP, dev %p (%s)\n", dev, dev->pretty_name); | |
498 | ||
499 | /* dev setup for LPAR is a little tricky, since the device tree might | |
500 | * contain the dma-window properties per-device and not neccesarily | |
501 | * for the bus. So we need to search upwards in the tree until we | |
502 | * either hit a dma-window property, OR find a parent with a table | |
503 | * already allocated. | |
504 | */ | |
505 | dn = pci_device_to_OF_node(dev); | |
506 | ||
1635317f PM |
507 | for (pdn = dn; pdn && pdn->data && !PCI_DN(pdn)->iommu_table; |
508 | pdn = pdn->parent) { | |
509 | dma_window = (unsigned int *) | |
510 | get_property(pdn, "ibm,dma-window", NULL); | |
1da177e4 LT |
511 | if (dma_window) |
512 | break; | |
513 | } | |
514 | ||
515 | /* Check for parent == NULL so we don't try to setup the empty EADS | |
516 | * slots on POWER4 machines. | |
517 | */ | |
518 | if (dma_window == NULL || pdn->parent == NULL) { | |
519 | /* Fall back to regular (non-LPAR) dev setup */ | |
520 | DBG("No dma window for device, falling back to regular setup\n"); | |
521 | iommu_dev_setup_pSeries(dev); | |
522 | return; | |
523 | } else { | |
524 | DBG("Found DMA window, allocating table\n"); | |
525 | } | |
526 | ||
1635317f PM |
527 | pci = pdn->data; |
528 | if (!pci->iommu_table) { | |
1da177e4 | 529 | /* iommu_table_setparms_lpar needs bussubno. */ |
1635317f | 530 | pci->bussubno = pci->phb->bus->number; |
1da177e4 LT |
531 | |
532 | tbl = (struct iommu_table *)kmalloc(sizeof(struct iommu_table), | |
533 | GFP_KERNEL); | |
534 | ||
1635317f | 535 | iommu_table_setparms_lpar(pci->phb, pdn, tbl, dma_window); |
1da177e4 | 536 | |
1635317f | 537 | pci->iommu_table = iommu_init_table(tbl); |
1da177e4 LT |
538 | } |
539 | ||
540 | if (pdn != dn) | |
1635317f | 541 | PCI_DN(dn)->iommu_table = pci->iommu_table; |
1da177e4 LT |
542 | } |
543 | ||
544 | static void iommu_bus_setup_null(struct pci_bus *b) { } | |
545 | static void iommu_dev_setup_null(struct pci_dev *d) { } | |
546 | ||
547 | /* These are called very early. */ | |
548 | void iommu_init_early_pSeries(void) | |
549 | { | |
550 | if (of_chosen && get_property(of_chosen, "linux,iommu-off", NULL)) { | |
551 | /* Direct I/O, IOMMU off */ | |
552 | ppc_md.iommu_dev_setup = iommu_dev_setup_null; | |
553 | ppc_md.iommu_bus_setup = iommu_bus_setup_null; | |
554 | pci_direct_iommu_init(); | |
555 | ||
556 | return; | |
557 | } | |
558 | ||
559 | if (systemcfg->platform & PLATFORM_LPAR) { | |
1ababe11 | 560 | if (firmware_has_feature(FW_FEATURE_MULTITCE)) { |
1da177e4 LT |
561 | ppc_md.tce_build = tce_buildmulti_pSeriesLP; |
562 | ppc_md.tce_free = tce_freemulti_pSeriesLP; | |
563 | } else { | |
564 | ppc_md.tce_build = tce_build_pSeriesLP; | |
565 | ppc_md.tce_free = tce_free_pSeriesLP; | |
566 | } | |
567 | ppc_md.iommu_bus_setup = iommu_bus_setup_pSeriesLP; | |
568 | ppc_md.iommu_dev_setup = iommu_dev_setup_pSeriesLP; | |
569 | } else { | |
570 | ppc_md.tce_build = tce_build_pSeries; | |
571 | ppc_md.tce_free = tce_free_pSeries; | |
572 | ppc_md.iommu_bus_setup = iommu_bus_setup_pSeries; | |
573 | ppc_md.iommu_dev_setup = iommu_dev_setup_pSeries; | |
574 | } | |
575 | ||
576 | ||
577 | pSeries_reconfig_notifier_register(&iommu_reconfig_nb); | |
578 | ||
579 | pci_iommu_init(); | |
580 | } | |
581 |