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1da177e4 LT |
1 | #ifndef _S390_RWSEM_H |
2 | #define _S390_RWSEM_H | |
3 | ||
4 | /* | |
5 | * include/asm-s390/rwsem.h | |
6 | * | |
7 | * S390 version | |
8 | * Copyright (C) 2002 IBM Deutschland Entwicklung GmbH, IBM Corporation | |
9 | * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com) | |
10 | * | |
11 | * Based on asm-alpha/semaphore.h and asm-i386/rwsem.h | |
12 | */ | |
13 | ||
14 | /* | |
15 | * | |
16 | * The MSW of the count is the negated number of active writers and waiting | |
17 | * lockers, and the LSW is the total number of active locks | |
18 | * | |
19 | * The lock count is initialized to 0 (no active and no waiting lockers). | |
20 | * | |
21 | * When a writer subtracts WRITE_BIAS, it'll get 0xffff0001 for the case of an | |
22 | * uncontended lock. This can be determined because XADD returns the old value. | |
23 | * Readers increment by 1 and see a positive value when uncontended, negative | |
24 | * if there are writers (and maybe) readers waiting (in which case it goes to | |
25 | * sleep). | |
26 | * | |
27 | * The value of WAITING_BIAS supports up to 32766 waiting processes. This can | |
28 | * be extended to 65534 by manually checking the whole MSW rather than relying | |
29 | * on the S flag. | |
30 | * | |
31 | * The value of ACTIVE_BIAS supports up to 65535 active processes. | |
32 | * | |
33 | * This should be totally fair - if anything is waiting, a process that wants a | |
34 | * lock will go to the back of the queue. When the currently active lock is | |
35 | * released, if there's a writer at the front of the queue, then that and only | |
36 | * that will be woken up; if there's a bunch of consequtive readers at the | |
37 | * front, then they'll all be woken up, but no other readers will be. | |
38 | */ | |
39 | ||
40 | #ifndef _LINUX_RWSEM_H | |
41 | #error "please don't include asm/rwsem.h directly, use linux/rwsem.h instead" | |
42 | #endif | |
43 | ||
f4815ac6 | 44 | #ifndef CONFIG_64BIT |
1da177e4 LT |
45 | #define RWSEM_UNLOCKED_VALUE 0x00000000 |
46 | #define RWSEM_ACTIVE_BIAS 0x00000001 | |
47 | #define RWSEM_ACTIVE_MASK 0x0000ffff | |
48 | #define RWSEM_WAITING_BIAS (-0x00010000) | |
f4815ac6 | 49 | #else /* CONFIG_64BIT */ |
1da177e4 LT |
50 | #define RWSEM_UNLOCKED_VALUE 0x0000000000000000L |
51 | #define RWSEM_ACTIVE_BIAS 0x0000000000000001L | |
52 | #define RWSEM_ACTIVE_MASK 0x00000000ffffffffL | |
53 | #define RWSEM_WAITING_BIAS (-0x0000000100000000L) | |
f4815ac6 | 54 | #endif /* CONFIG_64BIT */ |
1da177e4 LT |
55 | #define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS |
56 | #define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS) | |
57 | ||
1da177e4 LT |
58 | /* |
59 | * lock for reading | |
60 | */ | |
61 | static inline void __down_read(struct rw_semaphore *sem) | |
62 | { | |
63 | signed long old, new; | |
64 | ||
94c12cc7 | 65 | asm volatile( |
f4815ac6 | 66 | #ifndef CONFIG_64BIT |
987bcdac | 67 | " l %0,%2\n" |
94c12cc7 | 68 | "0: lr %1,%0\n" |
987bcdac MS |
69 | " ahi %1,%4\n" |
70 | " cs %0,%1,%2\n" | |
94c12cc7 | 71 | " jl 0b" |
f4815ac6 | 72 | #else /* CONFIG_64BIT */ |
987bcdac | 73 | " lg %0,%2\n" |
94c12cc7 | 74 | "0: lgr %1,%0\n" |
987bcdac MS |
75 | " aghi %1,%4\n" |
76 | " csg %0,%1,%2\n" | |
94c12cc7 | 77 | " jl 0b" |
f4815ac6 | 78 | #endif /* CONFIG_64BIT */ |
987bcdac MS |
79 | : "=&d" (old), "=&d" (new), "=Q" (sem->count) |
80 | : "Q" (sem->count), "i" (RWSEM_ACTIVE_READ_BIAS) | |
81 | : "cc", "memory"); | |
1da177e4 LT |
82 | if (old < 0) |
83 | rwsem_down_read_failed(sem); | |
84 | } | |
85 | ||
86 | /* | |
87 | * trylock for reading -- returns 1 if successful, 0 if contention | |
88 | */ | |
89 | static inline int __down_read_trylock(struct rw_semaphore *sem) | |
90 | { | |
91 | signed long old, new; | |
92 | ||
94c12cc7 | 93 | asm volatile( |
f4815ac6 | 94 | #ifndef CONFIG_64BIT |
987bcdac | 95 | " l %0,%2\n" |
94c12cc7 MS |
96 | "0: ltr %1,%0\n" |
97 | " jm 1f\n" | |
987bcdac MS |
98 | " ahi %1,%4\n" |
99 | " cs %0,%1,%2\n" | |
94c12cc7 | 100 | " jl 0b\n" |
1da177e4 | 101 | "1:" |
f4815ac6 | 102 | #else /* CONFIG_64BIT */ |
987bcdac | 103 | " lg %0,%2\n" |
94c12cc7 MS |
104 | "0: ltgr %1,%0\n" |
105 | " jm 1f\n" | |
987bcdac MS |
106 | " aghi %1,%4\n" |
107 | " csg %0,%1,%2\n" | |
94c12cc7 | 108 | " jl 0b\n" |
1da177e4 | 109 | "1:" |
f4815ac6 | 110 | #endif /* CONFIG_64BIT */ |
987bcdac MS |
111 | : "=&d" (old), "=&d" (new), "=Q" (sem->count) |
112 | : "Q" (sem->count), "i" (RWSEM_ACTIVE_READ_BIAS) | |
113 | : "cc", "memory"); | |
1da177e4 LT |
114 | return old >= 0 ? 1 : 0; |
115 | } | |
116 | ||
117 | /* | |
118 | * lock for writing | |
119 | */ | |
4ea2176d | 120 | static inline void __down_write_nested(struct rw_semaphore *sem, int subclass) |
1da177e4 LT |
121 | { |
122 | signed long old, new, tmp; | |
123 | ||
124 | tmp = RWSEM_ACTIVE_WRITE_BIAS; | |
94c12cc7 | 125 | asm volatile( |
f4815ac6 | 126 | #ifndef CONFIG_64BIT |
987bcdac | 127 | " l %0,%2\n" |
94c12cc7 | 128 | "0: lr %1,%0\n" |
987bcdac MS |
129 | " a %1,%4\n" |
130 | " cs %0,%1,%2\n" | |
94c12cc7 | 131 | " jl 0b" |
f4815ac6 | 132 | #else /* CONFIG_64BIT */ |
987bcdac | 133 | " lg %0,%2\n" |
94c12cc7 | 134 | "0: lgr %1,%0\n" |
987bcdac MS |
135 | " ag %1,%4\n" |
136 | " csg %0,%1,%2\n" | |
94c12cc7 | 137 | " jl 0b" |
f4815ac6 | 138 | #endif /* CONFIG_64BIT */ |
987bcdac MS |
139 | : "=&d" (old), "=&d" (new), "=Q" (sem->count) |
140 | : "Q" (sem->count), "m" (tmp) | |
94c12cc7 | 141 | : "cc", "memory"); |
1da177e4 LT |
142 | if (old != 0) |
143 | rwsem_down_write_failed(sem); | |
144 | } | |
145 | ||
4ea2176d IM |
146 | static inline void __down_write(struct rw_semaphore *sem) |
147 | { | |
148 | __down_write_nested(sem, 0); | |
149 | } | |
150 | ||
1da177e4 LT |
151 | /* |
152 | * trylock for writing -- returns 1 if successful, 0 if contention | |
153 | */ | |
154 | static inline int __down_write_trylock(struct rw_semaphore *sem) | |
155 | { | |
156 | signed long old; | |
157 | ||
94c12cc7 | 158 | asm volatile( |
f4815ac6 | 159 | #ifndef CONFIG_64BIT |
987bcdac | 160 | " l %0,%1\n" |
94c12cc7 MS |
161 | "0: ltr %0,%0\n" |
162 | " jnz 1f\n" | |
987bcdac | 163 | " cs %0,%3,%1\n" |
94c12cc7 | 164 | " jl 0b\n" |
f4815ac6 | 165 | #else /* CONFIG_64BIT */ |
987bcdac | 166 | " lg %0,%1\n" |
94c12cc7 MS |
167 | "0: ltgr %0,%0\n" |
168 | " jnz 1f\n" | |
987bcdac | 169 | " csg %0,%3,%1\n" |
94c12cc7 | 170 | " jl 0b\n" |
f4815ac6 | 171 | #endif /* CONFIG_64BIT */ |
1da177e4 | 172 | "1:" |
987bcdac MS |
173 | : "=&d" (old), "=Q" (sem->count) |
174 | : "Q" (sem->count), "d" (RWSEM_ACTIVE_WRITE_BIAS) | |
175 | : "cc", "memory"); | |
1da177e4 LT |
176 | return (old == RWSEM_UNLOCKED_VALUE) ? 1 : 0; |
177 | } | |
178 | ||
179 | /* | |
180 | * unlock after reading | |
181 | */ | |
182 | static inline void __up_read(struct rw_semaphore *sem) | |
183 | { | |
184 | signed long old, new; | |
185 | ||
94c12cc7 | 186 | asm volatile( |
f4815ac6 | 187 | #ifndef CONFIG_64BIT |
987bcdac | 188 | " l %0,%2\n" |
94c12cc7 | 189 | "0: lr %1,%0\n" |
987bcdac MS |
190 | " ahi %1,%4\n" |
191 | " cs %0,%1,%2\n" | |
94c12cc7 | 192 | " jl 0b" |
f4815ac6 | 193 | #else /* CONFIG_64BIT */ |
987bcdac | 194 | " lg %0,%2\n" |
94c12cc7 | 195 | "0: lgr %1,%0\n" |
987bcdac MS |
196 | " aghi %1,%4\n" |
197 | " csg %0,%1,%2\n" | |
94c12cc7 | 198 | " jl 0b" |
f4815ac6 | 199 | #endif /* CONFIG_64BIT */ |
987bcdac MS |
200 | : "=&d" (old), "=&d" (new), "=Q" (sem->count) |
201 | : "Q" (sem->count), "i" (-RWSEM_ACTIVE_READ_BIAS) | |
94c12cc7 | 202 | : "cc", "memory"); |
1da177e4 LT |
203 | if (new < 0) |
204 | if ((new & RWSEM_ACTIVE_MASK) == 0) | |
205 | rwsem_wake(sem); | |
206 | } | |
207 | ||
208 | /* | |
209 | * unlock after writing | |
210 | */ | |
211 | static inline void __up_write(struct rw_semaphore *sem) | |
212 | { | |
213 | signed long old, new, tmp; | |
214 | ||
215 | tmp = -RWSEM_ACTIVE_WRITE_BIAS; | |
94c12cc7 | 216 | asm volatile( |
f4815ac6 | 217 | #ifndef CONFIG_64BIT |
987bcdac | 218 | " l %0,%2\n" |
94c12cc7 | 219 | "0: lr %1,%0\n" |
987bcdac MS |
220 | " a %1,%4\n" |
221 | " cs %0,%1,%2\n" | |
94c12cc7 | 222 | " jl 0b" |
f4815ac6 | 223 | #else /* CONFIG_64BIT */ |
987bcdac | 224 | " lg %0,%2\n" |
94c12cc7 | 225 | "0: lgr %1,%0\n" |
987bcdac MS |
226 | " ag %1,%4\n" |
227 | " csg %0,%1,%2\n" | |
94c12cc7 | 228 | " jl 0b" |
f4815ac6 | 229 | #endif /* CONFIG_64BIT */ |
987bcdac MS |
230 | : "=&d" (old), "=&d" (new), "=Q" (sem->count) |
231 | : "Q" (sem->count), "m" (tmp) | |
94c12cc7 | 232 | : "cc", "memory"); |
1da177e4 LT |
233 | if (new < 0) |
234 | if ((new & RWSEM_ACTIVE_MASK) == 0) | |
235 | rwsem_wake(sem); | |
236 | } | |
237 | ||
238 | /* | |
239 | * downgrade write lock to read lock | |
240 | */ | |
241 | static inline void __downgrade_write(struct rw_semaphore *sem) | |
242 | { | |
243 | signed long old, new, tmp; | |
244 | ||
245 | tmp = -RWSEM_WAITING_BIAS; | |
94c12cc7 | 246 | asm volatile( |
f4815ac6 | 247 | #ifndef CONFIG_64BIT |
987bcdac | 248 | " l %0,%2\n" |
94c12cc7 | 249 | "0: lr %1,%0\n" |
987bcdac MS |
250 | " a %1,%4\n" |
251 | " cs %0,%1,%2\n" | |
94c12cc7 | 252 | " jl 0b" |
f4815ac6 | 253 | #else /* CONFIG_64BIT */ |
987bcdac | 254 | " lg %0,%2\n" |
94c12cc7 | 255 | "0: lgr %1,%0\n" |
987bcdac MS |
256 | " ag %1,%4\n" |
257 | " csg %0,%1,%2\n" | |
94c12cc7 | 258 | " jl 0b" |
f4815ac6 | 259 | #endif /* CONFIG_64BIT */ |
987bcdac MS |
260 | : "=&d" (old), "=&d" (new), "=Q" (sem->count) |
261 | : "Q" (sem->count), "m" (tmp) | |
94c12cc7 | 262 | : "cc", "memory"); |
1da177e4 LT |
263 | if (new > 1) |
264 | rwsem_downgrade_wake(sem); | |
265 | } | |
266 | ||
267 | /* | |
268 | * implement atomic add functionality | |
269 | */ | |
270 | static inline void rwsem_atomic_add(long delta, struct rw_semaphore *sem) | |
271 | { | |
272 | signed long old, new; | |
273 | ||
94c12cc7 | 274 | asm volatile( |
f4815ac6 | 275 | #ifndef CONFIG_64BIT |
987bcdac | 276 | " l %0,%2\n" |
94c12cc7 | 277 | "0: lr %1,%0\n" |
987bcdac MS |
278 | " ar %1,%4\n" |
279 | " cs %0,%1,%2\n" | |
94c12cc7 | 280 | " jl 0b" |
f4815ac6 | 281 | #else /* CONFIG_64BIT */ |
987bcdac | 282 | " lg %0,%2\n" |
94c12cc7 | 283 | "0: lgr %1,%0\n" |
987bcdac MS |
284 | " agr %1,%4\n" |
285 | " csg %0,%1,%2\n" | |
94c12cc7 | 286 | " jl 0b" |
f4815ac6 | 287 | #endif /* CONFIG_64BIT */ |
987bcdac MS |
288 | : "=&d" (old), "=&d" (new), "=Q" (sem->count) |
289 | : "Q" (sem->count), "d" (delta) | |
94c12cc7 | 290 | : "cc", "memory"); |
1da177e4 LT |
291 | } |
292 | ||
293 | /* | |
294 | * implement exchange and add functionality | |
295 | */ | |
296 | static inline long rwsem_atomic_update(long delta, struct rw_semaphore *sem) | |
297 | { | |
298 | signed long old, new; | |
299 | ||
94c12cc7 | 300 | asm volatile( |
f4815ac6 | 301 | #ifndef CONFIG_64BIT |
987bcdac | 302 | " l %0,%2\n" |
94c12cc7 | 303 | "0: lr %1,%0\n" |
987bcdac MS |
304 | " ar %1,%4\n" |
305 | " cs %0,%1,%2\n" | |
94c12cc7 | 306 | " jl 0b" |
f4815ac6 | 307 | #else /* CONFIG_64BIT */ |
987bcdac | 308 | " lg %0,%2\n" |
94c12cc7 | 309 | "0: lgr %1,%0\n" |
987bcdac MS |
310 | " agr %1,%4\n" |
311 | " csg %0,%1,%2\n" | |
94c12cc7 | 312 | " jl 0b" |
f4815ac6 | 313 | #endif /* CONFIG_64BIT */ |
987bcdac MS |
314 | : "=&d" (old), "=&d" (new), "=Q" (sem->count) |
315 | : "Q" (sem->count), "d" (delta) | |
94c12cc7 | 316 | : "cc", "memory"); |
1da177e4 LT |
317 | return new; |
318 | } | |
319 | ||
1da177e4 | 320 | #endif /* _S390_RWSEM_H */ |