Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * arch/s390/kernel/smp.c | |
3 | * | |
39ce010d | 4 | * Copyright IBM Corp. 1999,2007 |
1da177e4 | 5 | * Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com), |
39ce010d HC |
6 | * Martin Schwidefsky (schwidefsky@de.ibm.com) |
7 | * Heiko Carstens (heiko.carstens@de.ibm.com) | |
1da177e4 | 8 | * |
39ce010d | 9 | * based on other smp stuff by |
1da177e4 LT |
10 | * (c) 1995 Alan Cox, CymruNET Ltd <alan@cymru.net> |
11 | * (c) 1998 Ingo Molnar | |
12 | * | |
13 | * We work with logical cpu numbering everywhere we can. The only | |
14 | * functions using the real cpu address (got from STAP) are the sigp | |
15 | * functions. For all other functions we use the identity mapping. | |
16 | * That means that cpu_number_map[i] == i for every cpu. cpu_number_map is | |
17 | * used e.g. to find the idle task belonging to a logical cpu. Every array | |
18 | * in the kernel is sorted by the logical cpu number and not by the physical | |
19 | * one which is causing all the confusion with __cpu_logical_map and | |
20 | * cpu_number_map in other architectures. | |
21 | */ | |
22 | ||
395d31d4 MS |
23 | #define KMSG_COMPONENT "cpu" |
24 | #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt | |
25 | ||
1da177e4 LT |
26 | #include <linux/module.h> |
27 | #include <linux/init.h> | |
1da177e4 | 28 | #include <linux/mm.h> |
4e950f6f | 29 | #include <linux/err.h> |
1da177e4 LT |
30 | #include <linux/spinlock.h> |
31 | #include <linux/kernel_stat.h> | |
1da177e4 LT |
32 | #include <linux/delay.h> |
33 | #include <linux/cache.h> | |
34 | #include <linux/interrupt.h> | |
35 | #include <linux/cpu.h> | |
2b67fc46 | 36 | #include <linux/timex.h> |
411ed322 | 37 | #include <linux/bootmem.h> |
46b05d26 | 38 | #include <asm/ipl.h> |
2b67fc46 | 39 | #include <asm/setup.h> |
1da177e4 LT |
40 | #include <asm/sigp.h> |
41 | #include <asm/pgalloc.h> | |
42 | #include <asm/irq.h> | |
43 | #include <asm/s390_ext.h> | |
44 | #include <asm/cpcmd.h> | |
45 | #include <asm/tlbflush.h> | |
2b67fc46 | 46 | #include <asm/timer.h> |
411ed322 | 47 | #include <asm/lowcore.h> |
08d07968 | 48 | #include <asm/sclp.h> |
fae8b22d | 49 | #include <asm/cpu.h> |
a806170e | 50 | #include "entry.h" |
1da177e4 | 51 | |
1da177e4 LT |
52 | /* |
53 | * An array with a pointer the lowcore of every CPU. | |
54 | */ | |
1da177e4 | 55 | struct _lowcore *lowcore_ptr[NR_CPUS]; |
39ce010d | 56 | EXPORT_SYMBOL(lowcore_ptr); |
1da177e4 | 57 | |
255acee7 | 58 | cpumask_t cpu_online_map = CPU_MASK_NONE; |
39ce010d HC |
59 | EXPORT_SYMBOL(cpu_online_map); |
60 | ||
48483b32 | 61 | cpumask_t cpu_possible_map = CPU_MASK_ALL; |
39ce010d | 62 | EXPORT_SYMBOL(cpu_possible_map); |
1da177e4 LT |
63 | |
64 | static struct task_struct *current_set[NR_CPUS]; | |
65 | ||
08d07968 HC |
66 | static u8 smp_cpu_type; |
67 | static int smp_use_sigp_detection; | |
68 | ||
69 | enum s390_cpu_state { | |
70 | CPU_STATE_STANDBY, | |
71 | CPU_STATE_CONFIGURED, | |
72 | }; | |
73 | ||
dbd70fb4 | 74 | DEFINE_MUTEX(smp_cpu_state_mutex); |
c10fde0d | 75 | int smp_cpu_polarization[NR_CPUS]; |
08d07968 | 76 | static int smp_cpu_state[NR_CPUS]; |
c10fde0d | 77 | static int cpu_management; |
08d07968 HC |
78 | |
79 | static DEFINE_PER_CPU(struct cpu, cpu_devices); | |
08d07968 | 80 | |
1da177e4 | 81 | static void smp_ext_bitcall(int, ec_bit_sig); |
1da177e4 | 82 | |
677d7623 | 83 | void smp_send_stop(void) |
1da177e4 | 84 | { |
39ce010d | 85 | int cpu, rc; |
1da177e4 | 86 | |
677d7623 HC |
87 | /* Disable all interrupts/machine checks */ |
88 | __load_psw_mask(psw_kernel_bits & ~PSW_MASK_MCHECK); | |
1da177e4 | 89 | |
677d7623 HC |
90 | /* write magic number to zero page (absolute 0) */ |
91 | lowcore_ptr[smp_processor_id()]->panic_magic = __PANIC_MAGIC; | |
1da177e4 | 92 | |
677d7623 | 93 | /* stop all processors */ |
1da177e4 LT |
94 | for_each_online_cpu(cpu) { |
95 | if (cpu == smp_processor_id()) | |
96 | continue; | |
97 | do { | |
677d7623 | 98 | rc = signal_processor(cpu, sigp_stop); |
39ce010d | 99 | } while (rc == sigp_busy); |
1da177e4 | 100 | |
39ce010d | 101 | while (!smp_cpu_not_running(cpu)) |
c6b5b847 HC |
102 | cpu_relax(); |
103 | } | |
104 | } | |
105 | ||
1da177e4 LT |
106 | /* |
107 | * This is the main routine where commands issued by other | |
108 | * cpus are handled. | |
109 | */ | |
110 | ||
2b67fc46 | 111 | static void do_ext_call_interrupt(__u16 code) |
1da177e4 | 112 | { |
39ce010d | 113 | unsigned long bits; |
1da177e4 | 114 | |
39ce010d HC |
115 | /* |
116 | * handle bit signal external calls | |
117 | * | |
118 | * For the ec_schedule signal we have to do nothing. All the work | |
119 | * is done automatically when we return from the interrupt. | |
120 | */ | |
1da177e4 LT |
121 | bits = xchg(&S390_lowcore.ext_call_fast, 0); |
122 | ||
39ce010d | 123 | if (test_bit(ec_call_function, &bits)) |
ca9fc75a HC |
124 | generic_smp_call_function_interrupt(); |
125 | ||
126 | if (test_bit(ec_call_function_single, &bits)) | |
127 | generic_smp_call_function_single_interrupt(); | |
1da177e4 LT |
128 | } |
129 | ||
130 | /* | |
131 | * Send an external call sigp to another cpu and return without waiting | |
132 | * for its completion. | |
133 | */ | |
134 | static void smp_ext_bitcall(int cpu, ec_bit_sig sig) | |
135 | { | |
39ce010d HC |
136 | /* |
137 | * Set signaling bit in lowcore of target cpu and kick it | |
138 | */ | |
1da177e4 | 139 | set_bit(sig, (unsigned long *) &lowcore_ptr[cpu]->ext_call_fast); |
39ce010d | 140 | while (signal_processor(cpu, sigp_emergency_signal) == sigp_busy) |
1da177e4 LT |
141 | udelay(10); |
142 | } | |
143 | ||
ca9fc75a HC |
144 | void arch_send_call_function_ipi(cpumask_t mask) |
145 | { | |
146 | int cpu; | |
147 | ||
148 | for_each_cpu_mask(cpu, mask) | |
149 | smp_ext_bitcall(cpu, ec_call_function); | |
150 | } | |
151 | ||
152 | void arch_send_call_function_single_ipi(int cpu) | |
153 | { | |
154 | smp_ext_bitcall(cpu, ec_call_function_single); | |
155 | } | |
156 | ||
347a8dc3 | 157 | #ifndef CONFIG_64BIT |
1da177e4 LT |
158 | /* |
159 | * this function sends a 'purge tlb' signal to another CPU. | |
160 | */ | |
a806170e | 161 | static void smp_ptlb_callback(void *info) |
1da177e4 | 162 | { |
ba8a9229 | 163 | __tlb_flush_local(); |
1da177e4 LT |
164 | } |
165 | ||
166 | void smp_ptlb_all(void) | |
167 | { | |
15c8b6c1 | 168 | on_each_cpu(smp_ptlb_callback, NULL, 1); |
1da177e4 LT |
169 | } |
170 | EXPORT_SYMBOL(smp_ptlb_all); | |
347a8dc3 | 171 | #endif /* ! CONFIG_64BIT */ |
1da177e4 LT |
172 | |
173 | /* | |
174 | * this function sends a 'reschedule' IPI to another CPU. | |
175 | * it goes straight through and wastes no time serializing | |
176 | * anything. Worst case is that we lose a reschedule ... | |
177 | */ | |
178 | void smp_send_reschedule(int cpu) | |
179 | { | |
39ce010d | 180 | smp_ext_bitcall(cpu, ec_schedule); |
1da177e4 LT |
181 | } |
182 | ||
183 | /* | |
184 | * parameter area for the set/clear control bit callbacks | |
185 | */ | |
94c12cc7 | 186 | struct ec_creg_mask_parms { |
1da177e4 LT |
187 | unsigned long orvals[16]; |
188 | unsigned long andvals[16]; | |
94c12cc7 | 189 | }; |
1da177e4 LT |
190 | |
191 | /* | |
192 | * callback for setting/clearing control bits | |
193 | */ | |
39ce010d HC |
194 | static void smp_ctl_bit_callback(void *info) |
195 | { | |
94c12cc7 | 196 | struct ec_creg_mask_parms *pp = info; |
1da177e4 LT |
197 | unsigned long cregs[16]; |
198 | int i; | |
39ce010d | 199 | |
94c12cc7 MS |
200 | __ctl_store(cregs, 0, 15); |
201 | for (i = 0; i <= 15; i++) | |
1da177e4 | 202 | cregs[i] = (cregs[i] & pp->andvals[i]) | pp->orvals[i]; |
94c12cc7 | 203 | __ctl_load(cregs, 0, 15); |
1da177e4 LT |
204 | } |
205 | ||
206 | /* | |
207 | * Set a bit in a control register of all cpus | |
208 | */ | |
94c12cc7 MS |
209 | void smp_ctl_set_bit(int cr, int bit) |
210 | { | |
211 | struct ec_creg_mask_parms parms; | |
1da177e4 | 212 | |
94c12cc7 MS |
213 | memset(&parms.orvals, 0, sizeof(parms.orvals)); |
214 | memset(&parms.andvals, 0xff, sizeof(parms.andvals)); | |
1da177e4 | 215 | parms.orvals[cr] = 1 << bit; |
15c8b6c1 | 216 | on_each_cpu(smp_ctl_bit_callback, &parms, 1); |
1da177e4 | 217 | } |
39ce010d | 218 | EXPORT_SYMBOL(smp_ctl_set_bit); |
1da177e4 LT |
219 | |
220 | /* | |
221 | * Clear a bit in a control register of all cpus | |
222 | */ | |
94c12cc7 MS |
223 | void smp_ctl_clear_bit(int cr, int bit) |
224 | { | |
225 | struct ec_creg_mask_parms parms; | |
1da177e4 | 226 | |
94c12cc7 MS |
227 | memset(&parms.orvals, 0, sizeof(parms.orvals)); |
228 | memset(&parms.andvals, 0xff, sizeof(parms.andvals)); | |
1da177e4 | 229 | parms.andvals[cr] = ~(1L << bit); |
15c8b6c1 | 230 | on_each_cpu(smp_ctl_bit_callback, &parms, 1); |
1da177e4 | 231 | } |
39ce010d | 232 | EXPORT_SYMBOL(smp_ctl_clear_bit); |
1da177e4 | 233 | |
08d07968 HC |
234 | /* |
235 | * In early ipl state a temp. logically cpu number is needed, so the sigp | |
236 | * functions can be used to sense other cpus. Since NR_CPUS is >= 2 on | |
237 | * CONFIG_SMP and the ipl cpu is logical cpu 0, it must be 1. | |
238 | */ | |
239 | #define CPU_INIT_NO 1 | |
240 | ||
411ed322 MH |
241 | #if defined(CONFIG_ZFCPDUMP) || defined(CONFIG_ZFCPDUMP_MODULE) |
242 | ||
243 | /* | |
244 | * zfcpdump_prefix_array holds prefix registers for the following scenario: | |
245 | * 64 bit zfcpdump kernel and 31 bit kernel which is to be dumped. We have to | |
246 | * save its prefix registers, since they get lost, when switching from 31 bit | |
247 | * to 64 bit. | |
248 | */ | |
249 | unsigned int zfcpdump_prefix_array[NR_CPUS + 1] \ | |
250 | __attribute__((__section__(".data"))); | |
251 | ||
285f6722 | 252 | static void __init smp_get_save_area(unsigned int cpu, unsigned int phy_cpu) |
411ed322 | 253 | { |
411ed322 MH |
254 | if (ipl_info.type != IPL_TYPE_FCP_DUMP) |
255 | return; | |
285f6722 | 256 | if (cpu >= NR_CPUS) { |
395d31d4 MS |
257 | pr_warning("CPU %i exceeds the maximum %i and is excluded from " |
258 | "the dump\n", cpu, NR_CPUS - 1); | |
285f6722 | 259 | return; |
411ed322 | 260 | } |
48483b32 | 261 | zfcpdump_save_areas[cpu] = kmalloc(sizeof(union save_area), GFP_KERNEL); |
08d07968 HC |
262 | __cpu_logical_map[CPU_INIT_NO] = (__u16) phy_cpu; |
263 | while (signal_processor(CPU_INIT_NO, sigp_stop_and_store_status) == | |
264 | sigp_busy) | |
285f6722 HC |
265 | cpu_relax(); |
266 | memcpy(zfcpdump_save_areas[cpu], | |
267 | (void *)(unsigned long) store_prefix() + SAVE_AREA_BASE, | |
268 | SAVE_AREA_SIZE); | |
269 | #ifdef CONFIG_64BIT | |
270 | /* copy original prefix register */ | |
271 | zfcpdump_save_areas[cpu]->s390x.pref_reg = zfcpdump_prefix_array[cpu]; | |
272 | #endif | |
411ed322 MH |
273 | } |
274 | ||
275 | union save_area *zfcpdump_save_areas[NR_CPUS + 1]; | |
276 | EXPORT_SYMBOL_GPL(zfcpdump_save_areas); | |
277 | ||
278 | #else | |
285f6722 HC |
279 | |
280 | static inline void smp_get_save_area(unsigned int cpu, unsigned int phy_cpu) { } | |
281 | ||
282 | #endif /* CONFIG_ZFCPDUMP || CONFIG_ZFCPDUMP_MODULE */ | |
411ed322 | 283 | |
08d07968 HC |
284 | static int cpu_stopped(int cpu) |
285 | { | |
286 | __u32 status; | |
287 | ||
288 | /* Check for stopped state */ | |
289 | if (signal_processor_ps(&status, 0, cpu, sigp_sense) == | |
290 | sigp_status_stored) { | |
291 | if (status & 0x40) | |
292 | return 1; | |
293 | } | |
294 | return 0; | |
295 | } | |
296 | ||
08d07968 HC |
297 | static int cpu_known(int cpu_id) |
298 | { | |
299 | int cpu; | |
300 | ||
301 | for_each_present_cpu(cpu) { | |
302 | if (__cpu_logical_map[cpu] == cpu_id) | |
303 | return 1; | |
304 | } | |
305 | return 0; | |
306 | } | |
307 | ||
308 | static int smp_rescan_cpus_sigp(cpumask_t avail) | |
309 | { | |
310 | int cpu_id, logical_cpu; | |
311 | ||
312 | logical_cpu = first_cpu(avail); | |
313 | if (logical_cpu == NR_CPUS) | |
314 | return 0; | |
315 | for (cpu_id = 0; cpu_id <= 65535; cpu_id++) { | |
316 | if (cpu_known(cpu_id)) | |
317 | continue; | |
318 | __cpu_logical_map[logical_cpu] = cpu_id; | |
c10fde0d | 319 | smp_cpu_polarization[logical_cpu] = POLARIZATION_UNKNWN; |
08d07968 HC |
320 | if (!cpu_stopped(logical_cpu)) |
321 | continue; | |
322 | cpu_set(logical_cpu, cpu_present_map); | |
323 | smp_cpu_state[logical_cpu] = CPU_STATE_CONFIGURED; | |
324 | logical_cpu = next_cpu(logical_cpu, avail); | |
325 | if (logical_cpu == NR_CPUS) | |
326 | break; | |
327 | } | |
328 | return 0; | |
329 | } | |
330 | ||
48483b32 | 331 | static int smp_rescan_cpus_sclp(cpumask_t avail) |
08d07968 HC |
332 | { |
333 | struct sclp_cpu_info *info; | |
334 | int cpu_id, logical_cpu, cpu; | |
335 | int rc; | |
336 | ||
337 | logical_cpu = first_cpu(avail); | |
338 | if (logical_cpu == NR_CPUS) | |
339 | return 0; | |
48483b32 | 340 | info = kmalloc(sizeof(*info), GFP_KERNEL); |
08d07968 HC |
341 | if (!info) |
342 | return -ENOMEM; | |
343 | rc = sclp_get_cpu_info(info); | |
344 | if (rc) | |
345 | goto out; | |
346 | for (cpu = 0; cpu < info->combined; cpu++) { | |
347 | if (info->has_cpu_type && info->cpu[cpu].type != smp_cpu_type) | |
348 | continue; | |
349 | cpu_id = info->cpu[cpu].address; | |
350 | if (cpu_known(cpu_id)) | |
351 | continue; | |
352 | __cpu_logical_map[logical_cpu] = cpu_id; | |
c10fde0d | 353 | smp_cpu_polarization[logical_cpu] = POLARIZATION_UNKNWN; |
08d07968 HC |
354 | cpu_set(logical_cpu, cpu_present_map); |
355 | if (cpu >= info->configured) | |
356 | smp_cpu_state[logical_cpu] = CPU_STATE_STANDBY; | |
357 | else | |
358 | smp_cpu_state[logical_cpu] = CPU_STATE_CONFIGURED; | |
359 | logical_cpu = next_cpu(logical_cpu, avail); | |
360 | if (logical_cpu == NR_CPUS) | |
361 | break; | |
362 | } | |
363 | out: | |
48483b32 | 364 | kfree(info); |
08d07968 HC |
365 | return rc; |
366 | } | |
367 | ||
1e489518 | 368 | static int __smp_rescan_cpus(void) |
08d07968 HC |
369 | { |
370 | cpumask_t avail; | |
371 | ||
48483b32 | 372 | cpus_xor(avail, cpu_possible_map, cpu_present_map); |
08d07968 HC |
373 | if (smp_use_sigp_detection) |
374 | return smp_rescan_cpus_sigp(avail); | |
375 | else | |
376 | return smp_rescan_cpus_sclp(avail); | |
1da177e4 LT |
377 | } |
378 | ||
48483b32 HC |
379 | static void __init smp_detect_cpus(void) |
380 | { | |
381 | unsigned int cpu, c_cpus, s_cpus; | |
382 | struct sclp_cpu_info *info; | |
383 | u16 boot_cpu_addr, cpu_addr; | |
384 | ||
385 | c_cpus = 1; | |
386 | s_cpus = 0; | |
387 | boot_cpu_addr = S390_lowcore.cpu_data.cpu_addr; | |
388 | info = kmalloc(sizeof(*info), GFP_KERNEL); | |
389 | if (!info) | |
390 | panic("smp_detect_cpus failed to allocate memory\n"); | |
391 | /* Use sigp detection algorithm if sclp doesn't work. */ | |
392 | if (sclp_get_cpu_info(info)) { | |
393 | smp_use_sigp_detection = 1; | |
394 | for (cpu = 0; cpu <= 65535; cpu++) { | |
395 | if (cpu == boot_cpu_addr) | |
396 | continue; | |
397 | __cpu_logical_map[CPU_INIT_NO] = cpu; | |
398 | if (!cpu_stopped(CPU_INIT_NO)) | |
399 | continue; | |
400 | smp_get_save_area(c_cpus, cpu); | |
401 | c_cpus++; | |
402 | } | |
403 | goto out; | |
404 | } | |
405 | ||
406 | if (info->has_cpu_type) { | |
407 | for (cpu = 0; cpu < info->combined; cpu++) { | |
408 | if (info->cpu[cpu].address == boot_cpu_addr) { | |
409 | smp_cpu_type = info->cpu[cpu].type; | |
410 | break; | |
411 | } | |
412 | } | |
413 | } | |
414 | ||
415 | for (cpu = 0; cpu < info->combined; cpu++) { | |
416 | if (info->has_cpu_type && info->cpu[cpu].type != smp_cpu_type) | |
417 | continue; | |
418 | cpu_addr = info->cpu[cpu].address; | |
419 | if (cpu_addr == boot_cpu_addr) | |
420 | continue; | |
421 | __cpu_logical_map[CPU_INIT_NO] = cpu_addr; | |
422 | if (!cpu_stopped(CPU_INIT_NO)) { | |
423 | s_cpus++; | |
424 | continue; | |
425 | } | |
426 | smp_get_save_area(c_cpus, cpu_addr); | |
427 | c_cpus++; | |
428 | } | |
429 | out: | |
430 | kfree(info); | |
395d31d4 | 431 | pr_info("%d configured CPUs, %d standby CPUs\n", c_cpus, s_cpus); |
9d40d2e3 | 432 | get_online_cpus(); |
1e489518 | 433 | __smp_rescan_cpus(); |
9d40d2e3 | 434 | put_online_cpus(); |
48483b32 HC |
435 | } |
436 | ||
1da177e4 | 437 | /* |
39ce010d | 438 | * Activate a secondary processor. |
1da177e4 | 439 | */ |
ea1f4eec | 440 | int __cpuinit start_secondary(void *cpuvoid) |
1da177e4 | 441 | { |
39ce010d HC |
442 | /* Setup the cpu */ |
443 | cpu_init(); | |
5bfb5d69 | 444 | preempt_disable(); |
d54853ef | 445 | /* Enable TOD clock interrupts on the secondary cpu. */ |
39ce010d | 446 | init_cpu_timer(); |
d54853ef | 447 | /* Enable cpu timer interrupts on the secondary cpu. */ |
39ce010d | 448 | init_cpu_vtimer(); |
1da177e4 | 449 | /* Enable pfault pseudo page faults on this cpu. */ |
29b08d2b HC |
450 | pfault_init(); |
451 | ||
e545a614 MS |
452 | /* call cpu notifiers */ |
453 | notify_cpu_starting(smp_processor_id()); | |
1da177e4 | 454 | /* Mark this cpu as online */ |
ca9fc75a | 455 | ipi_call_lock(); |
1da177e4 | 456 | cpu_set(smp_processor_id(), cpu_online_map); |
ca9fc75a | 457 | ipi_call_unlock(); |
1da177e4 LT |
458 | /* Switch on interrupts */ |
459 | local_irq_enable(); | |
39ce010d HC |
460 | /* Print info about this processor */ |
461 | print_cpu_info(&S390_lowcore.cpu_data); | |
462 | /* cpu_idle will call schedule for us */ | |
463 | cpu_idle(); | |
464 | return 0; | |
1da177e4 LT |
465 | } |
466 | ||
467 | static void __init smp_create_idle(unsigned int cpu) | |
468 | { | |
469 | struct task_struct *p; | |
470 | ||
471 | /* | |
472 | * don't care about the psw and regs settings since we'll never | |
473 | * reschedule the forked task. | |
474 | */ | |
475 | p = fork_idle(cpu); | |
476 | if (IS_ERR(p)) | |
477 | panic("failed fork for CPU %u: %li", cpu, PTR_ERR(p)); | |
478 | current_set[cpu] = p; | |
479 | } | |
480 | ||
1cb6bb4b HC |
481 | static int __cpuinit smp_alloc_lowcore(int cpu) |
482 | { | |
483 | unsigned long async_stack, panic_stack; | |
484 | struct _lowcore *lowcore; | |
485 | int lc_order; | |
486 | ||
487 | lc_order = sizeof(long) == 8 ? 1 : 0; | |
488 | lowcore = (void *) __get_free_pages(GFP_KERNEL | GFP_DMA, lc_order); | |
489 | if (!lowcore) | |
490 | return -ENOMEM; | |
491 | async_stack = __get_free_pages(GFP_KERNEL, ASYNC_ORDER); | |
1cb6bb4b | 492 | panic_stack = __get_free_page(GFP_KERNEL); |
591bb4f6 HC |
493 | if (!panic_stack || !async_stack) |
494 | goto out; | |
98c7b388 HC |
495 | memcpy(lowcore, &S390_lowcore, 512); |
496 | memset((char *)lowcore + 512, 0, sizeof(*lowcore) - 512); | |
1cb6bb4b HC |
497 | lowcore->async_stack = async_stack + ASYNC_SIZE; |
498 | lowcore->panic_stack = panic_stack + PAGE_SIZE; | |
499 | ||
500 | #ifndef CONFIG_64BIT | |
501 | if (MACHINE_HAS_IEEE) { | |
502 | unsigned long save_area; | |
503 | ||
504 | save_area = get_zeroed_page(GFP_KERNEL); | |
505 | if (!save_area) | |
33b1d09e | 506 | goto out; |
1cb6bb4b HC |
507 | lowcore->extended_save_area_addr = (u32) save_area; |
508 | } | |
509 | #endif | |
510 | lowcore_ptr[cpu] = lowcore; | |
511 | return 0; | |
512 | ||
591bb4f6 | 513 | out: |
33b1d09e | 514 | free_page(panic_stack); |
1cb6bb4b | 515 | free_pages(async_stack, ASYNC_ORDER); |
1cb6bb4b HC |
516 | free_pages((unsigned long) lowcore, lc_order); |
517 | return -ENOMEM; | |
518 | } | |
519 | ||
520 | #ifdef CONFIG_HOTPLUG_CPU | |
521 | static void smp_free_lowcore(int cpu) | |
522 | { | |
523 | struct _lowcore *lowcore; | |
524 | int lc_order; | |
525 | ||
526 | lc_order = sizeof(long) == 8 ? 1 : 0; | |
527 | lowcore = lowcore_ptr[cpu]; | |
528 | #ifndef CONFIG_64BIT | |
529 | if (MACHINE_HAS_IEEE) | |
530 | free_page((unsigned long) lowcore->extended_save_area_addr); | |
531 | #endif | |
532 | free_page(lowcore->panic_stack - PAGE_SIZE); | |
533 | free_pages(lowcore->async_stack - ASYNC_SIZE, ASYNC_ORDER); | |
534 | free_pages((unsigned long) lowcore, lc_order); | |
535 | lowcore_ptr[cpu] = NULL; | |
536 | } | |
537 | #endif /* CONFIG_HOTPLUG_CPU */ | |
538 | ||
1da177e4 | 539 | /* Upping and downing of CPUs */ |
1cb6bb4b | 540 | int __cpuinit __cpu_up(unsigned int cpu) |
1da177e4 LT |
541 | { |
542 | struct task_struct *idle; | |
39ce010d | 543 | struct _lowcore *cpu_lowcore; |
1da177e4 | 544 | struct stack_frame *sf; |
39ce010d | 545 | sigp_ccode ccode; |
1da177e4 | 546 | |
08d07968 HC |
547 | if (smp_cpu_state[cpu] != CPU_STATE_CONFIGURED) |
548 | return -EIO; | |
1cb6bb4b HC |
549 | if (smp_alloc_lowcore(cpu)) |
550 | return -ENOMEM; | |
1da177e4 LT |
551 | |
552 | ccode = signal_processor_p((__u32)(unsigned long)(lowcore_ptr[cpu]), | |
553 | cpu, sigp_set_prefix); | |
395d31d4 | 554 | if (ccode) |
1da177e4 | 555 | return -EIO; |
1da177e4 LT |
556 | |
557 | idle = current_set[cpu]; | |
39ce010d | 558 | cpu_lowcore = lowcore_ptr[cpu]; |
1da177e4 | 559 | cpu_lowcore->kernel_stack = (unsigned long) |
39ce010d | 560 | task_stack_page(idle) + THREAD_SIZE; |
1cb6bb4b | 561 | cpu_lowcore->thread_info = (unsigned long) task_thread_info(idle); |
1da177e4 LT |
562 | sf = (struct stack_frame *) (cpu_lowcore->kernel_stack |
563 | - sizeof(struct pt_regs) | |
564 | - sizeof(struct stack_frame)); | |
565 | memset(sf, 0, sizeof(struct stack_frame)); | |
566 | sf->gprs[9] = (unsigned long) sf; | |
567 | cpu_lowcore->save_area[15] = (unsigned long) sf; | |
24d3e210 | 568 | __ctl_store(cpu_lowcore->cregs_save_area, 0, 15); |
94c12cc7 MS |
569 | asm volatile( |
570 | " stam 0,15,0(%0)" | |
571 | : : "a" (&cpu_lowcore->access_regs_save_area) : "memory"); | |
1da177e4 | 572 | cpu_lowcore->percpu_offset = __per_cpu_offset[cpu]; |
39ce010d HC |
573 | cpu_lowcore->current_task = (unsigned long) idle; |
574 | cpu_lowcore->cpu_data.cpu_nr = cpu; | |
591bb4f6 HC |
575 | cpu_lowcore->kernel_asce = S390_lowcore.kernel_asce; |
576 | cpu_lowcore->ipl_device = S390_lowcore.ipl_device; | |
1da177e4 | 577 | eieio(); |
699ff13f | 578 | |
39ce010d | 579 | while (signal_processor(cpu, sigp_restart) == sigp_busy) |
699ff13f | 580 | udelay(10); |
1da177e4 LT |
581 | |
582 | while (!cpu_online(cpu)) | |
583 | cpu_relax(); | |
584 | return 0; | |
585 | } | |
586 | ||
48483b32 | 587 | static int __init setup_possible_cpus(char *s) |
255acee7 | 588 | { |
48483b32 | 589 | int pcpus, cpu; |
255acee7 | 590 | |
48483b32 HC |
591 | pcpus = simple_strtoul(s, NULL, 0); |
592 | cpu_possible_map = cpumask_of_cpu(0); | |
593 | for (cpu = 1; cpu < pcpus && cpu < NR_CPUS; cpu++) | |
255acee7 | 594 | cpu_set(cpu, cpu_possible_map); |
37a33026 HC |
595 | return 0; |
596 | } | |
597 | early_param("possible_cpus", setup_possible_cpus); | |
598 | ||
48483b32 HC |
599 | #ifdef CONFIG_HOTPLUG_CPU |
600 | ||
39ce010d | 601 | int __cpu_disable(void) |
1da177e4 | 602 | { |
94c12cc7 | 603 | struct ec_creg_mask_parms cr_parms; |
f3705136 | 604 | int cpu = smp_processor_id(); |
1da177e4 | 605 | |
f3705136 | 606 | cpu_clear(cpu, cpu_online_map); |
1da177e4 | 607 | |
1da177e4 | 608 | /* Disable pfault pseudo page faults on this cpu. */ |
29b08d2b | 609 | pfault_fini(); |
1da177e4 | 610 | |
94c12cc7 MS |
611 | memset(&cr_parms.orvals, 0, sizeof(cr_parms.orvals)); |
612 | memset(&cr_parms.andvals, 0xff, sizeof(cr_parms.andvals)); | |
1da177e4 | 613 | |
94c12cc7 | 614 | /* disable all external interrupts */ |
1da177e4 | 615 | cr_parms.orvals[0] = 0; |
39ce010d HC |
616 | cr_parms.andvals[0] = ~(1 << 15 | 1 << 14 | 1 << 13 | 1 << 12 | |
617 | 1 << 11 | 1 << 10 | 1 << 6 | 1 << 4); | |
1da177e4 | 618 | /* disable all I/O interrupts */ |
1da177e4 | 619 | cr_parms.orvals[6] = 0; |
39ce010d HC |
620 | cr_parms.andvals[6] = ~(1 << 31 | 1 << 30 | 1 << 29 | 1 << 28 | |
621 | 1 << 27 | 1 << 26 | 1 << 25 | 1 << 24); | |
1da177e4 | 622 | /* disable most machine checks */ |
1da177e4 | 623 | cr_parms.orvals[14] = 0; |
39ce010d HC |
624 | cr_parms.andvals[14] = ~(1 << 28 | 1 << 27 | 1 << 26 | |
625 | 1 << 25 | 1 << 24); | |
94c12cc7 | 626 | |
1da177e4 LT |
627 | smp_ctl_bit_callback(&cr_parms); |
628 | ||
1da177e4 LT |
629 | return 0; |
630 | } | |
631 | ||
39ce010d | 632 | void __cpu_die(unsigned int cpu) |
1da177e4 LT |
633 | { |
634 | /* Wait until target cpu is down */ | |
635 | while (!smp_cpu_not_running(cpu)) | |
636 | cpu_relax(); | |
1cb6bb4b | 637 | smp_free_lowcore(cpu); |
395d31d4 | 638 | pr_info("Processor %d stopped\n", cpu); |
1da177e4 LT |
639 | } |
640 | ||
39ce010d | 641 | void cpu_die(void) |
1da177e4 LT |
642 | { |
643 | idle_task_exit(); | |
644 | signal_processor(smp_processor_id(), sigp_stop); | |
645 | BUG(); | |
39ce010d | 646 | for (;;); |
1da177e4 LT |
647 | } |
648 | ||
255acee7 HC |
649 | #endif /* CONFIG_HOTPLUG_CPU */ |
650 | ||
1da177e4 LT |
651 | void __init smp_prepare_cpus(unsigned int max_cpus) |
652 | { | |
591bb4f6 HC |
653 | #ifndef CONFIG_64BIT |
654 | unsigned long save_area = 0; | |
655 | #endif | |
656 | unsigned long async_stack, panic_stack; | |
657 | struct _lowcore *lowcore; | |
1da177e4 | 658 | unsigned int cpu; |
591bb4f6 | 659 | int lc_order; |
39ce010d | 660 | |
48483b32 HC |
661 | smp_detect_cpus(); |
662 | ||
39ce010d HC |
663 | /* request the 0x1201 emergency signal external interrupt */ |
664 | if (register_external_interrupt(0x1201, do_ext_call_interrupt) != 0) | |
665 | panic("Couldn't request external interrupt 0x1201"); | |
1da177e4 LT |
666 | print_cpu_info(&S390_lowcore.cpu_data); |
667 | ||
591bb4f6 HC |
668 | /* Reallocate current lowcore, but keep its contents. */ |
669 | lc_order = sizeof(long) == 8 ? 1 : 0; | |
670 | lowcore = (void *) __get_free_pages(GFP_KERNEL | GFP_DMA, lc_order); | |
671 | panic_stack = __get_free_page(GFP_KERNEL); | |
672 | async_stack = __get_free_pages(GFP_KERNEL, ASYNC_ORDER); | |
347a8dc3 | 673 | #ifndef CONFIG_64BIT |
77fa2245 | 674 | if (MACHINE_HAS_IEEE) |
591bb4f6 | 675 | save_area = get_zeroed_page(GFP_KERNEL); |
77fa2245 | 676 | #endif |
591bb4f6 HC |
677 | local_irq_disable(); |
678 | local_mcck_disable(); | |
679 | lowcore_ptr[smp_processor_id()] = lowcore; | |
680 | *lowcore = S390_lowcore; | |
681 | lowcore->panic_stack = panic_stack + PAGE_SIZE; | |
682 | lowcore->async_stack = async_stack + ASYNC_SIZE; | |
683 | #ifndef CONFIG_64BIT | |
684 | if (MACHINE_HAS_IEEE) | |
685 | lowcore->extended_save_area_addr = (u32) save_area; | |
686 | #endif | |
687 | set_prefix((u32)(unsigned long) lowcore); | |
688 | local_mcck_enable(); | |
689 | local_irq_enable(); | |
97db7fbf | 690 | for_each_possible_cpu(cpu) |
1da177e4 LT |
691 | if (cpu != smp_processor_id()) |
692 | smp_create_idle(cpu); | |
693 | } | |
694 | ||
ea1f4eec | 695 | void __init smp_prepare_boot_cpu(void) |
1da177e4 LT |
696 | { |
697 | BUG_ON(smp_processor_id() != 0); | |
698 | ||
48483b32 HC |
699 | current_thread_info()->cpu = 0; |
700 | cpu_set(0, cpu_present_map); | |
1da177e4 | 701 | cpu_set(0, cpu_online_map); |
1da177e4 LT |
702 | S390_lowcore.percpu_offset = __per_cpu_offset[0]; |
703 | current_set[0] = current; | |
08d07968 | 704 | smp_cpu_state[0] = CPU_STATE_CONFIGURED; |
c10fde0d | 705 | smp_cpu_polarization[0] = POLARIZATION_UNKNWN; |
1da177e4 LT |
706 | } |
707 | ||
ea1f4eec | 708 | void __init smp_cpus_done(unsigned int max_cpus) |
1da177e4 | 709 | { |
1da177e4 LT |
710 | } |
711 | ||
712 | /* | |
713 | * the frequency of the profiling timer can be changed | |
714 | * by writing a multiplier value into /proc/profile. | |
715 | * | |
716 | * usually you want to run this on all CPUs ;) | |
717 | */ | |
718 | int setup_profiling_timer(unsigned int multiplier) | |
719 | { | |
39ce010d | 720 | return 0; |
1da177e4 LT |
721 | } |
722 | ||
08d07968 | 723 | #ifdef CONFIG_HOTPLUG_CPU |
4a0b2b4d AK |
724 | static ssize_t cpu_configure_show(struct sys_device *dev, |
725 | struct sysdev_attribute *attr, char *buf) | |
08d07968 HC |
726 | { |
727 | ssize_t count; | |
728 | ||
729 | mutex_lock(&smp_cpu_state_mutex); | |
730 | count = sprintf(buf, "%d\n", smp_cpu_state[dev->id]); | |
731 | mutex_unlock(&smp_cpu_state_mutex); | |
732 | return count; | |
733 | } | |
734 | ||
4a0b2b4d AK |
735 | static ssize_t cpu_configure_store(struct sys_device *dev, |
736 | struct sysdev_attribute *attr, | |
737 | const char *buf, size_t count) | |
08d07968 HC |
738 | { |
739 | int cpu = dev->id; | |
740 | int val, rc; | |
741 | char delim; | |
742 | ||
743 | if (sscanf(buf, "%d %c", &val, &delim) != 1) | |
744 | return -EINVAL; | |
745 | if (val != 0 && val != 1) | |
746 | return -EINVAL; | |
747 | ||
9d40d2e3 | 748 | get_online_cpus(); |
0b18d318 | 749 | mutex_lock(&smp_cpu_state_mutex); |
08d07968 HC |
750 | rc = -EBUSY; |
751 | if (cpu_online(cpu)) | |
752 | goto out; | |
753 | rc = 0; | |
754 | switch (val) { | |
755 | case 0: | |
756 | if (smp_cpu_state[cpu] == CPU_STATE_CONFIGURED) { | |
757 | rc = sclp_cpu_deconfigure(__cpu_logical_map[cpu]); | |
c10fde0d | 758 | if (!rc) { |
08d07968 | 759 | smp_cpu_state[cpu] = CPU_STATE_STANDBY; |
c10fde0d HC |
760 | smp_cpu_polarization[cpu] = POLARIZATION_UNKNWN; |
761 | } | |
08d07968 HC |
762 | } |
763 | break; | |
764 | case 1: | |
765 | if (smp_cpu_state[cpu] == CPU_STATE_STANDBY) { | |
766 | rc = sclp_cpu_configure(__cpu_logical_map[cpu]); | |
c10fde0d | 767 | if (!rc) { |
08d07968 | 768 | smp_cpu_state[cpu] = CPU_STATE_CONFIGURED; |
c10fde0d HC |
769 | smp_cpu_polarization[cpu] = POLARIZATION_UNKNWN; |
770 | } | |
08d07968 HC |
771 | } |
772 | break; | |
773 | default: | |
774 | break; | |
775 | } | |
776 | out: | |
08d07968 | 777 | mutex_unlock(&smp_cpu_state_mutex); |
0b18d318 | 778 | put_online_cpus(); |
08d07968 HC |
779 | return rc ? rc : count; |
780 | } | |
781 | static SYSDEV_ATTR(configure, 0644, cpu_configure_show, cpu_configure_store); | |
782 | #endif /* CONFIG_HOTPLUG_CPU */ | |
783 | ||
4a0b2b4d AK |
784 | static ssize_t cpu_polarization_show(struct sys_device *dev, |
785 | struct sysdev_attribute *attr, char *buf) | |
c10fde0d HC |
786 | { |
787 | int cpu = dev->id; | |
788 | ssize_t count; | |
789 | ||
790 | mutex_lock(&smp_cpu_state_mutex); | |
791 | switch (smp_cpu_polarization[cpu]) { | |
792 | case POLARIZATION_HRZ: | |
793 | count = sprintf(buf, "horizontal\n"); | |
794 | break; | |
795 | case POLARIZATION_VL: | |
796 | count = sprintf(buf, "vertical:low\n"); | |
797 | break; | |
798 | case POLARIZATION_VM: | |
799 | count = sprintf(buf, "vertical:medium\n"); | |
800 | break; | |
801 | case POLARIZATION_VH: | |
802 | count = sprintf(buf, "vertical:high\n"); | |
803 | break; | |
804 | default: | |
805 | count = sprintf(buf, "unknown\n"); | |
806 | break; | |
807 | } | |
808 | mutex_unlock(&smp_cpu_state_mutex); | |
809 | return count; | |
810 | } | |
811 | static SYSDEV_ATTR(polarization, 0444, cpu_polarization_show, NULL); | |
812 | ||
4a0b2b4d AK |
813 | static ssize_t show_cpu_address(struct sys_device *dev, |
814 | struct sysdev_attribute *attr, char *buf) | |
08d07968 HC |
815 | { |
816 | return sprintf(buf, "%d\n", __cpu_logical_map[dev->id]); | |
817 | } | |
818 | static SYSDEV_ATTR(address, 0444, show_cpu_address, NULL); | |
819 | ||
820 | ||
821 | static struct attribute *cpu_common_attrs[] = { | |
822 | #ifdef CONFIG_HOTPLUG_CPU | |
823 | &attr_configure.attr, | |
824 | #endif | |
825 | &attr_address.attr, | |
c10fde0d | 826 | &attr_polarization.attr, |
08d07968 HC |
827 | NULL, |
828 | }; | |
829 | ||
830 | static struct attribute_group cpu_common_attr_group = { | |
831 | .attrs = cpu_common_attrs, | |
832 | }; | |
1da177e4 | 833 | |
4a0b2b4d AK |
834 | static ssize_t show_capability(struct sys_device *dev, |
835 | struct sysdev_attribute *attr, char *buf) | |
2fc2d1e9 HC |
836 | { |
837 | unsigned int capability; | |
838 | int rc; | |
839 | ||
840 | rc = get_cpu_capability(&capability); | |
841 | if (rc) | |
842 | return rc; | |
843 | return sprintf(buf, "%u\n", capability); | |
844 | } | |
845 | static SYSDEV_ATTR(capability, 0444, show_capability, NULL); | |
846 | ||
4a0b2b4d AK |
847 | static ssize_t show_idle_count(struct sys_device *dev, |
848 | struct sysdev_attribute *attr, char *buf) | |
fae8b22d HC |
849 | { |
850 | struct s390_idle_data *idle; | |
851 | unsigned long long idle_count; | |
852 | ||
853 | idle = &per_cpu(s390_idle, dev->id); | |
854 | spin_lock_irq(&idle->lock); | |
855 | idle_count = idle->idle_count; | |
856 | spin_unlock_irq(&idle->lock); | |
857 | return sprintf(buf, "%llu\n", idle_count); | |
858 | } | |
859 | static SYSDEV_ATTR(idle_count, 0444, show_idle_count, NULL); | |
860 | ||
4a0b2b4d AK |
861 | static ssize_t show_idle_time(struct sys_device *dev, |
862 | struct sysdev_attribute *attr, char *buf) | |
fae8b22d HC |
863 | { |
864 | struct s390_idle_data *idle; | |
865 | unsigned long long new_time; | |
866 | ||
867 | idle = &per_cpu(s390_idle, dev->id); | |
868 | spin_lock_irq(&idle->lock); | |
869 | if (idle->in_idle) { | |
870 | new_time = get_clock(); | |
871 | idle->idle_time += new_time - idle->idle_enter; | |
872 | idle->idle_enter = new_time; | |
873 | } | |
874 | new_time = idle->idle_time; | |
875 | spin_unlock_irq(&idle->lock); | |
69d39d66 | 876 | return sprintf(buf, "%llu\n", new_time >> 12); |
fae8b22d | 877 | } |
69d39d66 | 878 | static SYSDEV_ATTR(idle_time_us, 0444, show_idle_time, NULL); |
fae8b22d | 879 | |
08d07968 | 880 | static struct attribute *cpu_online_attrs[] = { |
fae8b22d HC |
881 | &attr_capability.attr, |
882 | &attr_idle_count.attr, | |
69d39d66 | 883 | &attr_idle_time_us.attr, |
fae8b22d HC |
884 | NULL, |
885 | }; | |
886 | ||
08d07968 HC |
887 | static struct attribute_group cpu_online_attr_group = { |
888 | .attrs = cpu_online_attrs, | |
fae8b22d HC |
889 | }; |
890 | ||
2fc2d1e9 HC |
891 | static int __cpuinit smp_cpu_notify(struct notifier_block *self, |
892 | unsigned long action, void *hcpu) | |
893 | { | |
894 | unsigned int cpu = (unsigned int)(long)hcpu; | |
895 | struct cpu *c = &per_cpu(cpu_devices, cpu); | |
896 | struct sys_device *s = &c->sysdev; | |
fae8b22d | 897 | struct s390_idle_data *idle; |
2fc2d1e9 HC |
898 | |
899 | switch (action) { | |
900 | case CPU_ONLINE: | |
8bb78442 | 901 | case CPU_ONLINE_FROZEN: |
fae8b22d HC |
902 | idle = &per_cpu(s390_idle, cpu); |
903 | spin_lock_irq(&idle->lock); | |
904 | idle->idle_enter = 0; | |
905 | idle->idle_time = 0; | |
906 | idle->idle_count = 0; | |
907 | spin_unlock_irq(&idle->lock); | |
08d07968 | 908 | if (sysfs_create_group(&s->kobj, &cpu_online_attr_group)) |
2fc2d1e9 HC |
909 | return NOTIFY_BAD; |
910 | break; | |
911 | case CPU_DEAD: | |
8bb78442 | 912 | case CPU_DEAD_FROZEN: |
08d07968 | 913 | sysfs_remove_group(&s->kobj, &cpu_online_attr_group); |
2fc2d1e9 HC |
914 | break; |
915 | } | |
916 | return NOTIFY_OK; | |
917 | } | |
918 | ||
919 | static struct notifier_block __cpuinitdata smp_cpu_nb = { | |
39ce010d | 920 | .notifier_call = smp_cpu_notify, |
2fc2d1e9 HC |
921 | }; |
922 | ||
2bc89b5e | 923 | static int __devinit smp_add_present_cpu(int cpu) |
08d07968 HC |
924 | { |
925 | struct cpu *c = &per_cpu(cpu_devices, cpu); | |
926 | struct sys_device *s = &c->sysdev; | |
927 | int rc; | |
928 | ||
929 | c->hotpluggable = 1; | |
930 | rc = register_cpu(c, cpu); | |
931 | if (rc) | |
932 | goto out; | |
933 | rc = sysfs_create_group(&s->kobj, &cpu_common_attr_group); | |
934 | if (rc) | |
935 | goto out_cpu; | |
936 | if (!cpu_online(cpu)) | |
937 | goto out; | |
938 | rc = sysfs_create_group(&s->kobj, &cpu_online_attr_group); | |
939 | if (!rc) | |
940 | return 0; | |
941 | sysfs_remove_group(&s->kobj, &cpu_common_attr_group); | |
942 | out_cpu: | |
943 | #ifdef CONFIG_HOTPLUG_CPU | |
944 | unregister_cpu(c); | |
945 | #endif | |
946 | out: | |
947 | return rc; | |
948 | } | |
949 | ||
950 | #ifdef CONFIG_HOTPLUG_CPU | |
1e489518 | 951 | |
67060d9c | 952 | int __ref smp_rescan_cpus(void) |
08d07968 HC |
953 | { |
954 | cpumask_t newcpus; | |
955 | int cpu; | |
956 | int rc; | |
957 | ||
9d40d2e3 | 958 | get_online_cpus(); |
0b18d318 | 959 | mutex_lock(&smp_cpu_state_mutex); |
08d07968 | 960 | newcpus = cpu_present_map; |
1e489518 | 961 | rc = __smp_rescan_cpus(); |
08d07968 HC |
962 | if (rc) |
963 | goto out; | |
964 | cpus_andnot(newcpus, cpu_present_map, newcpus); | |
965 | for_each_cpu_mask(cpu, newcpus) { | |
966 | rc = smp_add_present_cpu(cpu); | |
967 | if (rc) | |
968 | cpu_clear(cpu, cpu_present_map); | |
969 | } | |
970 | rc = 0; | |
971 | out: | |
08d07968 | 972 | mutex_unlock(&smp_cpu_state_mutex); |
0b18d318 | 973 | put_online_cpus(); |
c10fde0d HC |
974 | if (!cpus_empty(newcpus)) |
975 | topology_schedule_update(); | |
1e489518 HC |
976 | return rc; |
977 | } | |
978 | ||
da5aae70 | 979 | static ssize_t __ref rescan_store(struct sysdev_class *class, const char *buf, |
1e489518 HC |
980 | size_t count) |
981 | { | |
982 | int rc; | |
983 | ||
984 | rc = smp_rescan_cpus(); | |
08d07968 HC |
985 | return rc ? rc : count; |
986 | } | |
da5aae70 | 987 | static SYSDEV_CLASS_ATTR(rescan, 0200, NULL, rescan_store); |
08d07968 HC |
988 | #endif /* CONFIG_HOTPLUG_CPU */ |
989 | ||
da5aae70 | 990 | static ssize_t dispatching_show(struct sysdev_class *class, char *buf) |
c10fde0d HC |
991 | { |
992 | ssize_t count; | |
993 | ||
994 | mutex_lock(&smp_cpu_state_mutex); | |
995 | count = sprintf(buf, "%d\n", cpu_management); | |
996 | mutex_unlock(&smp_cpu_state_mutex); | |
997 | return count; | |
998 | } | |
999 | ||
da5aae70 HC |
1000 | static ssize_t dispatching_store(struct sysdev_class *dev, const char *buf, |
1001 | size_t count) | |
c10fde0d HC |
1002 | { |
1003 | int val, rc; | |
1004 | char delim; | |
1005 | ||
1006 | if (sscanf(buf, "%d %c", &val, &delim) != 1) | |
1007 | return -EINVAL; | |
1008 | if (val != 0 && val != 1) | |
1009 | return -EINVAL; | |
1010 | rc = 0; | |
c10fde0d | 1011 | get_online_cpus(); |
0b18d318 | 1012 | mutex_lock(&smp_cpu_state_mutex); |
c10fde0d HC |
1013 | if (cpu_management == val) |
1014 | goto out; | |
1015 | rc = topology_set_cpu_management(val); | |
1016 | if (!rc) | |
1017 | cpu_management = val; | |
1018 | out: | |
c10fde0d | 1019 | mutex_unlock(&smp_cpu_state_mutex); |
0b18d318 | 1020 | put_online_cpus(); |
c10fde0d HC |
1021 | return rc ? rc : count; |
1022 | } | |
da5aae70 HC |
1023 | static SYSDEV_CLASS_ATTR(dispatching, 0644, dispatching_show, |
1024 | dispatching_store); | |
c10fde0d | 1025 | |
1da177e4 LT |
1026 | static int __init topology_init(void) |
1027 | { | |
1028 | int cpu; | |
fae8b22d | 1029 | int rc; |
2fc2d1e9 HC |
1030 | |
1031 | register_cpu_notifier(&smp_cpu_nb); | |
1da177e4 | 1032 | |
08d07968 | 1033 | #ifdef CONFIG_HOTPLUG_CPU |
da5aae70 | 1034 | rc = sysdev_class_create_file(&cpu_sysdev_class, &attr_rescan); |
08d07968 HC |
1035 | if (rc) |
1036 | return rc; | |
1037 | #endif | |
da5aae70 | 1038 | rc = sysdev_class_create_file(&cpu_sysdev_class, &attr_dispatching); |
c10fde0d HC |
1039 | if (rc) |
1040 | return rc; | |
08d07968 HC |
1041 | for_each_present_cpu(cpu) { |
1042 | rc = smp_add_present_cpu(cpu); | |
fae8b22d HC |
1043 | if (rc) |
1044 | return rc; | |
1da177e4 LT |
1045 | } |
1046 | return 0; | |
1047 | } | |
1da177e4 | 1048 | subsys_initcall(topology_init); |