Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
8b646bd7 | 2 | * SMP related functions |
1da177e4 | 3 | * |
a53c8fab | 4 | * Copyright IBM Corp. 1999, 2012 |
8b646bd7 MS |
5 | * Author(s): Denis Joseph Barrow, |
6 | * Martin Schwidefsky <schwidefsky@de.ibm.com>, | |
7 | * Heiko Carstens <heiko.carstens@de.ibm.com>, | |
1da177e4 | 8 | * |
39ce010d | 9 | * based on other smp stuff by |
1da177e4 LT |
10 | * (c) 1995 Alan Cox, CymruNET Ltd <alan@cymru.net> |
11 | * (c) 1998 Ingo Molnar | |
12 | * | |
8b646bd7 MS |
13 | * The code outside of smp.c uses logical cpu numbers, only smp.c does |
14 | * the translation of logical to physical cpu ids. All new code that | |
15 | * operates on physical cpu numbers needs to go into smp.c. | |
1da177e4 LT |
16 | */ |
17 | ||
395d31d4 MS |
18 | #define KMSG_COMPONENT "cpu" |
19 | #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt | |
20 | ||
f230886b | 21 | #include <linux/workqueue.h> |
1da177e4 LT |
22 | #include <linux/module.h> |
23 | #include <linux/init.h> | |
1da177e4 | 24 | #include <linux/mm.h> |
4e950f6f | 25 | #include <linux/err.h> |
1da177e4 LT |
26 | #include <linux/spinlock.h> |
27 | #include <linux/kernel_stat.h> | |
1da177e4 | 28 | #include <linux/delay.h> |
1da177e4 | 29 | #include <linux/interrupt.h> |
3324e60a | 30 | #include <linux/irqflags.h> |
1da177e4 | 31 | #include <linux/cpu.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
60a0c68d | 33 | #include <linux/crash_dump.h> |
cbb870c8 | 34 | #include <asm/asm-offsets.h> |
1e3cab2f HC |
35 | #include <asm/switch_to.h> |
36 | #include <asm/facility.h> | |
46b05d26 | 37 | #include <asm/ipl.h> |
2b67fc46 | 38 | #include <asm/setup.h> |
1da177e4 | 39 | #include <asm/irq.h> |
1da177e4 | 40 | #include <asm/tlbflush.h> |
27f6b416 | 41 | #include <asm/vtimer.h> |
411ed322 | 42 | #include <asm/lowcore.h> |
08d07968 | 43 | #include <asm/sclp.h> |
c742b31c | 44 | #include <asm/vdso.h> |
3ab121ab | 45 | #include <asm/debug.h> |
4857d4bb | 46 | #include <asm/os_info.h> |
a9ae32c3 | 47 | #include <asm/sigp.h> |
a806170e | 48 | #include "entry.h" |
1da177e4 | 49 | |
8b646bd7 MS |
50 | enum { |
51 | ec_schedule = 0, | |
8b646bd7 MS |
52 | ec_call_function_single, |
53 | ec_stop_cpu, | |
54 | }; | |
08d07968 | 55 | |
8b646bd7 | 56 | enum { |
08d07968 HC |
57 | CPU_STATE_STANDBY, |
58 | CPU_STATE_CONFIGURED, | |
59 | }; | |
60 | ||
8b646bd7 MS |
61 | struct pcpu { |
62 | struct cpu cpu; | |
8b646bd7 MS |
63 | struct _lowcore *lowcore; /* lowcore page(s) for the cpu */ |
64 | unsigned long async_stack; /* async stack for the cpu */ | |
65 | unsigned long panic_stack; /* panic stack for the cpu */ | |
66 | unsigned long ec_mask; /* bit mask for ec_xxx functions */ | |
67 | int state; /* physical cpu state */ | |
50ab9a9a | 68 | int polarization; /* physical polarization */ |
8b646bd7 MS |
69 | u16 address; /* physical cpu address */ |
70 | }; | |
71 | ||
72 | static u8 boot_cpu_type; | |
73 | static u16 boot_cpu_address; | |
74 | static struct pcpu pcpu_devices[NR_CPUS]; | |
75 | ||
50ab9a9a HC |
76 | /* |
77 | * The smp_cpu_state_mutex must be held when changing the state or polarization | |
78 | * member of a pcpu data structure within the pcpu_devices arreay. | |
79 | */ | |
dbd70fb4 | 80 | DEFINE_MUTEX(smp_cpu_state_mutex); |
08d07968 | 81 | |
8b646bd7 MS |
82 | /* |
83 | * Signal processor helper functions. | |
84 | */ | |
85 | static inline int __pcpu_sigp(u16 addr, u8 order, u32 parm, u32 *status) | |
86 | { | |
87 | register unsigned int reg1 asm ("1") = parm; | |
88 | int cc; | |
08d07968 | 89 | |
8b646bd7 MS |
90 | asm volatile( |
91 | " sigp %1,%2,0(%3)\n" | |
92 | " ipm %0\n" | |
93 | " srl %0,28\n" | |
94 | : "=d" (cc), "+d" (reg1) : "d" (addr), "a" (order) : "cc"); | |
95 | if (status && cc == 1) | |
96 | *status = reg1; | |
97 | return cc; | |
98 | } | |
1da177e4 | 99 | |
8b646bd7 | 100 | static inline int __pcpu_sigp_relax(u16 addr, u8 order, u32 parm, u32 *status) |
5c0b912e | 101 | { |
8b646bd7 | 102 | int cc; |
5c0b912e | 103 | |
8b646bd7 | 104 | while (1) { |
c5e3acd6 | 105 | cc = __pcpu_sigp(addr, order, parm, NULL); |
a9ae32c3 | 106 | if (cc != SIGP_CC_BUSY) |
8b646bd7 MS |
107 | return cc; |
108 | cpu_relax(); | |
5c0b912e | 109 | } |
5c0b912e HC |
110 | } |
111 | ||
8b646bd7 | 112 | static int pcpu_sigp_retry(struct pcpu *pcpu, u8 order, u32 parm) |
a93b8ec1 | 113 | { |
8b646bd7 MS |
114 | int cc, retry; |
115 | ||
116 | for (retry = 0; ; retry++) { | |
c5e3acd6 | 117 | cc = __pcpu_sigp(pcpu->address, order, parm, NULL); |
a9ae32c3 | 118 | if (cc != SIGP_CC_BUSY) |
8b646bd7 MS |
119 | break; |
120 | if (retry >= 3) | |
121 | udelay(10); | |
122 | } | |
123 | return cc; | |
124 | } | |
125 | ||
126 | static inline int pcpu_stopped(struct pcpu *pcpu) | |
127 | { | |
41459d36 | 128 | u32 uninitialized_var(status); |
c5e3acd6 | 129 | |
a9ae32c3 | 130 | if (__pcpu_sigp(pcpu->address, SIGP_SENSE, |
c5e3acd6 | 131 | 0, &status) != SIGP_CC_STATUS_STORED) |
8b646bd7 | 132 | return 0; |
c5e3acd6 | 133 | return !!(status & (SIGP_STATUS_CHECK_STOP|SIGP_STATUS_STOPPED)); |
8b646bd7 MS |
134 | } |
135 | ||
136 | static inline int pcpu_running(struct pcpu *pcpu) | |
a93b8ec1 | 137 | { |
a9ae32c3 | 138 | if (__pcpu_sigp(pcpu->address, SIGP_SENSE_RUNNING, |
c5e3acd6 | 139 | 0, NULL) != SIGP_CC_STATUS_STORED) |
8b646bd7 | 140 | return 1; |
524b24ad HC |
141 | /* Status stored condition code is equivalent to cpu not running. */ |
142 | return 0; | |
a93b8ec1 HC |
143 | } |
144 | ||
1943f53c | 145 | /* |
8b646bd7 | 146 | * Find struct pcpu by cpu address. |
1943f53c | 147 | */ |
8b646bd7 | 148 | static struct pcpu *pcpu_find_address(const struct cpumask *mask, int address) |
1943f53c MH |
149 | { |
150 | int cpu; | |
151 | ||
8b646bd7 MS |
152 | for_each_cpu(cpu, mask) |
153 | if (pcpu_devices[cpu].address == address) | |
154 | return pcpu_devices + cpu; | |
155 | return NULL; | |
156 | } | |
157 | ||
158 | static void pcpu_ec_call(struct pcpu *pcpu, int ec_bit) | |
159 | { | |
160 | int order; | |
161 | ||
162 | set_bit(ec_bit, &pcpu->ec_mask); | |
163 | order = pcpu_running(pcpu) ? | |
a9ae32c3 | 164 | SIGP_EXTERNAL_CALL : SIGP_EMERGENCY_SIGNAL; |
8b646bd7 MS |
165 | pcpu_sigp_retry(pcpu, order, 0); |
166 | } | |
167 | ||
e2741f17 | 168 | static int pcpu_alloc_lowcore(struct pcpu *pcpu, int cpu) |
8b646bd7 MS |
169 | { |
170 | struct _lowcore *lc; | |
171 | ||
172 | if (pcpu != &pcpu_devices[0]) { | |
173 | pcpu->lowcore = (struct _lowcore *) | |
174 | __get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER); | |
175 | pcpu->async_stack = __get_free_pages(GFP_KERNEL, ASYNC_ORDER); | |
176 | pcpu->panic_stack = __get_free_page(GFP_KERNEL); | |
177 | if (!pcpu->lowcore || !pcpu->panic_stack || !pcpu->async_stack) | |
178 | goto out; | |
1943f53c | 179 | } |
8b646bd7 MS |
180 | lc = pcpu->lowcore; |
181 | memcpy(lc, &S390_lowcore, 512); | |
182 | memset((char *) lc + 512, 0, sizeof(*lc) - 512); | |
dc7ee00d MS |
183 | lc->async_stack = pcpu->async_stack + ASYNC_SIZE |
184 | - STACK_FRAME_OVERHEAD - sizeof(struct pt_regs); | |
185 | lc->panic_stack = pcpu->panic_stack + PAGE_SIZE | |
186 | - STACK_FRAME_OVERHEAD - sizeof(struct pt_regs); | |
8b646bd7 MS |
187 | lc->cpu_nr = cpu; |
188 | #ifndef CONFIG_64BIT | |
189 | if (MACHINE_HAS_IEEE) { | |
190 | lc->extended_save_area_addr = get_zeroed_page(GFP_KERNEL); | |
191 | if (!lc->extended_save_area_addr) | |
192 | goto out; | |
193 | } | |
194 | #else | |
195 | if (vdso_alloc_per_cpu(lc)) | |
196 | goto out; | |
197 | #endif | |
198 | lowcore_ptr[cpu] = lc; | |
a9ae32c3 | 199 | pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, (u32)(unsigned long) lc); |
8b646bd7 MS |
200 | return 0; |
201 | out: | |
202 | if (pcpu != &pcpu_devices[0]) { | |
203 | free_page(pcpu->panic_stack); | |
204 | free_pages(pcpu->async_stack, ASYNC_ORDER); | |
205 | free_pages((unsigned long) pcpu->lowcore, LC_ORDER); | |
206 | } | |
207 | return -ENOMEM; | |
1943f53c MH |
208 | } |
209 | ||
9d0f46af HC |
210 | #ifdef CONFIG_HOTPLUG_CPU |
211 | ||
8b646bd7 | 212 | static void pcpu_free_lowcore(struct pcpu *pcpu) |
2c2df118 | 213 | { |
a9ae32c3 | 214 | pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, 0); |
8b646bd7 MS |
215 | lowcore_ptr[pcpu - pcpu_devices] = NULL; |
216 | #ifndef CONFIG_64BIT | |
217 | if (MACHINE_HAS_IEEE) { | |
218 | struct _lowcore *lc = pcpu->lowcore; | |
219 | ||
220 | free_page((unsigned long) lc->extended_save_area_addr); | |
221 | lc->extended_save_area_addr = 0; | |
222 | } | |
223 | #else | |
224 | vdso_free_per_cpu(pcpu->lowcore); | |
225 | #endif | |
226 | if (pcpu != &pcpu_devices[0]) { | |
227 | free_page(pcpu->panic_stack); | |
228 | free_pages(pcpu->async_stack, ASYNC_ORDER); | |
229 | free_pages((unsigned long) pcpu->lowcore, LC_ORDER); | |
230 | } | |
231 | } | |
232 | ||
9d0f46af HC |
233 | #endif /* CONFIG_HOTPLUG_CPU */ |
234 | ||
8b646bd7 MS |
235 | static void pcpu_prepare_secondary(struct pcpu *pcpu, int cpu) |
236 | { | |
237 | struct _lowcore *lc = pcpu->lowcore; | |
238 | ||
239 | atomic_inc(&init_mm.context.attach_count); | |
240 | lc->cpu_nr = cpu; | |
241 | lc->percpu_offset = __per_cpu_offset[cpu]; | |
242 | lc->kernel_asce = S390_lowcore.kernel_asce; | |
243 | lc->machine_flags = S390_lowcore.machine_flags; | |
244 | lc->ftrace_func = S390_lowcore.ftrace_func; | |
245 | lc->user_timer = lc->system_timer = lc->steal_timer = 0; | |
246 | __ctl_store(lc->cregs_save_area, 0, 15); | |
247 | save_access_regs((unsigned int *) lc->access_regs_save_area); | |
248 | memcpy(lc->stfle_fac_list, S390_lowcore.stfle_fac_list, | |
249 | MAX_FACILITY_BIT/8); | |
250 | } | |
251 | ||
252 | static void pcpu_attach_task(struct pcpu *pcpu, struct task_struct *tsk) | |
253 | { | |
254 | struct _lowcore *lc = pcpu->lowcore; | |
255 | struct thread_info *ti = task_thread_info(tsk); | |
256 | ||
dc7ee00d MS |
257 | lc->kernel_stack = (unsigned long) task_stack_page(tsk) |
258 | + THREAD_SIZE - STACK_FRAME_OVERHEAD - sizeof(struct pt_regs); | |
8b646bd7 MS |
259 | lc->thread_info = (unsigned long) task_thread_info(tsk); |
260 | lc->current_task = (unsigned long) tsk; | |
261 | lc->user_timer = ti->user_timer; | |
262 | lc->system_timer = ti->system_timer; | |
263 | lc->steal_timer = 0; | |
264 | } | |
265 | ||
266 | static void pcpu_start_fn(struct pcpu *pcpu, void (*func)(void *), void *data) | |
267 | { | |
268 | struct _lowcore *lc = pcpu->lowcore; | |
269 | ||
270 | lc->restart_stack = lc->kernel_stack; | |
271 | lc->restart_fn = (unsigned long) func; | |
272 | lc->restart_data = (unsigned long) data; | |
273 | lc->restart_source = -1UL; | |
a9ae32c3 | 274 | pcpu_sigp_retry(pcpu, SIGP_RESTART, 0); |
8b646bd7 MS |
275 | } |
276 | ||
277 | /* | |
278 | * Call function via PSW restart on pcpu and stop the current cpu. | |
279 | */ | |
280 | static void pcpu_delegate(struct pcpu *pcpu, void (*func)(void *), | |
281 | void *data, unsigned long stack) | |
282 | { | |
061da3df | 283 | struct _lowcore *lc = lowcore_ptr[pcpu - pcpu_devices]; |
fbe76568 | 284 | unsigned long source_cpu = stap(); |
8b646bd7 | 285 | |
e258d719 | 286 | __load_psw_mask(PSW_KERNEL_BITS); |
fbe76568 | 287 | if (pcpu->address == source_cpu) |
8b646bd7 MS |
288 | func(data); /* should not return */ |
289 | /* Stop target cpu (if func returns this stops the current cpu). */ | |
a9ae32c3 | 290 | pcpu_sigp_retry(pcpu, SIGP_STOP, 0); |
8b646bd7 | 291 | /* Restart func on the target cpu and stop the current cpu. */ |
fbe76568 HC |
292 | mem_assign_absolute(lc->restart_stack, stack); |
293 | mem_assign_absolute(lc->restart_fn, (unsigned long) func); | |
294 | mem_assign_absolute(lc->restart_data, (unsigned long) data); | |
295 | mem_assign_absolute(lc->restart_source, source_cpu); | |
8b646bd7 | 296 | asm volatile( |
eb546195 | 297 | "0: sigp 0,%0,%2 # sigp restart to target cpu\n" |
8b646bd7 | 298 | " brc 2,0b # busy, try again\n" |
eb546195 | 299 | "1: sigp 0,%1,%3 # sigp stop to current cpu\n" |
8b646bd7 | 300 | " brc 2,1b # busy, try again\n" |
fbe76568 | 301 | : : "d" (pcpu->address), "d" (source_cpu), |
eb546195 HC |
302 | "K" (SIGP_RESTART), "K" (SIGP_STOP) |
303 | : "0", "1", "cc"); | |
8b646bd7 MS |
304 | for (;;) ; |
305 | } | |
306 | ||
307 | /* | |
308 | * Call function on an online CPU. | |
309 | */ | |
310 | void smp_call_online_cpu(void (*func)(void *), void *data) | |
311 | { | |
312 | struct pcpu *pcpu; | |
313 | ||
314 | /* Use the current cpu if it is online. */ | |
315 | pcpu = pcpu_find_address(cpu_online_mask, stap()); | |
316 | if (!pcpu) | |
317 | /* Use the first online cpu. */ | |
318 | pcpu = pcpu_devices + cpumask_first(cpu_online_mask); | |
319 | pcpu_delegate(pcpu, func, data, (unsigned long) restart_stack); | |
320 | } | |
321 | ||
322 | /* | |
323 | * Call function on the ipl CPU. | |
324 | */ | |
325 | void smp_call_ipl_cpu(void (*func)(void *), void *data) | |
326 | { | |
c6da39f2 MH |
327 | pcpu_delegate(&pcpu_devices[0], func, data, |
328 | pcpu_devices->panic_stack + PAGE_SIZE); | |
8b646bd7 MS |
329 | } |
330 | ||
331 | int smp_find_processor_id(u16 address) | |
332 | { | |
333 | int cpu; | |
334 | ||
335 | for_each_present_cpu(cpu) | |
336 | if (pcpu_devices[cpu].address == address) | |
337 | return cpu; | |
338 | return -1; | |
2c2df118 HC |
339 | } |
340 | ||
8b646bd7 | 341 | int smp_vcpu_scheduled(int cpu) |
85ac7ca5 | 342 | { |
8b646bd7 MS |
343 | return pcpu_running(pcpu_devices + cpu); |
344 | } | |
345 | ||
346 | void smp_yield(void) | |
347 | { | |
348 | if (MACHINE_HAS_DIAG44) | |
349 | asm volatile("diag 0,0,0x44"); | |
2c2df118 HC |
350 | } |
351 | ||
8b646bd7 | 352 | void smp_yield_cpu(int cpu) |
85ac7ca5 | 353 | { |
8b646bd7 MS |
354 | if (MACHINE_HAS_DIAG9C) |
355 | asm volatile("diag %0,0,0x9c" | |
356 | : : "d" (pcpu_devices[cpu].address)); | |
357 | else if (MACHINE_HAS_DIAG44) | |
358 | asm volatile("diag 0,0,0x44"); | |
359 | } | |
360 | ||
361 | /* | |
362 | * Send cpus emergency shutdown signal. This gives the cpus the | |
363 | * opportunity to complete outstanding interrupts. | |
364 | */ | |
63df41d6 | 365 | static void smp_emergency_stop(cpumask_t *cpumask) |
8b646bd7 MS |
366 | { |
367 | u64 end; | |
368 | int cpu; | |
369 | ||
1aae0560 | 370 | end = get_tod_clock() + (1000000UL << 12); |
8b646bd7 MS |
371 | for_each_cpu(cpu, cpumask) { |
372 | struct pcpu *pcpu = pcpu_devices + cpu; | |
373 | set_bit(ec_stop_cpu, &pcpu->ec_mask); | |
a9ae32c3 HC |
374 | while (__pcpu_sigp(pcpu->address, SIGP_EMERGENCY_SIGNAL, |
375 | 0, NULL) == SIGP_CC_BUSY && | |
1aae0560 | 376 | get_tod_clock() < end) |
8b646bd7 MS |
377 | cpu_relax(); |
378 | } | |
1aae0560 | 379 | while (get_tod_clock() < end) { |
8b646bd7 MS |
380 | for_each_cpu(cpu, cpumask) |
381 | if (pcpu_stopped(pcpu_devices + cpu)) | |
382 | cpumask_clear_cpu(cpu, cpumask); | |
383 | if (cpumask_empty(cpumask)) | |
384 | break; | |
85ac7ca5 | 385 | cpu_relax(); |
8b646bd7 | 386 | } |
85ac7ca5 MS |
387 | } |
388 | ||
8b646bd7 MS |
389 | /* |
390 | * Stop all cpus but the current one. | |
391 | */ | |
677d7623 | 392 | void smp_send_stop(void) |
1da177e4 | 393 | { |
85ac7ca5 MS |
394 | cpumask_t cpumask; |
395 | int cpu; | |
1da177e4 | 396 | |
677d7623 | 397 | /* Disable all interrupts/machine checks */ |
e258d719 | 398 | __load_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT); |
3324e60a | 399 | trace_hardirqs_off(); |
1da177e4 | 400 | |
3ab121ab | 401 | debug_set_critical(); |
85ac7ca5 MS |
402 | cpumask_copy(&cpumask, cpu_online_mask); |
403 | cpumask_clear_cpu(smp_processor_id(), &cpumask); | |
404 | ||
8b646bd7 MS |
405 | if (oops_in_progress) |
406 | smp_emergency_stop(&cpumask); | |
1da177e4 | 407 | |
85ac7ca5 MS |
408 | /* stop all processors */ |
409 | for_each_cpu(cpu, &cpumask) { | |
8b646bd7 | 410 | struct pcpu *pcpu = pcpu_devices + cpu; |
a9ae32c3 | 411 | pcpu_sigp_retry(pcpu, SIGP_STOP, 0); |
8b646bd7 | 412 | while (!pcpu_stopped(pcpu)) |
c6b5b847 HC |
413 | cpu_relax(); |
414 | } | |
415 | } | |
416 | ||
8b646bd7 MS |
417 | /* |
418 | * Stop the current cpu. | |
419 | */ | |
420 | void smp_stop_cpu(void) | |
421 | { | |
a9ae32c3 | 422 | pcpu_sigp_retry(pcpu_devices + smp_processor_id(), SIGP_STOP, 0); |
8b646bd7 MS |
423 | for (;;) ; |
424 | } | |
425 | ||
1da177e4 LT |
426 | /* |
427 | * This is the main routine where commands issued by other | |
428 | * cpus are handled. | |
429 | */ | |
9acf73b7 | 430 | static void smp_handle_ext_call(void) |
1da177e4 | 431 | { |
39ce010d | 432 | unsigned long bits; |
1da177e4 | 433 | |
9acf73b7 HC |
434 | /* handle bit signal external calls */ |
435 | bits = xchg(&pcpu_devices[smp_processor_id()].ec_mask, 0); | |
85ac7ca5 MS |
436 | if (test_bit(ec_stop_cpu, &bits)) |
437 | smp_stop_cpu(); | |
184748cc PZ |
438 | if (test_bit(ec_schedule, &bits)) |
439 | scheduler_ipi(); | |
ca9fc75a HC |
440 | if (test_bit(ec_call_function_single, &bits)) |
441 | generic_smp_call_function_single_interrupt(); | |
9acf73b7 | 442 | } |
85ac7ca5 | 443 | |
9acf73b7 HC |
444 | static void do_ext_call_interrupt(struct ext_code ext_code, |
445 | unsigned int param32, unsigned long param64) | |
446 | { | |
447 | inc_irq_stat(ext_code.code == 0x1202 ? IRQEXT_EXC : IRQEXT_EMS); | |
448 | smp_handle_ext_call(); | |
1da177e4 LT |
449 | } |
450 | ||
630cd046 | 451 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
ca9fc75a HC |
452 | { |
453 | int cpu; | |
454 | ||
630cd046 | 455 | for_each_cpu(cpu, mask) |
b6ed49e0 | 456 | pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single); |
ca9fc75a HC |
457 | } |
458 | ||
459 | void arch_send_call_function_single_ipi(int cpu) | |
460 | { | |
8b646bd7 | 461 | pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single); |
ca9fc75a HC |
462 | } |
463 | ||
347a8dc3 | 464 | #ifndef CONFIG_64BIT |
1da177e4 LT |
465 | /* |
466 | * this function sends a 'purge tlb' signal to another CPU. | |
467 | */ | |
a806170e | 468 | static void smp_ptlb_callback(void *info) |
1da177e4 | 469 | { |
ba8a9229 | 470 | __tlb_flush_local(); |
1da177e4 LT |
471 | } |
472 | ||
473 | void smp_ptlb_all(void) | |
474 | { | |
15c8b6c1 | 475 | on_each_cpu(smp_ptlb_callback, NULL, 1); |
1da177e4 LT |
476 | } |
477 | EXPORT_SYMBOL(smp_ptlb_all); | |
347a8dc3 | 478 | #endif /* ! CONFIG_64BIT */ |
1da177e4 LT |
479 | |
480 | /* | |
481 | * this function sends a 'reschedule' IPI to another CPU. | |
482 | * it goes straight through and wastes no time serializing | |
483 | * anything. Worst case is that we lose a reschedule ... | |
484 | */ | |
485 | void smp_send_reschedule(int cpu) | |
486 | { | |
8b646bd7 | 487 | pcpu_ec_call(pcpu_devices + cpu, ec_schedule); |
1da177e4 LT |
488 | } |
489 | ||
490 | /* | |
491 | * parameter area for the set/clear control bit callbacks | |
492 | */ | |
94c12cc7 | 493 | struct ec_creg_mask_parms { |
8b646bd7 MS |
494 | unsigned long orval; |
495 | unsigned long andval; | |
496 | int cr; | |
94c12cc7 | 497 | }; |
1da177e4 LT |
498 | |
499 | /* | |
500 | * callback for setting/clearing control bits | |
501 | */ | |
39ce010d HC |
502 | static void smp_ctl_bit_callback(void *info) |
503 | { | |
94c12cc7 | 504 | struct ec_creg_mask_parms *pp = info; |
1da177e4 | 505 | unsigned long cregs[16]; |
39ce010d | 506 | |
94c12cc7 | 507 | __ctl_store(cregs, 0, 15); |
8b646bd7 | 508 | cregs[pp->cr] = (cregs[pp->cr] & pp->andval) | pp->orval; |
94c12cc7 | 509 | __ctl_load(cregs, 0, 15); |
1da177e4 LT |
510 | } |
511 | ||
512 | /* | |
513 | * Set a bit in a control register of all cpus | |
514 | */ | |
94c12cc7 MS |
515 | void smp_ctl_set_bit(int cr, int bit) |
516 | { | |
8b646bd7 | 517 | struct ec_creg_mask_parms parms = { 1UL << bit, -1UL, cr }; |
1da177e4 | 518 | |
15c8b6c1 | 519 | on_each_cpu(smp_ctl_bit_callback, &parms, 1); |
1da177e4 | 520 | } |
39ce010d | 521 | EXPORT_SYMBOL(smp_ctl_set_bit); |
1da177e4 LT |
522 | |
523 | /* | |
524 | * Clear a bit in a control register of all cpus | |
525 | */ | |
94c12cc7 MS |
526 | void smp_ctl_clear_bit(int cr, int bit) |
527 | { | |
8b646bd7 | 528 | struct ec_creg_mask_parms parms = { 0, ~(1UL << bit), cr }; |
1da177e4 | 529 | |
15c8b6c1 | 530 | on_each_cpu(smp_ctl_bit_callback, &parms, 1); |
1da177e4 | 531 | } |
39ce010d | 532 | EXPORT_SYMBOL(smp_ctl_clear_bit); |
1da177e4 | 533 | |
60a0c68d | 534 | #if defined(CONFIG_ZFCPDUMP) || defined(CONFIG_CRASH_DUMP) |
411ed322 | 535 | |
8b646bd7 | 536 | static void __init smp_get_save_area(int cpu, u16 address) |
411ed322 | 537 | { |
8b646bd7 MS |
538 | void *lc = pcpu_devices[0].lowcore; |
539 | struct save_area *save_area; | |
540 | ||
60a0c68d | 541 | if (is_kdump_kernel()) |
411ed322 | 542 | return; |
8b646bd7 MS |
543 | if (!OLDMEM_BASE && (address == boot_cpu_address || |
544 | ipl_info.type != IPL_TYPE_FCP_DUMP)) | |
545 | return; | |
58952942 | 546 | save_area = dump_save_area_create(cpu); |
8b646bd7 MS |
547 | if (!save_area) |
548 | panic("could not allocate memory for save area\n"); | |
8b646bd7 MS |
549 | #ifdef CONFIG_CRASH_DUMP |
550 | if (address == boot_cpu_address) { | |
551 | /* Copy the registers of the boot cpu. */ | |
552 | copy_oldmem_page(1, (void *) save_area, sizeof(*save_area), | |
553 | SAVE_AREA_BASE - PAGE_SIZE, 0); | |
554 | return; | |
555 | } | |
556 | #endif | |
557 | /* Get the registers of a non-boot cpu. */ | |
a9ae32c3 | 558 | __pcpu_sigp_relax(address, SIGP_STOP_AND_STORE_STATUS, 0, NULL); |
8b646bd7 | 559 | memcpy_real(save_area, lc + SAVE_AREA_BASE, sizeof(*save_area)); |
411ed322 MH |
560 | } |
561 | ||
8b646bd7 | 562 | int smp_store_status(int cpu) |
08d07968 | 563 | { |
8b646bd7 | 564 | struct pcpu *pcpu; |
08d07968 | 565 | |
8b646bd7 | 566 | pcpu = pcpu_devices + cpu; |
a9ae32c3 HC |
567 | if (__pcpu_sigp_relax(pcpu->address, SIGP_STOP_AND_STORE_STATUS, |
568 | 0, NULL) != SIGP_CC_ORDER_CODE_ACCEPTED) | |
8b646bd7 | 569 | return -EIO; |
08d07968 HC |
570 | return 0; |
571 | } | |
572 | ||
8b646bd7 | 573 | #else /* CONFIG_ZFCPDUMP || CONFIG_CRASH_DUMP */ |
08d07968 | 574 | |
8b646bd7 | 575 | static inline void smp_get_save_area(int cpu, u16 address) { } |
08d07968 | 576 | |
8b646bd7 | 577 | #endif /* CONFIG_ZFCPDUMP || CONFIG_CRASH_DUMP */ |
08d07968 | 578 | |
50ab9a9a HC |
579 | void smp_cpu_set_polarization(int cpu, int val) |
580 | { | |
581 | pcpu_devices[cpu].polarization = val; | |
582 | } | |
583 | ||
584 | int smp_cpu_get_polarization(int cpu) | |
585 | { | |
586 | return pcpu_devices[cpu].polarization; | |
587 | } | |
588 | ||
8b646bd7 | 589 | static struct sclp_cpu_info *smp_get_cpu_info(void) |
08d07968 | 590 | { |
8b646bd7 | 591 | static int use_sigp_detection; |
08d07968 | 592 | struct sclp_cpu_info *info; |
8b646bd7 MS |
593 | int address; |
594 | ||
595 | info = kzalloc(sizeof(*info), GFP_KERNEL); | |
596 | if (info && (use_sigp_detection || sclp_get_cpu_info(info))) { | |
597 | use_sigp_detection = 1; | |
598 | for (address = 0; address <= MAX_CPU_ADDRESS; address++) { | |
a9ae32c3 HC |
599 | if (__pcpu_sigp_relax(address, SIGP_SENSE, 0, NULL) == |
600 | SIGP_CC_NOT_OPERATIONAL) | |
8b646bd7 MS |
601 | continue; |
602 | info->cpu[info->configured].address = address; | |
603 | info->configured++; | |
604 | } | |
605 | info->combined = info->configured; | |
08d07968 | 606 | } |
8b646bd7 | 607 | return info; |
08d07968 HC |
608 | } |
609 | ||
e2741f17 | 610 | static int smp_add_present_cpu(int cpu); |
8b646bd7 | 611 | |
e2741f17 | 612 | static int __smp_rescan_cpus(struct sclp_cpu_info *info, int sysfs_add) |
08d07968 | 613 | { |
8b646bd7 | 614 | struct pcpu *pcpu; |
08d07968 | 615 | cpumask_t avail; |
8b646bd7 | 616 | int cpu, nr, i; |
08d07968 | 617 | |
8b646bd7 | 618 | nr = 0; |
0f1959f5 | 619 | cpumask_xor(&avail, cpu_possible_mask, cpu_present_mask); |
8b646bd7 MS |
620 | cpu = cpumask_first(&avail); |
621 | for (i = 0; (i < info->combined) && (cpu < nr_cpu_ids); i++) { | |
622 | if (info->has_cpu_type && info->cpu[i].type != boot_cpu_type) | |
623 | continue; | |
624 | if (pcpu_find_address(cpu_present_mask, info->cpu[i].address)) | |
625 | continue; | |
626 | pcpu = pcpu_devices + cpu; | |
627 | pcpu->address = info->cpu[i].address; | |
a4eeea4e | 628 | pcpu->state = (i >= info->configured) ? |
8b646bd7 | 629 | CPU_STATE_STANDBY : CPU_STATE_CONFIGURED; |
50ab9a9a | 630 | smp_cpu_set_polarization(cpu, POLARIZATION_UNKNOWN); |
8b646bd7 MS |
631 | set_cpu_present(cpu, true); |
632 | if (sysfs_add && smp_add_present_cpu(cpu) != 0) | |
633 | set_cpu_present(cpu, false); | |
634 | else | |
635 | nr++; | |
636 | cpu = cpumask_next(cpu, &avail); | |
637 | } | |
638 | return nr; | |
1da177e4 LT |
639 | } |
640 | ||
48483b32 HC |
641 | static void __init smp_detect_cpus(void) |
642 | { | |
643 | unsigned int cpu, c_cpus, s_cpus; | |
644 | struct sclp_cpu_info *info; | |
48483b32 | 645 | |
8b646bd7 | 646 | info = smp_get_cpu_info(); |
48483b32 HC |
647 | if (!info) |
648 | panic("smp_detect_cpus failed to allocate memory\n"); | |
48483b32 HC |
649 | if (info->has_cpu_type) { |
650 | for (cpu = 0; cpu < info->combined; cpu++) { | |
8b646bd7 MS |
651 | if (info->cpu[cpu].address != boot_cpu_address) |
652 | continue; | |
653 | /* The boot cpu dictates the cpu type. */ | |
654 | boot_cpu_type = info->cpu[cpu].type; | |
655 | break; | |
48483b32 HC |
656 | } |
657 | } | |
8b646bd7 | 658 | c_cpus = s_cpus = 0; |
48483b32 | 659 | for (cpu = 0; cpu < info->combined; cpu++) { |
8b646bd7 | 660 | if (info->has_cpu_type && info->cpu[cpu].type != boot_cpu_type) |
48483b32 | 661 | continue; |
8b646bd7 MS |
662 | if (cpu < info->configured) { |
663 | smp_get_save_area(c_cpus, info->cpu[cpu].address); | |
664 | c_cpus++; | |
665 | } else | |
48483b32 | 666 | s_cpus++; |
48483b32 | 667 | } |
395d31d4 | 668 | pr_info("%d configured CPUs, %d standby CPUs\n", c_cpus, s_cpus); |
9d40d2e3 | 669 | get_online_cpus(); |
8b646bd7 | 670 | __smp_rescan_cpus(info, 0); |
9d40d2e3 | 671 | put_online_cpus(); |
8b646bd7 | 672 | kfree(info); |
48483b32 HC |
673 | } |
674 | ||
1da177e4 | 675 | /* |
39ce010d | 676 | * Activate a secondary processor. |
1da177e4 | 677 | */ |
e2741f17 | 678 | static void smp_start_secondary(void *cpuvoid) |
1da177e4 | 679 | { |
1aae0560 | 680 | S390_lowcore.last_update_clock = get_tod_clock(); |
8b646bd7 MS |
681 | S390_lowcore.restart_stack = (unsigned long) restart_stack; |
682 | S390_lowcore.restart_fn = (unsigned long) do_restart; | |
683 | S390_lowcore.restart_data = 0; | |
684 | S390_lowcore.restart_source = -1UL; | |
685 | restore_access_regs(S390_lowcore.access_regs_save_area); | |
686 | __ctl_load(S390_lowcore.cregs_save_area, 0, 15); | |
e258d719 | 687 | __load_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT); |
39ce010d | 688 | cpu_init(); |
5bfb5d69 | 689 | preempt_disable(); |
39ce010d | 690 | init_cpu_timer(); |
39ce010d | 691 | init_cpu_vtimer(); |
29b08d2b | 692 | pfault_init(); |
e545a614 | 693 | notify_cpu_starting(smp_processor_id()); |
0f1959f5 | 694 | set_cpu_online(smp_processor_id(), true); |
93f3b2ee | 695 | inc_irq_stat(CPU_RST); |
1da177e4 | 696 | local_irq_enable(); |
52c00659 | 697 | cpu_startup_entry(CPUHP_ONLINE); |
1da177e4 LT |
698 | } |
699 | ||
1da177e4 | 700 | /* Upping and downing of CPUs */ |
e2741f17 | 701 | int __cpu_up(unsigned int cpu, struct task_struct *tidle) |
1da177e4 | 702 | { |
8b646bd7 MS |
703 | struct pcpu *pcpu; |
704 | int rc; | |
1da177e4 | 705 | |
8b646bd7 MS |
706 | pcpu = pcpu_devices + cpu; |
707 | if (pcpu->state != CPU_STATE_CONFIGURED) | |
08d07968 | 708 | return -EIO; |
a9ae32c3 HC |
709 | if (pcpu_sigp_retry(pcpu, SIGP_INITIAL_CPU_RESET, 0) != |
710 | SIGP_CC_ORDER_CODE_ACCEPTED) | |
08d07968 | 711 | return -EIO; |
e80e7813 | 712 | |
8b646bd7 MS |
713 | rc = pcpu_alloc_lowcore(pcpu, cpu); |
714 | if (rc) | |
715 | return rc; | |
716 | pcpu_prepare_secondary(pcpu, cpu); | |
e80e7813 | 717 | pcpu_attach_task(pcpu, tidle); |
8b646bd7 | 718 | pcpu_start_fn(pcpu, smp_start_secondary, NULL); |
1da177e4 LT |
719 | while (!cpu_online(cpu)) |
720 | cpu_relax(); | |
721 | return 0; | |
722 | } | |
723 | ||
48483b32 | 724 | static int __init setup_possible_cpus(char *s) |
255acee7 | 725 | { |
8b646bd7 | 726 | int max, cpu; |
255acee7 | 727 | |
8b646bd7 MS |
728 | if (kstrtoint(s, 0, &max) < 0) |
729 | return 0; | |
88e01285 | 730 | init_cpu_possible(cpumask_of(0)); |
8b646bd7 | 731 | for (cpu = 1; cpu < max && cpu < nr_cpu_ids; cpu++) |
def6cfb7 | 732 | set_cpu_possible(cpu, true); |
37a33026 HC |
733 | return 0; |
734 | } | |
735 | early_param("possible_cpus", setup_possible_cpus); | |
736 | ||
48483b32 HC |
737 | #ifdef CONFIG_HOTPLUG_CPU |
738 | ||
39ce010d | 739 | int __cpu_disable(void) |
1da177e4 | 740 | { |
8b646bd7 | 741 | unsigned long cregs[16]; |
1da177e4 | 742 | |
9acf73b7 HC |
743 | /* Handle possible pending IPIs */ |
744 | smp_handle_ext_call(); | |
8b646bd7 MS |
745 | set_cpu_online(smp_processor_id(), false); |
746 | /* Disable pseudo page faults on this cpu. */ | |
29b08d2b | 747 | pfault_fini(); |
8b646bd7 MS |
748 | /* Disable interrupt sources via control register. */ |
749 | __ctl_store(cregs, 0, 15); | |
750 | cregs[0] &= ~0x0000ee70UL; /* disable all external interrupts */ | |
751 | cregs[6] &= ~0xff000000UL; /* disable all I/O interrupts */ | |
752 | cregs[14] &= ~0x1f000000UL; /* disable most machine checks */ | |
753 | __ctl_load(cregs, 0, 15); | |
1da177e4 LT |
754 | return 0; |
755 | } | |
756 | ||
39ce010d | 757 | void __cpu_die(unsigned int cpu) |
1da177e4 | 758 | { |
8b646bd7 MS |
759 | struct pcpu *pcpu; |
760 | ||
1da177e4 | 761 | /* Wait until target cpu is down */ |
8b646bd7 MS |
762 | pcpu = pcpu_devices + cpu; |
763 | while (!pcpu_stopped(pcpu)) | |
1da177e4 | 764 | cpu_relax(); |
8b646bd7 | 765 | pcpu_free_lowcore(pcpu); |
050eef36 | 766 | atomic_dec(&init_mm.context.attach_count); |
1da177e4 LT |
767 | } |
768 | ||
b456d94a | 769 | void __noreturn cpu_die(void) |
1da177e4 LT |
770 | { |
771 | idle_task_exit(); | |
a9ae32c3 | 772 | pcpu_sigp_retry(pcpu_devices + smp_processor_id(), SIGP_STOP, 0); |
8b646bd7 | 773 | for (;;) ; |
1da177e4 LT |
774 | } |
775 | ||
255acee7 HC |
776 | #endif /* CONFIG_HOTPLUG_CPU */ |
777 | ||
1da177e4 LT |
778 | void __init smp_prepare_cpus(unsigned int max_cpus) |
779 | { | |
39ce010d HC |
780 | /* request the 0x1201 emergency signal external interrupt */ |
781 | if (register_external_interrupt(0x1201, do_ext_call_interrupt) != 0) | |
782 | panic("Couldn't request external interrupt 0x1201"); | |
d98e19cc MS |
783 | /* request the 0x1202 external call external interrupt */ |
784 | if (register_external_interrupt(0x1202, do_ext_call_interrupt) != 0) | |
785 | panic("Couldn't request external interrupt 0x1202"); | |
8b646bd7 | 786 | smp_detect_cpus(); |
1da177e4 LT |
787 | } |
788 | ||
ea1f4eec | 789 | void __init smp_prepare_boot_cpu(void) |
1da177e4 | 790 | { |
8b646bd7 MS |
791 | struct pcpu *pcpu = pcpu_devices; |
792 | ||
793 | boot_cpu_address = stap(); | |
8b646bd7 MS |
794 | pcpu->state = CPU_STATE_CONFIGURED; |
795 | pcpu->address = boot_cpu_address; | |
796 | pcpu->lowcore = (struct _lowcore *)(unsigned long) store_prefix(); | |
dc7ee00d MS |
797 | pcpu->async_stack = S390_lowcore.async_stack - ASYNC_SIZE |
798 | + STACK_FRAME_OVERHEAD + sizeof(struct pt_regs); | |
799 | pcpu->panic_stack = S390_lowcore.panic_stack - PAGE_SIZE | |
800 | + STACK_FRAME_OVERHEAD + sizeof(struct pt_regs); | |
1da177e4 | 801 | S390_lowcore.percpu_offset = __per_cpu_offset[0]; |
50ab9a9a | 802 | smp_cpu_set_polarization(0, POLARIZATION_UNKNOWN); |
8b646bd7 MS |
803 | set_cpu_present(0, true); |
804 | set_cpu_online(0, true); | |
1da177e4 LT |
805 | } |
806 | ||
ea1f4eec | 807 | void __init smp_cpus_done(unsigned int max_cpus) |
1da177e4 | 808 | { |
1da177e4 LT |
809 | } |
810 | ||
02beaccc HC |
811 | void __init smp_setup_processor_id(void) |
812 | { | |
813 | S390_lowcore.cpu_nr = 0; | |
02beaccc HC |
814 | } |
815 | ||
1da177e4 LT |
816 | /* |
817 | * the frequency of the profiling timer can be changed | |
818 | * by writing a multiplier value into /proc/profile. | |
819 | * | |
820 | * usually you want to run this on all CPUs ;) | |
821 | */ | |
822 | int setup_profiling_timer(unsigned int multiplier) | |
823 | { | |
39ce010d | 824 | return 0; |
1da177e4 LT |
825 | } |
826 | ||
08d07968 | 827 | #ifdef CONFIG_HOTPLUG_CPU |
8a25a2fd | 828 | static ssize_t cpu_configure_show(struct device *dev, |
8b646bd7 | 829 | struct device_attribute *attr, char *buf) |
08d07968 HC |
830 | { |
831 | ssize_t count; | |
832 | ||
833 | mutex_lock(&smp_cpu_state_mutex); | |
8b646bd7 | 834 | count = sprintf(buf, "%d\n", pcpu_devices[dev->id].state); |
08d07968 HC |
835 | mutex_unlock(&smp_cpu_state_mutex); |
836 | return count; | |
837 | } | |
838 | ||
8a25a2fd | 839 | static ssize_t cpu_configure_store(struct device *dev, |
8b646bd7 MS |
840 | struct device_attribute *attr, |
841 | const char *buf, size_t count) | |
08d07968 | 842 | { |
8b646bd7 MS |
843 | struct pcpu *pcpu; |
844 | int cpu, val, rc; | |
08d07968 HC |
845 | char delim; |
846 | ||
847 | if (sscanf(buf, "%d %c", &val, &delim) != 1) | |
848 | return -EINVAL; | |
849 | if (val != 0 && val != 1) | |
850 | return -EINVAL; | |
9d40d2e3 | 851 | get_online_cpus(); |
0b18d318 | 852 | mutex_lock(&smp_cpu_state_mutex); |
08d07968 | 853 | rc = -EBUSY; |
2c2df118 | 854 | /* disallow configuration changes of online cpus and cpu 0 */ |
8b646bd7 | 855 | cpu = dev->id; |
2c2df118 | 856 | if (cpu_online(cpu) || cpu == 0) |
08d07968 | 857 | goto out; |
8b646bd7 | 858 | pcpu = pcpu_devices + cpu; |
08d07968 HC |
859 | rc = 0; |
860 | switch (val) { | |
861 | case 0: | |
8b646bd7 MS |
862 | if (pcpu->state != CPU_STATE_CONFIGURED) |
863 | break; | |
864 | rc = sclp_cpu_deconfigure(pcpu->address); | |
865 | if (rc) | |
866 | break; | |
867 | pcpu->state = CPU_STATE_STANDBY; | |
50ab9a9a | 868 | smp_cpu_set_polarization(cpu, POLARIZATION_UNKNOWN); |
8b646bd7 | 869 | topology_expect_change(); |
08d07968 HC |
870 | break; |
871 | case 1: | |
8b646bd7 MS |
872 | if (pcpu->state != CPU_STATE_STANDBY) |
873 | break; | |
874 | rc = sclp_cpu_configure(pcpu->address); | |
875 | if (rc) | |
876 | break; | |
877 | pcpu->state = CPU_STATE_CONFIGURED; | |
50ab9a9a | 878 | smp_cpu_set_polarization(cpu, POLARIZATION_UNKNOWN); |
8b646bd7 | 879 | topology_expect_change(); |
08d07968 HC |
880 | break; |
881 | default: | |
882 | break; | |
883 | } | |
884 | out: | |
08d07968 | 885 | mutex_unlock(&smp_cpu_state_mutex); |
0b18d318 | 886 | put_online_cpus(); |
08d07968 HC |
887 | return rc ? rc : count; |
888 | } | |
8a25a2fd | 889 | static DEVICE_ATTR(configure, 0644, cpu_configure_show, cpu_configure_store); |
08d07968 HC |
890 | #endif /* CONFIG_HOTPLUG_CPU */ |
891 | ||
8a25a2fd KS |
892 | static ssize_t show_cpu_address(struct device *dev, |
893 | struct device_attribute *attr, char *buf) | |
08d07968 | 894 | { |
8b646bd7 | 895 | return sprintf(buf, "%d\n", pcpu_devices[dev->id].address); |
08d07968 | 896 | } |
8a25a2fd | 897 | static DEVICE_ATTR(address, 0444, show_cpu_address, NULL); |
08d07968 | 898 | |
08d07968 HC |
899 | static struct attribute *cpu_common_attrs[] = { |
900 | #ifdef CONFIG_HOTPLUG_CPU | |
8a25a2fd | 901 | &dev_attr_configure.attr, |
08d07968 | 902 | #endif |
8a25a2fd | 903 | &dev_attr_address.attr, |
08d07968 HC |
904 | NULL, |
905 | }; | |
906 | ||
907 | static struct attribute_group cpu_common_attr_group = { | |
908 | .attrs = cpu_common_attrs, | |
909 | }; | |
1da177e4 | 910 | |
8a25a2fd KS |
911 | static ssize_t show_idle_count(struct device *dev, |
912 | struct device_attribute *attr, char *buf) | |
fae8b22d | 913 | { |
4c1051e3 | 914 | struct s390_idle_data *idle = &per_cpu(s390_idle, dev->id); |
fae8b22d | 915 | unsigned long long idle_count; |
e98bbaaf | 916 | unsigned int sequence; |
fae8b22d | 917 | |
4c1051e3 MS |
918 | do { |
919 | sequence = ACCESS_ONCE(idle->sequence); | |
920 | idle_count = ACCESS_ONCE(idle->idle_count); | |
27f6b416 | 921 | if (ACCESS_ONCE(idle->clock_idle_enter)) |
4c1051e3 | 922 | idle_count++; |
4560e7c3 | 923 | } while ((sequence & 1) || (ACCESS_ONCE(idle->sequence) != sequence)); |
fae8b22d HC |
924 | return sprintf(buf, "%llu\n", idle_count); |
925 | } | |
8a25a2fd | 926 | static DEVICE_ATTR(idle_count, 0444, show_idle_count, NULL); |
fae8b22d | 927 | |
8a25a2fd KS |
928 | static ssize_t show_idle_time(struct device *dev, |
929 | struct device_attribute *attr, char *buf) | |
fae8b22d | 930 | { |
4c1051e3 MS |
931 | struct s390_idle_data *idle = &per_cpu(s390_idle, dev->id); |
932 | unsigned long long now, idle_time, idle_enter, idle_exit; | |
e98bbaaf | 933 | unsigned int sequence; |
fae8b22d | 934 | |
4c1051e3 | 935 | do { |
1aae0560 | 936 | now = get_tod_clock(); |
4c1051e3 MS |
937 | sequence = ACCESS_ONCE(idle->sequence); |
938 | idle_time = ACCESS_ONCE(idle->idle_time); | |
27f6b416 MS |
939 | idle_enter = ACCESS_ONCE(idle->clock_idle_enter); |
940 | idle_exit = ACCESS_ONCE(idle->clock_idle_exit); | |
4560e7c3 | 941 | } while ((sequence & 1) || (ACCESS_ONCE(idle->sequence) != sequence)); |
4c1051e3 | 942 | idle_time += idle_enter ? ((idle_exit ? : now) - idle_enter) : 0; |
6f430924 | 943 | return sprintf(buf, "%llu\n", idle_time >> 12); |
fae8b22d | 944 | } |
8a25a2fd | 945 | static DEVICE_ATTR(idle_time_us, 0444, show_idle_time, NULL); |
fae8b22d | 946 | |
08d07968 | 947 | static struct attribute *cpu_online_attrs[] = { |
8a25a2fd KS |
948 | &dev_attr_idle_count.attr, |
949 | &dev_attr_idle_time_us.attr, | |
fae8b22d HC |
950 | NULL, |
951 | }; | |
952 | ||
08d07968 HC |
953 | static struct attribute_group cpu_online_attr_group = { |
954 | .attrs = cpu_online_attrs, | |
fae8b22d HC |
955 | }; |
956 | ||
e2741f17 PG |
957 | static int smp_cpu_notify(struct notifier_block *self, unsigned long action, |
958 | void *hcpu) | |
2fc2d1e9 HC |
959 | { |
960 | unsigned int cpu = (unsigned int)(long)hcpu; | |
8b646bd7 | 961 | struct cpu *c = &pcpu_devices[cpu].cpu; |
8a25a2fd | 962 | struct device *s = &c->dev; |
d882ba69 | 963 | int err = 0; |
2fc2d1e9 | 964 | |
1c725922 | 965 | switch (action & ~CPU_TASKS_FROZEN) { |
2fc2d1e9 | 966 | case CPU_ONLINE: |
d882ba69 | 967 | err = sysfs_create_group(&s->kobj, &cpu_online_attr_group); |
2fc2d1e9 HC |
968 | break; |
969 | case CPU_DEAD: | |
08d07968 | 970 | sysfs_remove_group(&s->kobj, &cpu_online_attr_group); |
2fc2d1e9 HC |
971 | break; |
972 | } | |
d882ba69 | 973 | return notifier_from_errno(err); |
2fc2d1e9 HC |
974 | } |
975 | ||
e2741f17 | 976 | static int smp_add_present_cpu(int cpu) |
08d07968 | 977 | { |
8b646bd7 | 978 | struct cpu *c = &pcpu_devices[cpu].cpu; |
8a25a2fd | 979 | struct device *s = &c->dev; |
08d07968 HC |
980 | int rc; |
981 | ||
982 | c->hotpluggable = 1; | |
983 | rc = register_cpu(c, cpu); | |
984 | if (rc) | |
985 | goto out; | |
986 | rc = sysfs_create_group(&s->kobj, &cpu_common_attr_group); | |
987 | if (rc) | |
988 | goto out_cpu; | |
83a24e32 HC |
989 | if (cpu_online(cpu)) { |
990 | rc = sysfs_create_group(&s->kobj, &cpu_online_attr_group); | |
991 | if (rc) | |
992 | goto out_online; | |
993 | } | |
994 | rc = topology_cpu_init(c); | |
995 | if (rc) | |
996 | goto out_topology; | |
997 | return 0; | |
998 | ||
999 | out_topology: | |
1000 | if (cpu_online(cpu)) | |
1001 | sysfs_remove_group(&s->kobj, &cpu_online_attr_group); | |
1002 | out_online: | |
08d07968 HC |
1003 | sysfs_remove_group(&s->kobj, &cpu_common_attr_group); |
1004 | out_cpu: | |
1005 | #ifdef CONFIG_HOTPLUG_CPU | |
1006 | unregister_cpu(c); | |
1007 | #endif | |
1008 | out: | |
1009 | return rc; | |
1010 | } | |
1011 | ||
1012 | #ifdef CONFIG_HOTPLUG_CPU | |
1e489518 | 1013 | |
67060d9c | 1014 | int __ref smp_rescan_cpus(void) |
08d07968 | 1015 | { |
8b646bd7 MS |
1016 | struct sclp_cpu_info *info; |
1017 | int nr; | |
08d07968 | 1018 | |
8b646bd7 MS |
1019 | info = smp_get_cpu_info(); |
1020 | if (!info) | |
1021 | return -ENOMEM; | |
9d40d2e3 | 1022 | get_online_cpus(); |
0b18d318 | 1023 | mutex_lock(&smp_cpu_state_mutex); |
8b646bd7 | 1024 | nr = __smp_rescan_cpus(info, 1); |
08d07968 | 1025 | mutex_unlock(&smp_cpu_state_mutex); |
0b18d318 | 1026 | put_online_cpus(); |
8b646bd7 MS |
1027 | kfree(info); |
1028 | if (nr) | |
c10fde0d | 1029 | topology_schedule_update(); |
8b646bd7 | 1030 | return 0; |
1e489518 HC |
1031 | } |
1032 | ||
8a25a2fd KS |
1033 | static ssize_t __ref rescan_store(struct device *dev, |
1034 | struct device_attribute *attr, | |
c9be0a36 | 1035 | const char *buf, |
1e489518 HC |
1036 | size_t count) |
1037 | { | |
1038 | int rc; | |
1039 | ||
1040 | rc = smp_rescan_cpus(); | |
08d07968 HC |
1041 | return rc ? rc : count; |
1042 | } | |
8a25a2fd | 1043 | static DEVICE_ATTR(rescan, 0200, NULL, rescan_store); |
08d07968 HC |
1044 | #endif /* CONFIG_HOTPLUG_CPU */ |
1045 | ||
83a24e32 | 1046 | static int __init s390_smp_init(void) |
1da177e4 | 1047 | { |
83a24e32 | 1048 | int cpu, rc; |
2fc2d1e9 | 1049 | |
7755d6b2 | 1050 | hotcpu_notifier(smp_cpu_notify, 0); |
08d07968 | 1051 | #ifdef CONFIG_HOTPLUG_CPU |
8a25a2fd | 1052 | rc = device_create_file(cpu_subsys.dev_root, &dev_attr_rescan); |
08d07968 HC |
1053 | if (rc) |
1054 | return rc; | |
1055 | #endif | |
1056 | for_each_present_cpu(cpu) { | |
1057 | rc = smp_add_present_cpu(cpu); | |
fae8b22d HC |
1058 | if (rc) |
1059 | return rc; | |
1da177e4 LT |
1060 | } |
1061 | return 0; | |
1062 | } | |
83a24e32 | 1063 | subsys_initcall(s390_smp_init); |