Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * arch/s390/kernel/time.c | |
3 | * Time of day based timer functions. | |
4 | * | |
5 | * S390 version | |
d2fec595 | 6 | * Copyright IBM Corp. 1999, 2008 |
1da177e4 LT |
7 | * Author(s): Hartmut Penner (hp@de.ibm.com), |
8 | * Martin Schwidefsky (schwidefsky@de.ibm.com), | |
9 | * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com) | |
10 | * | |
11 | * Derived from "arch/i386/kernel/time.c" | |
12 | * Copyright (C) 1991, 1992, 1995 Linus Torvalds | |
13 | */ | |
14 | ||
feab6501 MS |
15 | #define KMSG_COMPONENT "time" |
16 | #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt | |
17 | ||
1da177e4 LT |
18 | #include <linux/errno.h> |
19 | #include <linux/module.h> | |
20 | #include <linux/sched.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/param.h> | |
23 | #include <linux/string.h> | |
24 | #include <linux/mm.h> | |
25 | #include <linux/interrupt.h> | |
750887de HC |
26 | #include <linux/cpu.h> |
27 | #include <linux/stop_machine.h> | |
1da177e4 | 28 | #include <linux/time.h> |
3367b994 | 29 | #include <linux/sysdev.h> |
1da177e4 LT |
30 | #include <linux/delay.h> |
31 | #include <linux/init.h> | |
32 | #include <linux/smp.h> | |
33 | #include <linux/types.h> | |
34 | #include <linux/profile.h> | |
35 | #include <linux/timex.h> | |
36 | #include <linux/notifier.h> | |
dc64bef5 | 37 | #include <linux/clocksource.h> |
5a62b192 | 38 | #include <linux/clockchips.h> |
5a0e3ad6 | 39 | #include <linux/gfp.h> |
1da177e4 LT |
40 | #include <asm/uaccess.h> |
41 | #include <asm/delay.h> | |
42 | #include <asm/s390_ext.h> | |
43 | #include <asm/div64.h> | |
b020632e | 44 | #include <asm/vdso.h> |
1da177e4 | 45 | #include <asm/irq.h> |
5a489b98 | 46 | #include <asm/irq_regs.h> |
1da177e4 | 47 | #include <asm/timer.h> |
d54853ef | 48 | #include <asm/etr.h> |
a806170e | 49 | #include <asm/cio.h> |
1da177e4 LT |
50 | |
51 | /* change this if you have some constant time drift */ | |
52 | #define USECS_PER_JIFFY ((unsigned long) 1000000/HZ) | |
53 | #define CLK_TICKS_PER_JIFFY ((unsigned long) USECS_PER_JIFFY << 12) | |
54 | ||
b6112ccb | 55 | u64 sched_clock_base_cc = -1; /* Force to data section. */ |
05e7ff7d | 56 | EXPORT_SYMBOL_GPL(sched_clock_base_cc); |
b6112ccb | 57 | |
5a62b192 | 58 | static DEFINE_PER_CPU(struct clock_event_device, comparators); |
1da177e4 | 59 | |
1da177e4 LT |
60 | /* |
61 | * Scheduler clock - returns current time in nanosec units. | |
62 | */ | |
88dbd203 | 63 | unsigned long long notrace sched_clock(void) |
1da177e4 | 64 | { |
05e7ff7d | 65 | return (get_clock_monotonic() * 125) >> 9; |
1da177e4 LT |
66 | } |
67 | ||
32f65f27 JG |
68 | /* |
69 | * Monotonic_clock - returns # of nanoseconds passed since time_init() | |
70 | */ | |
71 | unsigned long long monotonic_clock(void) | |
72 | { | |
73 | return sched_clock(); | |
74 | } | |
75 | EXPORT_SYMBOL(monotonic_clock); | |
76 | ||
b1e2ba8d | 77 | void tod_to_timeval(__u64 todval, struct timespec *xt) |
1da177e4 LT |
78 | { |
79 | unsigned long long sec; | |
80 | ||
81 | sec = todval >> 12; | |
82 | do_div(sec, 1000000); | |
b1e2ba8d | 83 | xt->tv_sec = sec; |
1da177e4 | 84 | todval -= (sec * 1000000) << 12; |
b1e2ba8d | 85 | xt->tv_nsec = ((todval * 1000) >> 12); |
1da177e4 | 86 | } |
b592e89a | 87 | EXPORT_SYMBOL(tod_to_timeval); |
1da177e4 | 88 | |
5a62b192 | 89 | void clock_comparator_work(void) |
1da177e4 | 90 | { |
5a62b192 | 91 | struct clock_event_device *cd; |
1da177e4 | 92 | |
5a62b192 HC |
93 | S390_lowcore.clock_comparator = -1ULL; |
94 | set_clock_comparator(S390_lowcore.clock_comparator); | |
95 | cd = &__get_cpu_var(comparators); | |
96 | cd->event_handler(cd); | |
1da177e4 LT |
97 | } |
98 | ||
1da177e4 | 99 | /* |
5a62b192 | 100 | * Fixup the clock comparator. |
1da177e4 | 101 | */ |
5a62b192 | 102 | static void fixup_clock_comparator(unsigned long long delta) |
1da177e4 | 103 | { |
5a62b192 HC |
104 | /* If nobody is waiting there's nothing to fix. */ |
105 | if (S390_lowcore.clock_comparator == -1ULL) | |
1da177e4 | 106 | return; |
5a62b192 HC |
107 | S390_lowcore.clock_comparator += delta; |
108 | set_clock_comparator(S390_lowcore.clock_comparator); | |
1da177e4 LT |
109 | } |
110 | ||
5a62b192 HC |
111 | static int s390_next_event(unsigned long delta, |
112 | struct clock_event_device *evt) | |
1da177e4 | 113 | { |
5a62b192 HC |
114 | S390_lowcore.clock_comparator = get_clock() + delta; |
115 | set_clock_comparator(S390_lowcore.clock_comparator); | |
116 | return 0; | |
1da177e4 LT |
117 | } |
118 | ||
5a62b192 HC |
119 | static void s390_set_mode(enum clock_event_mode mode, |
120 | struct clock_event_device *evt) | |
1da177e4 | 121 | { |
d54853ef MS |
122 | } |
123 | ||
124 | /* | |
125 | * Set up lowcore and control register of the current cpu to | |
126 | * enable TOD clock and clock comparator interrupts. | |
1da177e4 LT |
127 | */ |
128 | void init_cpu_timer(void) | |
129 | { | |
5a62b192 HC |
130 | struct clock_event_device *cd; |
131 | int cpu; | |
132 | ||
133 | S390_lowcore.clock_comparator = -1ULL; | |
134 | set_clock_comparator(S390_lowcore.clock_comparator); | |
135 | ||
136 | cpu = smp_processor_id(); | |
137 | cd = &per_cpu(comparators, cpu); | |
138 | cd->name = "comparator"; | |
139 | cd->features = CLOCK_EVT_FEAT_ONESHOT; | |
140 | cd->mult = 16777; | |
141 | cd->shift = 12; | |
142 | cd->min_delta_ns = 1; | |
143 | cd->max_delta_ns = LONG_MAX; | |
144 | cd->rating = 400; | |
320ab2b0 | 145 | cd->cpumask = cpumask_of(cpu); |
5a62b192 HC |
146 | cd->set_next_event = s390_next_event; |
147 | cd->set_mode = s390_set_mode; | |
148 | ||
149 | clockevents_register_device(cd); | |
d54853ef MS |
150 | |
151 | /* Enable clock comparator timer interrupt. */ | |
152 | __ctl_set_bit(0,11); | |
153 | ||
d2fec595 | 154 | /* Always allow the timing alert external interrupt. */ |
d54853ef MS |
155 | __ctl_set_bit(0, 4); |
156 | } | |
157 | ||
158 | static void clock_comparator_interrupt(__u16 code) | |
159 | { | |
d3d238c7 HC |
160 | if (S390_lowcore.clock_comparator == -1ULL) |
161 | set_clock_comparator(S390_lowcore.clock_comparator); | |
d54853ef MS |
162 | } |
163 | ||
d2fec595 MS |
164 | static void etr_timing_alert(struct etr_irq_parm *); |
165 | static void stp_timing_alert(struct stp_irq_parm *); | |
166 | ||
167 | static void timing_alert_interrupt(__u16 code) | |
168 | { | |
169 | if (S390_lowcore.ext_params & 0x00c40000) | |
170 | etr_timing_alert((struct etr_irq_parm *) | |
171 | &S390_lowcore.ext_params); | |
172 | if (S390_lowcore.ext_params & 0x00038000) | |
173 | stp_timing_alert((struct stp_irq_parm *) | |
174 | &S390_lowcore.ext_params); | |
175 | } | |
176 | ||
d54853ef | 177 | static void etr_reset(void); |
d2fec595 | 178 | static void stp_reset(void); |
d54853ef | 179 | |
d4f587c6 | 180 | void read_persistent_clock(struct timespec *ts) |
d54853ef | 181 | { |
d4f587c6 | 182 | tod_to_timeval(get_clock() - TOD_UNIX_EPOCH, ts); |
1da177e4 | 183 | } |
d54853ef | 184 | |
23970e38 MS |
185 | void read_boot_clock(struct timespec *ts) |
186 | { | |
187 | tod_to_timeval(sched_clock_base_cc - TOD_UNIX_EPOCH, ts); | |
1da177e4 LT |
188 | } |
189 | ||
8e19608e | 190 | static cycle_t read_tod_clock(struct clocksource *cs) |
dc64bef5 MS |
191 | { |
192 | return get_clock(); | |
193 | } | |
194 | ||
195 | static struct clocksource clocksource_tod = { | |
196 | .name = "tod", | |
d2cb0e6e | 197 | .rating = 400, |
dc64bef5 MS |
198 | .read = read_tod_clock, |
199 | .mask = -1ULL, | |
200 | .mult = 1000, | |
201 | .shift = 12, | |
cc02d809 | 202 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
dc64bef5 MS |
203 | }; |
204 | ||
f1b82746 MS |
205 | struct clocksource * __init clocksource_default_clock(void) |
206 | { | |
207 | return &clocksource_tod; | |
208 | } | |
dc64bef5 | 209 | |
0696b711 LM |
210 | void update_vsyscall(struct timespec *wall_time, struct clocksource *clock, |
211 | u32 mult) | |
b020632e MS |
212 | { |
213 | if (clock != &clocksource_tod) | |
214 | return; | |
215 | ||
216 | /* Make userspace gettimeofday spin until we're done. */ | |
217 | ++vdso_data->tb_update_count; | |
218 | smp_wmb(); | |
219 | vdso_data->xtime_tod_stamp = clock->cycle_last; | |
b1e2ba8d JS |
220 | vdso_data->xtime_clock_sec = wall_time->tv_sec; |
221 | vdso_data->xtime_clock_nsec = wall_time->tv_nsec; | |
b020632e MS |
222 | vdso_data->wtom_clock_sec = wall_to_monotonic.tv_sec; |
223 | vdso_data->wtom_clock_nsec = wall_to_monotonic.tv_nsec; | |
157a1a27 | 224 | vdso_data->ntp_mult = mult; |
b020632e MS |
225 | smp_wmb(); |
226 | ++vdso_data->tb_update_count; | |
227 | } | |
228 | ||
229 | extern struct timezone sys_tz; | |
230 | ||
231 | void update_vsyscall_tz(void) | |
232 | { | |
233 | /* Make userspace gettimeofday spin until we're done. */ | |
234 | ++vdso_data->tb_update_count; | |
235 | smp_wmb(); | |
236 | vdso_data->tz_minuteswest = sys_tz.tz_minuteswest; | |
237 | vdso_data->tz_dsttime = sys_tz.tz_dsttime; | |
238 | smp_wmb(); | |
239 | ++vdso_data->tb_update_count; | |
240 | } | |
241 | ||
1da177e4 LT |
242 | /* |
243 | * Initialize the TOD clock and the CPU timer of | |
244 | * the boot cpu. | |
245 | */ | |
246 | void __init time_init(void) | |
247 | { | |
b6112ccb MS |
248 | /* Reset time synchronization interfaces. */ |
249 | etr_reset(); | |
250 | stp_reset(); | |
1da177e4 | 251 | |
1da177e4 | 252 | /* request the clock comparator external interrupt */ |
d7d1104f | 253 | if (register_external_interrupt(0x1004, clock_comparator_interrupt)) |
1da177e4 LT |
254 | panic("Couldn't request external interrupt 0x1004"); |
255 | ||
d2fec595 | 256 | /* request the timing alert external interrupt */ |
d7d1104f | 257 | if (register_external_interrupt(0x1406, timing_alert_interrupt)) |
d54853ef MS |
258 | panic("Couldn't request external interrupt 0x1406"); |
259 | ||
ab96e798 MS |
260 | if (clocksource_register(&clocksource_tod) != 0) |
261 | panic("Could not register TOD clock source"); | |
262 | ||
d54853ef MS |
263 | /* Enable TOD clock interrupts on the boot cpu. */ |
264 | init_cpu_timer(); | |
ab96e798 | 265 | |
c185b783 | 266 | /* Enable cpu timer interrupts on the boot cpu. */ |
1da177e4 | 267 | vtime_init(); |
d54853ef MS |
268 | } |
269 | ||
d2fec595 MS |
270 | /* |
271 | * The time is "clock". old is what we think the time is. | |
272 | * Adjust the value by a multiple of jiffies and add the delta to ntp. | |
273 | * "delay" is an approximation how long the synchronization took. If | |
274 | * the time correction is positive, then "delay" is subtracted from | |
275 | * the time difference and only the remaining part is passed to ntp. | |
276 | */ | |
277 | static unsigned long long adjust_time(unsigned long long old, | |
278 | unsigned long long clock, | |
279 | unsigned long long delay) | |
280 | { | |
281 | unsigned long long delta, ticks; | |
282 | struct timex adjust; | |
283 | ||
284 | if (clock > old) { | |
285 | /* It is later than we thought. */ | |
286 | delta = ticks = clock - old; | |
287 | delta = ticks = (delta < delay) ? 0 : delta - delay; | |
288 | delta -= do_div(ticks, CLK_TICKS_PER_JIFFY); | |
289 | adjust.offset = ticks * (1000000 / HZ); | |
290 | } else { | |
291 | /* It is earlier than we thought. */ | |
292 | delta = ticks = old - clock; | |
293 | delta -= do_div(ticks, CLK_TICKS_PER_JIFFY); | |
294 | delta = -delta; | |
295 | adjust.offset = -ticks * (1000000 / HZ); | |
296 | } | |
8107d829 | 297 | sched_clock_base_cc += delta; |
d2fec595 | 298 | if (adjust.offset != 0) { |
feab6501 MS |
299 | pr_notice("The ETR interface has adjusted the clock " |
300 | "by %li microseconds\n", adjust.offset); | |
d2fec595 MS |
301 | adjust.modes = ADJ_OFFSET_SINGLESHOT; |
302 | do_adjtimex(&adjust); | |
303 | } | |
304 | return delta; | |
305 | } | |
306 | ||
307 | static DEFINE_PER_CPU(atomic_t, clock_sync_word); | |
8283cb43 | 308 | static DEFINE_MUTEX(clock_sync_mutex); |
d2fec595 MS |
309 | static unsigned long clock_sync_flags; |
310 | ||
311 | #define CLOCK_SYNC_HAS_ETR 0 | |
312 | #define CLOCK_SYNC_HAS_STP 1 | |
313 | #define CLOCK_SYNC_ETR 2 | |
314 | #define CLOCK_SYNC_STP 3 | |
315 | ||
316 | /* | |
317 | * The synchronous get_clock function. It will write the current clock | |
318 | * value to the clock pointer and return 0 if the clock is in sync with | |
319 | * the external time source. If the clock mode is local it will return | |
320 | * -ENOSYS and -EAGAIN if the clock is not in sync with the external | |
321 | * reference. | |
322 | */ | |
323 | int get_sync_clock(unsigned long long *clock) | |
324 | { | |
325 | atomic_t *sw_ptr; | |
326 | unsigned int sw0, sw1; | |
327 | ||
328 | sw_ptr = &get_cpu_var(clock_sync_word); | |
329 | sw0 = atomic_read(sw_ptr); | |
330 | *clock = get_clock(); | |
331 | sw1 = atomic_read(sw_ptr); | |
bd119ee2 | 332 | put_cpu_var(clock_sync_word); |
d2fec595 MS |
333 | if (sw0 == sw1 && (sw0 & 0x80000000U)) |
334 | /* Success: time is in sync. */ | |
335 | return 0; | |
336 | if (!test_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags) && | |
337 | !test_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags)) | |
338 | return -ENOSYS; | |
339 | if (!test_bit(CLOCK_SYNC_ETR, &clock_sync_flags) && | |
340 | !test_bit(CLOCK_SYNC_STP, &clock_sync_flags)) | |
341 | return -EACCES; | |
342 | return -EAGAIN; | |
343 | } | |
344 | EXPORT_SYMBOL(get_sync_clock); | |
345 | ||
346 | /* | |
347 | * Make get_sync_clock return -EAGAIN. | |
348 | */ | |
349 | static void disable_sync_clock(void *dummy) | |
350 | { | |
351 | atomic_t *sw_ptr = &__get_cpu_var(clock_sync_word); | |
352 | /* | |
353 | * Clear the in-sync bit 2^31. All get_sync_clock calls will | |
354 | * fail until the sync bit is turned back on. In addition | |
355 | * increase the "sequence" counter to avoid the race of an | |
356 | * etr event and the complete recovery against get_sync_clock. | |
357 | */ | |
358 | atomic_clear_mask(0x80000000, sw_ptr); | |
359 | atomic_inc(sw_ptr); | |
360 | } | |
361 | ||
362 | /* | |
363 | * Make get_sync_clock return 0 again. | |
364 | * Needs to be called from a context disabled for preemption. | |
365 | */ | |
366 | static void enable_sync_clock(void) | |
367 | { | |
368 | atomic_t *sw_ptr = &__get_cpu_var(clock_sync_word); | |
369 | atomic_set_mask(0x80000000, sw_ptr); | |
370 | } | |
371 | ||
8283cb43 MS |
372 | /* |
373 | * Function to check if the clock is in sync. | |
374 | */ | |
375 | static inline int check_sync_clock(void) | |
376 | { | |
377 | atomic_t *sw_ptr; | |
378 | int rc; | |
379 | ||
380 | sw_ptr = &get_cpu_var(clock_sync_word); | |
381 | rc = (atomic_read(sw_ptr) & 0x80000000U) != 0; | |
bd119ee2 | 382 | put_cpu_var(clock_sync_word); |
8283cb43 MS |
383 | return rc; |
384 | } | |
385 | ||
750887de HC |
386 | /* Single threaded workqueue used for etr and stp sync events */ |
387 | static struct workqueue_struct *time_sync_wq; | |
388 | ||
389 | static void __init time_init_wq(void) | |
390 | { | |
179cb81a HC |
391 | if (time_sync_wq) |
392 | return; | |
393 | time_sync_wq = create_singlethread_workqueue("timesync"); | |
750887de HC |
394 | } |
395 | ||
d54853ef MS |
396 | /* |
397 | * External Time Reference (ETR) code. | |
398 | */ | |
399 | static int etr_port0_online; | |
400 | static int etr_port1_online; | |
d2fec595 | 401 | static int etr_steai_available; |
d54853ef MS |
402 | |
403 | static int __init early_parse_etr(char *p) | |
404 | { | |
405 | if (strncmp(p, "off", 3) == 0) | |
406 | etr_port0_online = etr_port1_online = 0; | |
407 | else if (strncmp(p, "port0", 5) == 0) | |
408 | etr_port0_online = 1; | |
409 | else if (strncmp(p, "port1", 5) == 0) | |
410 | etr_port1_online = 1; | |
411 | else if (strncmp(p, "on", 2) == 0) | |
412 | etr_port0_online = etr_port1_online = 1; | |
413 | return 0; | |
414 | } | |
415 | early_param("etr", early_parse_etr); | |
416 | ||
417 | enum etr_event { | |
418 | ETR_EVENT_PORT0_CHANGE, | |
419 | ETR_EVENT_PORT1_CHANGE, | |
420 | ETR_EVENT_PORT_ALERT, | |
421 | ETR_EVENT_SYNC_CHECK, | |
422 | ETR_EVENT_SWITCH_LOCAL, | |
423 | ETR_EVENT_UPDATE, | |
424 | }; | |
425 | ||
d54853ef MS |
426 | /* |
427 | * Valid bit combinations of the eacr register are (x = don't care): | |
428 | * e0 e1 dp p0 p1 ea es sl | |
429 | * 0 0 x 0 0 0 0 0 initial, disabled state | |
430 | * 0 0 x 0 1 1 0 0 port 1 online | |
431 | * 0 0 x 1 0 1 0 0 port 0 online | |
432 | * 0 0 x 1 1 1 0 0 both ports online | |
433 | * 0 1 x 0 1 1 0 0 port 1 online and usable, ETR or PPS mode | |
434 | * 0 1 x 0 1 1 0 1 port 1 online, usable and ETR mode | |
435 | * 0 1 x 0 1 1 1 0 port 1 online, usable, PPS mode, in-sync | |
436 | * 0 1 x 0 1 1 1 1 port 1 online, usable, ETR mode, in-sync | |
437 | * 0 1 x 1 1 1 0 0 both ports online, port 1 usable | |
438 | * 0 1 x 1 1 1 1 0 both ports online, port 1 usable, PPS mode, in-sync | |
439 | * 0 1 x 1 1 1 1 1 both ports online, port 1 usable, ETR mode, in-sync | |
440 | * 1 0 x 1 0 1 0 0 port 0 online and usable, ETR or PPS mode | |
441 | * 1 0 x 1 0 1 0 1 port 0 online, usable and ETR mode | |
442 | * 1 0 x 1 0 1 1 0 port 0 online, usable, PPS mode, in-sync | |
443 | * 1 0 x 1 0 1 1 1 port 0 online, usable, ETR mode, in-sync | |
444 | * 1 0 x 1 1 1 0 0 both ports online, port 0 usable | |
445 | * 1 0 x 1 1 1 1 0 both ports online, port 0 usable, PPS mode, in-sync | |
446 | * 1 0 x 1 1 1 1 1 both ports online, port 0 usable, ETR mode, in-sync | |
447 | * 1 1 x 1 1 1 1 0 both ports online & usable, ETR, in-sync | |
448 | * 1 1 x 1 1 1 1 1 both ports online & usable, ETR, in-sync | |
449 | */ | |
450 | static struct etr_eacr etr_eacr; | |
451 | static u64 etr_tolec; /* time of last eacr update */ | |
d54853ef MS |
452 | static struct etr_aib etr_port0; |
453 | static int etr_port0_uptodate; | |
454 | static struct etr_aib etr_port1; | |
455 | static int etr_port1_uptodate; | |
456 | static unsigned long etr_events; | |
457 | static struct timer_list etr_timer; | |
d54853ef MS |
458 | |
459 | static void etr_timeout(unsigned long dummy); | |
ecdcc023 | 460 | static void etr_work_fn(struct work_struct *work); |
0b3016b7 | 461 | static DEFINE_MUTEX(etr_work_mutex); |
ecdcc023 | 462 | static DECLARE_WORK(etr_work, etr_work_fn); |
d54853ef | 463 | |
d54853ef MS |
464 | /* |
465 | * Reset ETR attachment. | |
466 | */ | |
467 | static void etr_reset(void) | |
468 | { | |
469 | etr_eacr = (struct etr_eacr) { | |
470 | .e0 = 0, .e1 = 0, ._pad0 = 4, .dp = 0, | |
471 | .p0 = 0, .p1 = 0, ._pad1 = 0, .ea = 0, | |
472 | .es = 0, .sl = 0 }; | |
d2fec595 | 473 | if (etr_setr(&etr_eacr) == 0) { |
d54853ef | 474 | etr_tolec = get_clock(); |
d2fec595 | 475 | set_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags); |
8283cb43 MS |
476 | if (etr_port0_online && etr_port1_online) |
477 | set_bit(CLOCK_SYNC_ETR, &clock_sync_flags); | |
d2fec595 | 478 | } else if (etr_port0_online || etr_port1_online) { |
feab6501 MS |
479 | pr_warning("The real or virtual hardware system does " |
480 | "not provide an ETR interface\n"); | |
d2fec595 | 481 | etr_port0_online = etr_port1_online = 0; |
d54853ef MS |
482 | } |
483 | } | |
484 | ||
ecdcc023 | 485 | static int __init etr_init(void) |
d54853ef MS |
486 | { |
487 | struct etr_aib aib; | |
488 | ||
d2fec595 | 489 | if (!test_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags)) |
ecdcc023 | 490 | return 0; |
750887de | 491 | time_init_wq(); |
d54853ef MS |
492 | /* Check if this machine has the steai instruction. */ |
493 | if (etr_steai(&aib, ETR_STEAI_STEPPING_PORT) == 0) | |
d2fec595 | 494 | etr_steai_available = 1; |
d54853ef | 495 | setup_timer(&etr_timer, etr_timeout, 0UL); |
d54853ef MS |
496 | if (etr_port0_online) { |
497 | set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events); | |
750887de | 498 | queue_work(time_sync_wq, &etr_work); |
d54853ef MS |
499 | } |
500 | if (etr_port1_online) { | |
501 | set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events); | |
750887de | 502 | queue_work(time_sync_wq, &etr_work); |
d54853ef | 503 | } |
ecdcc023 | 504 | return 0; |
d54853ef MS |
505 | } |
506 | ||
ecdcc023 MS |
507 | arch_initcall(etr_init); |
508 | ||
d54853ef MS |
509 | /* |
510 | * Two sorts of ETR machine checks. The architecture reads: | |
511 | * "When a machine-check niterruption occurs and if a switch-to-local or | |
512 | * ETR-sync-check interrupt request is pending but disabled, this pending | |
513 | * disabled interruption request is indicated and is cleared". | |
514 | * Which means that we can get etr_switch_to_local events from the machine | |
515 | * check handler although the interruption condition is disabled. Lovely.. | |
516 | */ | |
517 | ||
518 | /* | |
519 | * Switch to local machine check. This is called when the last usable | |
520 | * ETR port goes inactive. After switch to local the clock is not in sync. | |
521 | */ | |
522 | void etr_switch_to_local(void) | |
523 | { | |
524 | if (!etr_eacr.sl) | |
525 | return; | |
8283cb43 | 526 | disable_sync_clock(NULL); |
d54853ef | 527 | set_bit(ETR_EVENT_SWITCH_LOCAL, &etr_events); |
750887de | 528 | queue_work(time_sync_wq, &etr_work); |
d54853ef MS |
529 | } |
530 | ||
531 | /* | |
532 | * ETR sync check machine check. This is called when the ETR OTE and the | |
533 | * local clock OTE are farther apart than the ETR sync check tolerance. | |
534 | * After a ETR sync check the clock is not in sync. The machine check | |
535 | * is broadcasted to all cpus at the same time. | |
536 | */ | |
537 | void etr_sync_check(void) | |
538 | { | |
539 | if (!etr_eacr.es) | |
540 | return; | |
8283cb43 | 541 | disable_sync_clock(NULL); |
d54853ef | 542 | set_bit(ETR_EVENT_SYNC_CHECK, &etr_events); |
750887de | 543 | queue_work(time_sync_wq, &etr_work); |
d54853ef MS |
544 | } |
545 | ||
546 | /* | |
d2fec595 | 547 | * ETR timing alert. There are two causes: |
d54853ef MS |
548 | * 1) port state change, check the usability of the port |
549 | * 2) port alert, one of the ETR-data-validity bits (v1-v2 bits of the | |
550 | * sldr-status word) or ETR-data word 1 (edf1) or ETR-data word 3 (edf3) | |
551 | * or ETR-data word 4 (edf4) has changed. | |
552 | */ | |
d2fec595 | 553 | static void etr_timing_alert(struct etr_irq_parm *intparm) |
d54853ef | 554 | { |
d54853ef MS |
555 | if (intparm->pc0) |
556 | /* ETR port 0 state change. */ | |
557 | set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events); | |
558 | if (intparm->pc1) | |
559 | /* ETR port 1 state change. */ | |
560 | set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events); | |
561 | if (intparm->eai) | |
562 | /* | |
563 | * ETR port alert on either port 0, 1 or both. | |
564 | * Both ports are not up-to-date now. | |
565 | */ | |
566 | set_bit(ETR_EVENT_PORT_ALERT, &etr_events); | |
750887de | 567 | queue_work(time_sync_wq, &etr_work); |
d54853ef MS |
568 | } |
569 | ||
570 | static void etr_timeout(unsigned long dummy) | |
571 | { | |
572 | set_bit(ETR_EVENT_UPDATE, &etr_events); | |
750887de | 573 | queue_work(time_sync_wq, &etr_work); |
d54853ef MS |
574 | } |
575 | ||
576 | /* | |
577 | * Check if the etr mode is pss. | |
578 | */ | |
579 | static inline int etr_mode_is_pps(struct etr_eacr eacr) | |
580 | { | |
581 | return eacr.es && !eacr.sl; | |
582 | } | |
583 | ||
584 | /* | |
585 | * Check if the etr mode is etr. | |
586 | */ | |
587 | static inline int etr_mode_is_etr(struct etr_eacr eacr) | |
588 | { | |
589 | return eacr.es && eacr.sl; | |
590 | } | |
591 | ||
592 | /* | |
593 | * Check if the port can be used for TOD synchronization. | |
594 | * For PPS mode the port has to receive OTEs. For ETR mode | |
595 | * the port has to receive OTEs, the ETR stepping bit has to | |
596 | * be zero and the validity bits for data frame 1, 2, and 3 | |
597 | * have to be 1. | |
598 | */ | |
599 | static int etr_port_valid(struct etr_aib *aib, int port) | |
600 | { | |
601 | unsigned int psc; | |
602 | ||
603 | /* Check that this port is receiving OTEs. */ | |
604 | if (aib->tsp == 0) | |
605 | return 0; | |
606 | ||
607 | psc = port ? aib->esw.psc1 : aib->esw.psc0; | |
608 | if (psc == etr_lpsc_pps_mode) | |
609 | return 1; | |
610 | if (psc == etr_lpsc_operational_step) | |
611 | return !aib->esw.y && aib->slsw.v1 && | |
612 | aib->slsw.v2 && aib->slsw.v3; | |
613 | return 0; | |
614 | } | |
615 | ||
616 | /* | |
617 | * Check if two ports are on the same network. | |
618 | */ | |
619 | static int etr_compare_network(struct etr_aib *aib1, struct etr_aib *aib2) | |
620 | { | |
621 | // FIXME: any other fields we have to compare? | |
622 | return aib1->edf1.net_id == aib2->edf1.net_id; | |
623 | } | |
624 | ||
625 | /* | |
626 | * Wrapper for etr_stei that converts physical port states | |
627 | * to logical port states to be consistent with the output | |
628 | * of stetr (see etr_psc vs. etr_lpsc). | |
629 | */ | |
630 | static void etr_steai_cv(struct etr_aib *aib, unsigned int func) | |
631 | { | |
632 | BUG_ON(etr_steai(aib, func) != 0); | |
633 | /* Convert port state to logical port state. */ | |
634 | if (aib->esw.psc0 == 1) | |
635 | aib->esw.psc0 = 2; | |
636 | else if (aib->esw.psc0 == 0 && aib->esw.p == 0) | |
637 | aib->esw.psc0 = 1; | |
638 | if (aib->esw.psc1 == 1) | |
639 | aib->esw.psc1 = 2; | |
640 | else if (aib->esw.psc1 == 0 && aib->esw.p == 1) | |
641 | aib->esw.psc1 = 1; | |
642 | } | |
643 | ||
644 | /* | |
645 | * Check if the aib a2 is still connected to the same attachment as | |
646 | * aib a1, the etv values differ by one and a2 is valid. | |
647 | */ | |
648 | static int etr_aib_follows(struct etr_aib *a1, struct etr_aib *a2, int p) | |
649 | { | |
650 | int state_a1, state_a2; | |
651 | ||
652 | /* Paranoia check: e0/e1 should better be the same. */ | |
653 | if (a1->esw.eacr.e0 != a2->esw.eacr.e0 || | |
654 | a1->esw.eacr.e1 != a2->esw.eacr.e1) | |
655 | return 0; | |
656 | ||
657 | /* Still connected to the same etr ? */ | |
658 | state_a1 = p ? a1->esw.psc1 : a1->esw.psc0; | |
659 | state_a2 = p ? a2->esw.psc1 : a2->esw.psc0; | |
660 | if (state_a1 == etr_lpsc_operational_step) { | |
661 | if (state_a2 != etr_lpsc_operational_step || | |
662 | a1->edf1.net_id != a2->edf1.net_id || | |
663 | a1->edf1.etr_id != a2->edf1.etr_id || | |
664 | a1->edf1.etr_pn != a2->edf1.etr_pn) | |
665 | return 0; | |
666 | } else if (state_a2 != etr_lpsc_pps_mode) | |
667 | return 0; | |
668 | ||
669 | /* The ETV value of a2 needs to be ETV of a1 + 1. */ | |
670 | if (a1->edf2.etv + 1 != a2->edf2.etv) | |
671 | return 0; | |
672 | ||
673 | if (!etr_port_valid(a2, p)) | |
674 | return 0; | |
675 | ||
676 | return 1; | |
677 | } | |
678 | ||
d2fec595 | 679 | struct clock_sync_data { |
750887de | 680 | atomic_t cpus; |
5a62b192 HC |
681 | int in_sync; |
682 | unsigned long long fixup_cc; | |
750887de HC |
683 | int etr_port; |
684 | struct etr_aib *etr_aib; | |
d2fec595 | 685 | }; |
5a62b192 | 686 | |
750887de | 687 | static void clock_sync_cpu(struct clock_sync_data *sync) |
d54853ef | 688 | { |
750887de | 689 | atomic_dec(&sync->cpus); |
d2fec595 | 690 | enable_sync_clock(); |
d54853ef MS |
691 | /* |
692 | * This looks like a busy wait loop but it isn't. etr_sync_cpus | |
693 | * is called on all other cpus while the TOD clocks is stopped. | |
694 | * __udelay will stop the cpu on an enabled wait psw until the | |
695 | * TOD is running again. | |
696 | */ | |
d2fec595 | 697 | while (sync->in_sync == 0) { |
d54853ef | 698 | __udelay(1); |
6c732de2 HC |
699 | /* |
700 | * A different cpu changes *in_sync. Therefore use | |
701 | * barrier() to force memory access. | |
702 | */ | |
703 | barrier(); | |
704 | } | |
d2fec595 | 705 | if (sync->in_sync != 1) |
d54853ef | 706 | /* Didn't work. Clear per-cpu in sync bit again. */ |
d2fec595 | 707 | disable_sync_clock(NULL); |
d54853ef MS |
708 | /* |
709 | * This round of TOD syncing is done. Set the clock comparator | |
710 | * to the next tick and let the processor continue. | |
711 | */ | |
d2fec595 | 712 | fixup_clock_comparator(sync->fixup_cc); |
d54853ef MS |
713 | } |
714 | ||
d54853ef MS |
715 | /* |
716 | * Sync the TOD clock using the port refered to by aibp. This port | |
717 | * has to be enabled and the other port has to be disabled. The | |
718 | * last eacr update has to be more than 1.6 seconds in the past. | |
719 | */ | |
750887de | 720 | static int etr_sync_clock(void *data) |
d54853ef | 721 | { |
750887de | 722 | static int first; |
5a62b192 | 723 | unsigned long long clock, old_clock, delay, delta; |
750887de HC |
724 | struct clock_sync_data *etr_sync; |
725 | struct etr_aib *sync_port, *aib; | |
726 | int port; | |
d54853ef MS |
727 | int rc; |
728 | ||
750887de | 729 | etr_sync = data; |
d54853ef | 730 | |
750887de HC |
731 | if (xchg(&first, 1) == 1) { |
732 | /* Slave */ | |
733 | clock_sync_cpu(etr_sync); | |
734 | return 0; | |
735 | } | |
736 | ||
737 | /* Wait until all other cpus entered the sync function. */ | |
738 | while (atomic_read(&etr_sync->cpus) != 0) | |
739 | cpu_relax(); | |
740 | ||
741 | port = etr_sync->etr_port; | |
742 | aib = etr_sync->etr_aib; | |
743 | sync_port = (port == 0) ? &etr_port0 : &etr_port1; | |
d2fec595 | 744 | enable_sync_clock(); |
d54853ef MS |
745 | |
746 | /* Set clock to next OTE. */ | |
747 | __ctl_set_bit(14, 21); | |
748 | __ctl_set_bit(0, 29); | |
749 | clock = ((unsigned long long) (aib->edf2.etv + 1)) << 32; | |
5a62b192 | 750 | old_clock = get_clock(); |
d54853ef MS |
751 | if (set_clock(clock) == 0) { |
752 | __udelay(1); /* Wait for the clock to start. */ | |
753 | __ctl_clear_bit(0, 29); | |
754 | __ctl_clear_bit(14, 21); | |
755 | etr_stetr(aib); | |
756 | /* Adjust Linux timing variables. */ | |
757 | delay = (unsigned long long) | |
758 | (aib->edf2.etv - sync_port->edf2.etv) << 32; | |
d2fec595 | 759 | delta = adjust_time(old_clock, clock, delay); |
750887de | 760 | etr_sync->fixup_cc = delta; |
5a62b192 | 761 | fixup_clock_comparator(delta); |
d54853ef MS |
762 | /* Verify that the clock is properly set. */ |
763 | if (!etr_aib_follows(sync_port, aib, port)) { | |
764 | /* Didn't work. */ | |
d2fec595 | 765 | disable_sync_clock(NULL); |
750887de | 766 | etr_sync->in_sync = -EAGAIN; |
d54853ef MS |
767 | rc = -EAGAIN; |
768 | } else { | |
750887de | 769 | etr_sync->in_sync = 1; |
d54853ef MS |
770 | rc = 0; |
771 | } | |
772 | } else { | |
773 | /* Could not set the clock ?!? */ | |
774 | __ctl_clear_bit(0, 29); | |
775 | __ctl_clear_bit(14, 21); | |
d2fec595 | 776 | disable_sync_clock(NULL); |
750887de | 777 | etr_sync->in_sync = -EAGAIN; |
d54853ef MS |
778 | rc = -EAGAIN; |
779 | } | |
750887de HC |
780 | xchg(&first, 0); |
781 | return rc; | |
782 | } | |
783 | ||
784 | static int etr_sync_clock_stop(struct etr_aib *aib, int port) | |
785 | { | |
786 | struct clock_sync_data etr_sync; | |
787 | struct etr_aib *sync_port; | |
788 | int follows; | |
789 | int rc; | |
790 | ||
791 | /* Check if the current aib is adjacent to the sync port aib. */ | |
792 | sync_port = (port == 0) ? &etr_port0 : &etr_port1; | |
793 | follows = etr_aib_follows(sync_port, aib, port); | |
794 | memcpy(sync_port, aib, sizeof(*aib)); | |
795 | if (!follows) | |
796 | return -EAGAIN; | |
797 | memset(&etr_sync, 0, sizeof(etr_sync)); | |
798 | etr_sync.etr_aib = aib; | |
799 | etr_sync.etr_port = port; | |
800 | get_online_cpus(); | |
801 | atomic_set(&etr_sync.cpus, num_online_cpus() - 1); | |
802 | rc = stop_machine(etr_sync_clock, &etr_sync, &cpu_online_map); | |
803 | put_online_cpus(); | |
d54853ef MS |
804 | return rc; |
805 | } | |
806 | ||
807 | /* | |
808 | * Handle the immediate effects of the different events. | |
809 | * The port change event is used for online/offline changes. | |
810 | */ | |
811 | static struct etr_eacr etr_handle_events(struct etr_eacr eacr) | |
812 | { | |
813 | if (test_and_clear_bit(ETR_EVENT_SYNC_CHECK, &etr_events)) | |
814 | eacr.es = 0; | |
815 | if (test_and_clear_bit(ETR_EVENT_SWITCH_LOCAL, &etr_events)) | |
816 | eacr.es = eacr.sl = 0; | |
817 | if (test_and_clear_bit(ETR_EVENT_PORT_ALERT, &etr_events)) | |
818 | etr_port0_uptodate = etr_port1_uptodate = 0; | |
819 | ||
820 | if (test_and_clear_bit(ETR_EVENT_PORT0_CHANGE, &etr_events)) { | |
821 | if (eacr.e0) | |
822 | /* | |
823 | * Port change of an enabled port. We have to | |
824 | * assume that this can have caused an stepping | |
825 | * port switch. | |
826 | */ | |
827 | etr_tolec = get_clock(); | |
828 | eacr.p0 = etr_port0_online; | |
829 | if (!eacr.p0) | |
830 | eacr.e0 = 0; | |
831 | etr_port0_uptodate = 0; | |
832 | } | |
833 | if (test_and_clear_bit(ETR_EVENT_PORT1_CHANGE, &etr_events)) { | |
834 | if (eacr.e1) | |
835 | /* | |
836 | * Port change of an enabled port. We have to | |
837 | * assume that this can have caused an stepping | |
838 | * port switch. | |
839 | */ | |
840 | etr_tolec = get_clock(); | |
841 | eacr.p1 = etr_port1_online; | |
842 | if (!eacr.p1) | |
843 | eacr.e1 = 0; | |
844 | etr_port1_uptodate = 0; | |
845 | } | |
846 | clear_bit(ETR_EVENT_UPDATE, &etr_events); | |
847 | return eacr; | |
848 | } | |
849 | ||
850 | /* | |
851 | * Set up a timer that expires after the etr_tolec + 1.6 seconds if | |
852 | * one of the ports needs an update. | |
853 | */ | |
854 | static void etr_set_tolec_timeout(unsigned long long now) | |
855 | { | |
856 | unsigned long micros; | |
857 | ||
858 | if ((!etr_eacr.p0 || etr_port0_uptodate) && | |
859 | (!etr_eacr.p1 || etr_port1_uptodate)) | |
860 | return; | |
861 | micros = (now > etr_tolec) ? ((now - etr_tolec) >> 12) : 0; | |
862 | micros = (micros > 1600000) ? 0 : 1600000 - micros; | |
863 | mod_timer(&etr_timer, jiffies + (micros * HZ) / 1000000 + 1); | |
864 | } | |
865 | ||
866 | /* | |
867 | * Set up a time that expires after 1/2 second. | |
868 | */ | |
869 | static void etr_set_sync_timeout(void) | |
870 | { | |
871 | mod_timer(&etr_timer, jiffies + HZ/2); | |
872 | } | |
873 | ||
874 | /* | |
875 | * Update the aib information for one or both ports. | |
876 | */ | |
877 | static struct etr_eacr etr_handle_update(struct etr_aib *aib, | |
878 | struct etr_eacr eacr) | |
879 | { | |
880 | /* With both ports disabled the aib information is useless. */ | |
881 | if (!eacr.e0 && !eacr.e1) | |
882 | return eacr; | |
883 | ||
ecdcc023 | 884 | /* Update port0 or port1 with aib stored in etr_work_fn. */ |
d54853ef MS |
885 | if (aib->esw.q == 0) { |
886 | /* Information for port 0 stored. */ | |
887 | if (eacr.p0 && !etr_port0_uptodate) { | |
888 | etr_port0 = *aib; | |
889 | if (etr_port0_online) | |
890 | etr_port0_uptodate = 1; | |
891 | } | |
892 | } else { | |
893 | /* Information for port 1 stored. */ | |
894 | if (eacr.p1 && !etr_port1_uptodate) { | |
895 | etr_port1 = *aib; | |
896 | if (etr_port0_online) | |
897 | etr_port1_uptodate = 1; | |
898 | } | |
899 | } | |
900 | ||
901 | /* | |
902 | * Do not try to get the alternate port aib if the clock | |
903 | * is not in sync yet. | |
904 | */ | |
8283cb43 | 905 | if (!check_sync_clock()) |
d54853ef MS |
906 | return eacr; |
907 | ||
908 | /* | |
909 | * If steai is available we can get the information about | |
910 | * the other port immediately. If only stetr is available the | |
911 | * data-port bit toggle has to be used. | |
912 | */ | |
d2fec595 | 913 | if (etr_steai_available) { |
d54853ef MS |
914 | if (eacr.p0 && !etr_port0_uptodate) { |
915 | etr_steai_cv(&etr_port0, ETR_STEAI_PORT_0); | |
916 | etr_port0_uptodate = 1; | |
917 | } | |
918 | if (eacr.p1 && !etr_port1_uptodate) { | |
919 | etr_steai_cv(&etr_port1, ETR_STEAI_PORT_1); | |
920 | etr_port1_uptodate = 1; | |
921 | } | |
922 | } else { | |
923 | /* | |
924 | * One port was updated above, if the other | |
925 | * port is not uptodate toggle dp bit. | |
926 | */ | |
927 | if ((eacr.p0 && !etr_port0_uptodate) || | |
928 | (eacr.p1 && !etr_port1_uptodate)) | |
929 | eacr.dp ^= 1; | |
930 | else | |
931 | eacr.dp = 0; | |
932 | } | |
933 | return eacr; | |
934 | } | |
935 | ||
936 | /* | |
937 | * Write new etr control register if it differs from the current one. | |
938 | * Return 1 if etr_tolec has been updated as well. | |
939 | */ | |
940 | static void etr_update_eacr(struct etr_eacr eacr) | |
941 | { | |
942 | int dp_changed; | |
943 | ||
944 | if (memcmp(&etr_eacr, &eacr, sizeof(eacr)) == 0) | |
945 | /* No change, return. */ | |
946 | return; | |
947 | /* | |
948 | * The disable of an active port of the change of the data port | |
949 | * bit can/will cause a change in the data port. | |
950 | */ | |
951 | dp_changed = etr_eacr.e0 > eacr.e0 || etr_eacr.e1 > eacr.e1 || | |
952 | (etr_eacr.dp ^ eacr.dp) != 0; | |
953 | etr_eacr = eacr; | |
954 | etr_setr(&etr_eacr); | |
955 | if (dp_changed) | |
956 | etr_tolec = get_clock(); | |
957 | } | |
958 | ||
959 | /* | |
750887de | 960 | * ETR work. In this function you'll find the main logic. In |
d54853ef MS |
961 | * particular this is the only function that calls etr_update_eacr(), |
962 | * it "controls" the etr control register. | |
963 | */ | |
ecdcc023 | 964 | static void etr_work_fn(struct work_struct *work) |
d54853ef MS |
965 | { |
966 | unsigned long long now; | |
967 | struct etr_eacr eacr; | |
968 | struct etr_aib aib; | |
969 | int sync_port; | |
970 | ||
0b3016b7 MS |
971 | /* prevent multiple execution. */ |
972 | mutex_lock(&etr_work_mutex); | |
973 | ||
d54853ef MS |
974 | /* Create working copy of etr_eacr. */ |
975 | eacr = etr_eacr; | |
976 | ||
977 | /* Check for the different events and their immediate effects. */ | |
978 | eacr = etr_handle_events(eacr); | |
979 | ||
980 | /* Check if ETR is supposed to be active. */ | |
981 | eacr.ea = eacr.p0 || eacr.p1; | |
982 | if (!eacr.ea) { | |
983 | /* Both ports offline. Reset everything. */ | |
984 | eacr.dp = eacr.es = eacr.sl = 0; | |
1a781a77 | 985 | on_each_cpu(disable_sync_clock, NULL, 1); |
d54853ef MS |
986 | del_timer_sync(&etr_timer); |
987 | etr_update_eacr(eacr); | |
0b3016b7 | 988 | goto out_unlock; |
d54853ef MS |
989 | } |
990 | ||
991 | /* Store aib to get the current ETR status word. */ | |
992 | BUG_ON(etr_stetr(&aib) != 0); | |
993 | etr_port0.esw = etr_port1.esw = aib.esw; /* Copy status word. */ | |
994 | now = get_clock(); | |
995 | ||
996 | /* | |
997 | * Update the port information if the last stepping port change | |
998 | * or data port change is older than 1.6 seconds. | |
999 | */ | |
1000 | if (now >= etr_tolec + (1600000 << 12)) | |
1001 | eacr = etr_handle_update(&aib, eacr); | |
1002 | ||
1003 | /* | |
1004 | * Select ports to enable. The prefered synchronization mode is PPS. | |
1005 | * If a port can be enabled depends on a number of things: | |
1006 | * 1) The port needs to be online and uptodate. A port is not | |
1007 | * disabled just because it is not uptodate, but it is only | |
1008 | * enabled if it is uptodate. | |
1009 | * 2) The port needs to have the same mode (pps / etr). | |
1010 | * 3) The port needs to be usable -> etr_port_valid() == 1 | |
1011 | * 4) To enable the second port the clock needs to be in sync. | |
1012 | * 5) If both ports are useable and are ETR ports, the network id | |
1013 | * has to be the same. | |
1014 | * The eacr.sl bit is used to indicate etr mode vs. pps mode. | |
1015 | */ | |
1016 | if (eacr.p0 && aib.esw.psc0 == etr_lpsc_pps_mode) { | |
1017 | eacr.sl = 0; | |
1018 | eacr.e0 = 1; | |
1019 | if (!etr_mode_is_pps(etr_eacr)) | |
1020 | eacr.es = 0; | |
1021 | if (!eacr.es || !eacr.p1 || aib.esw.psc1 != etr_lpsc_pps_mode) | |
1022 | eacr.e1 = 0; | |
1023 | // FIXME: uptodate checks ? | |
1024 | else if (etr_port0_uptodate && etr_port1_uptodate) | |
1025 | eacr.e1 = 1; | |
1026 | sync_port = (etr_port0_uptodate && | |
1027 | etr_port_valid(&etr_port0, 0)) ? 0 : -1; | |
d54853ef MS |
1028 | } else if (eacr.p1 && aib.esw.psc1 == etr_lpsc_pps_mode) { |
1029 | eacr.sl = 0; | |
1030 | eacr.e0 = 0; | |
1031 | eacr.e1 = 1; | |
1032 | if (!etr_mode_is_pps(etr_eacr)) | |
1033 | eacr.es = 0; | |
1034 | sync_port = (etr_port1_uptodate && | |
1035 | etr_port_valid(&etr_port1, 1)) ? 1 : -1; | |
d54853ef MS |
1036 | } else if (eacr.p0 && aib.esw.psc0 == etr_lpsc_operational_step) { |
1037 | eacr.sl = 1; | |
1038 | eacr.e0 = 1; | |
1039 | if (!etr_mode_is_etr(etr_eacr)) | |
1040 | eacr.es = 0; | |
1041 | if (!eacr.es || !eacr.p1 || | |
1042 | aib.esw.psc1 != etr_lpsc_operational_alt) | |
1043 | eacr.e1 = 0; | |
1044 | else if (etr_port0_uptodate && etr_port1_uptodate && | |
1045 | etr_compare_network(&etr_port0, &etr_port1)) | |
1046 | eacr.e1 = 1; | |
1047 | sync_port = (etr_port0_uptodate && | |
1048 | etr_port_valid(&etr_port0, 0)) ? 0 : -1; | |
d54853ef MS |
1049 | } else if (eacr.p1 && aib.esw.psc1 == etr_lpsc_operational_step) { |
1050 | eacr.sl = 1; | |
1051 | eacr.e0 = 0; | |
1052 | eacr.e1 = 1; | |
1053 | if (!etr_mode_is_etr(etr_eacr)) | |
1054 | eacr.es = 0; | |
1055 | sync_port = (etr_port1_uptodate && | |
1056 | etr_port_valid(&etr_port1, 1)) ? 1 : -1; | |
d54853ef MS |
1057 | } else { |
1058 | /* Both ports not usable. */ | |
1059 | eacr.es = eacr.sl = 0; | |
1060 | sync_port = -1; | |
d54853ef MS |
1061 | } |
1062 | ||
1063 | /* | |
1064 | * If the clock is in sync just update the eacr and return. | |
1065 | * If there is no valid sync port wait for a port update. | |
1066 | */ | |
8283cb43 | 1067 | if (check_sync_clock() || sync_port < 0) { |
d54853ef MS |
1068 | etr_update_eacr(eacr); |
1069 | etr_set_tolec_timeout(now); | |
0b3016b7 | 1070 | goto out_unlock; |
d54853ef MS |
1071 | } |
1072 | ||
1073 | /* | |
1074 | * Prepare control register for clock syncing | |
1075 | * (reset data port bit, set sync check control. | |
1076 | */ | |
1077 | eacr.dp = 0; | |
1078 | eacr.es = 1; | |
1079 | ||
1080 | /* | |
1081 | * Update eacr and try to synchronize the clock. If the update | |
1082 | * of eacr caused a stepping port switch (or if we have to | |
1083 | * assume that a stepping port switch has occured) or the | |
1084 | * clock syncing failed, reset the sync check control bit | |
1085 | * and set up a timer to try again after 0.5 seconds | |
1086 | */ | |
1087 | etr_update_eacr(eacr); | |
1088 | if (now < etr_tolec + (1600000 << 12) || | |
750887de | 1089 | etr_sync_clock_stop(&aib, sync_port) != 0) { |
d54853ef MS |
1090 | /* Sync failed. Try again in 1/2 second. */ |
1091 | eacr.es = 0; | |
1092 | etr_update_eacr(eacr); | |
1093 | etr_set_sync_timeout(); | |
1094 | } else | |
1095 | etr_set_tolec_timeout(now); | |
0b3016b7 MS |
1096 | out_unlock: |
1097 | mutex_unlock(&etr_work_mutex); | |
d54853ef MS |
1098 | } |
1099 | ||
1100 | /* | |
1101 | * Sysfs interface functions | |
1102 | */ | |
1103 | static struct sysdev_class etr_sysclass = { | |
af5ca3f4 | 1104 | .name = "etr", |
d54853ef MS |
1105 | }; |
1106 | ||
1107 | static struct sys_device etr_port0_dev = { | |
1108 | .id = 0, | |
1109 | .cls = &etr_sysclass, | |
1110 | }; | |
1111 | ||
1112 | static struct sys_device etr_port1_dev = { | |
1113 | .id = 1, | |
1114 | .cls = &etr_sysclass, | |
1115 | }; | |
1116 | ||
1117 | /* | |
1118 | * ETR class attributes | |
1119 | */ | |
c9be0a36 AK |
1120 | static ssize_t etr_stepping_port_show(struct sysdev_class *class, |
1121 | struct sysdev_class_attribute *attr, | |
1122 | char *buf) | |
d54853ef MS |
1123 | { |
1124 | return sprintf(buf, "%i\n", etr_port0.esw.p); | |
1125 | } | |
1126 | ||
1127 | static SYSDEV_CLASS_ATTR(stepping_port, 0400, etr_stepping_port_show, NULL); | |
1128 | ||
c9be0a36 AK |
1129 | static ssize_t etr_stepping_mode_show(struct sysdev_class *class, |
1130 | struct sysdev_class_attribute *attr, | |
1131 | char *buf) | |
d54853ef MS |
1132 | { |
1133 | char *mode_str; | |
1134 | ||
1135 | if (etr_mode_is_pps(etr_eacr)) | |
1136 | mode_str = "pps"; | |
1137 | else if (etr_mode_is_etr(etr_eacr)) | |
1138 | mode_str = "etr"; | |
1139 | else | |
1140 | mode_str = "local"; | |
1141 | return sprintf(buf, "%s\n", mode_str); | |
1142 | } | |
1143 | ||
1144 | static SYSDEV_CLASS_ATTR(stepping_mode, 0400, etr_stepping_mode_show, NULL); | |
1145 | ||
1146 | /* | |
1147 | * ETR port attributes | |
1148 | */ | |
1149 | static inline struct etr_aib *etr_aib_from_dev(struct sys_device *dev) | |
1150 | { | |
1151 | if (dev == &etr_port0_dev) | |
1152 | return etr_port0_online ? &etr_port0 : NULL; | |
1153 | else | |
1154 | return etr_port1_online ? &etr_port1 : NULL; | |
1155 | } | |
1156 | ||
4a0b2b4d AK |
1157 | static ssize_t etr_online_show(struct sys_device *dev, |
1158 | struct sysdev_attribute *attr, | |
1159 | char *buf) | |
d54853ef MS |
1160 | { |
1161 | unsigned int online; | |
1162 | ||
1163 | online = (dev == &etr_port0_dev) ? etr_port0_online : etr_port1_online; | |
1164 | return sprintf(buf, "%i\n", online); | |
1165 | } | |
1166 | ||
1167 | static ssize_t etr_online_store(struct sys_device *dev, | |
4a0b2b4d AK |
1168 | struct sysdev_attribute *attr, |
1169 | const char *buf, size_t count) | |
d54853ef MS |
1170 | { |
1171 | unsigned int value; | |
1172 | ||
1173 | value = simple_strtoul(buf, NULL, 0); | |
1174 | if (value != 0 && value != 1) | |
1175 | return -EINVAL; | |
d2fec595 MS |
1176 | if (!test_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags)) |
1177 | return -EOPNOTSUPP; | |
8283cb43 | 1178 | mutex_lock(&clock_sync_mutex); |
d54853ef MS |
1179 | if (dev == &etr_port0_dev) { |
1180 | if (etr_port0_online == value) | |
8283cb43 | 1181 | goto out; /* Nothing to do. */ |
d54853ef | 1182 | etr_port0_online = value; |
8283cb43 MS |
1183 | if (etr_port0_online && etr_port1_online) |
1184 | set_bit(CLOCK_SYNC_ETR, &clock_sync_flags); | |
1185 | else | |
1186 | clear_bit(CLOCK_SYNC_ETR, &clock_sync_flags); | |
d54853ef | 1187 | set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events); |
750887de | 1188 | queue_work(time_sync_wq, &etr_work); |
d54853ef MS |
1189 | } else { |
1190 | if (etr_port1_online == value) | |
8283cb43 | 1191 | goto out; /* Nothing to do. */ |
d54853ef | 1192 | etr_port1_online = value; |
8283cb43 MS |
1193 | if (etr_port0_online && etr_port1_online) |
1194 | set_bit(CLOCK_SYNC_ETR, &clock_sync_flags); | |
1195 | else | |
1196 | clear_bit(CLOCK_SYNC_ETR, &clock_sync_flags); | |
d54853ef | 1197 | set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events); |
750887de | 1198 | queue_work(time_sync_wq, &etr_work); |
d54853ef | 1199 | } |
8283cb43 MS |
1200 | out: |
1201 | mutex_unlock(&clock_sync_mutex); | |
d54853ef MS |
1202 | return count; |
1203 | } | |
1204 | ||
1205 | static SYSDEV_ATTR(online, 0600, etr_online_show, etr_online_store); | |
1206 | ||
4a0b2b4d AK |
1207 | static ssize_t etr_stepping_control_show(struct sys_device *dev, |
1208 | struct sysdev_attribute *attr, | |
1209 | char *buf) | |
d54853ef MS |
1210 | { |
1211 | return sprintf(buf, "%i\n", (dev == &etr_port0_dev) ? | |
1212 | etr_eacr.e0 : etr_eacr.e1); | |
1213 | } | |
1214 | ||
1215 | static SYSDEV_ATTR(stepping_control, 0400, etr_stepping_control_show, NULL); | |
1216 | ||
4a0b2b4d AK |
1217 | static ssize_t etr_mode_code_show(struct sys_device *dev, |
1218 | struct sysdev_attribute *attr, char *buf) | |
d54853ef MS |
1219 | { |
1220 | if (!etr_port0_online && !etr_port1_online) | |
1221 | /* Status word is not uptodate if both ports are offline. */ | |
1222 | return -ENODATA; | |
1223 | return sprintf(buf, "%i\n", (dev == &etr_port0_dev) ? | |
1224 | etr_port0.esw.psc0 : etr_port0.esw.psc1); | |
1225 | } | |
1226 | ||
1227 | static SYSDEV_ATTR(state_code, 0400, etr_mode_code_show, NULL); | |
1228 | ||
4a0b2b4d AK |
1229 | static ssize_t etr_untuned_show(struct sys_device *dev, |
1230 | struct sysdev_attribute *attr, char *buf) | |
d54853ef MS |
1231 | { |
1232 | struct etr_aib *aib = etr_aib_from_dev(dev); | |
1233 | ||
1234 | if (!aib || !aib->slsw.v1) | |
1235 | return -ENODATA; | |
1236 | return sprintf(buf, "%i\n", aib->edf1.u); | |
1237 | } | |
1238 | ||
1239 | static SYSDEV_ATTR(untuned, 0400, etr_untuned_show, NULL); | |
1240 | ||
4a0b2b4d AK |
1241 | static ssize_t etr_network_id_show(struct sys_device *dev, |
1242 | struct sysdev_attribute *attr, char *buf) | |
d54853ef MS |
1243 | { |
1244 | struct etr_aib *aib = etr_aib_from_dev(dev); | |
1245 | ||
1246 | if (!aib || !aib->slsw.v1) | |
1247 | return -ENODATA; | |
1248 | return sprintf(buf, "%i\n", aib->edf1.net_id); | |
1249 | } | |
1250 | ||
1251 | static SYSDEV_ATTR(network, 0400, etr_network_id_show, NULL); | |
1252 | ||
4a0b2b4d AK |
1253 | static ssize_t etr_id_show(struct sys_device *dev, |
1254 | struct sysdev_attribute *attr, char *buf) | |
d54853ef MS |
1255 | { |
1256 | struct etr_aib *aib = etr_aib_from_dev(dev); | |
1257 | ||
1258 | if (!aib || !aib->slsw.v1) | |
1259 | return -ENODATA; | |
1260 | return sprintf(buf, "%i\n", aib->edf1.etr_id); | |
1261 | } | |
1262 | ||
1263 | static SYSDEV_ATTR(id, 0400, etr_id_show, NULL); | |
1264 | ||
4a0b2b4d AK |
1265 | static ssize_t etr_port_number_show(struct sys_device *dev, |
1266 | struct sysdev_attribute *attr, char *buf) | |
d54853ef MS |
1267 | { |
1268 | struct etr_aib *aib = etr_aib_from_dev(dev); | |
1269 | ||
1270 | if (!aib || !aib->slsw.v1) | |
1271 | return -ENODATA; | |
1272 | return sprintf(buf, "%i\n", aib->edf1.etr_pn); | |
1273 | } | |
1274 | ||
1275 | static SYSDEV_ATTR(port, 0400, etr_port_number_show, NULL); | |
1276 | ||
4a0b2b4d AK |
1277 | static ssize_t etr_coupled_show(struct sys_device *dev, |
1278 | struct sysdev_attribute *attr, char *buf) | |
d54853ef MS |
1279 | { |
1280 | struct etr_aib *aib = etr_aib_from_dev(dev); | |
1281 | ||
1282 | if (!aib || !aib->slsw.v3) | |
1283 | return -ENODATA; | |
1284 | return sprintf(buf, "%i\n", aib->edf3.c); | |
1285 | } | |
1286 | ||
1287 | static SYSDEV_ATTR(coupled, 0400, etr_coupled_show, NULL); | |
1288 | ||
4a0b2b4d AK |
1289 | static ssize_t etr_local_time_show(struct sys_device *dev, |
1290 | struct sysdev_attribute *attr, char *buf) | |
d54853ef MS |
1291 | { |
1292 | struct etr_aib *aib = etr_aib_from_dev(dev); | |
1293 | ||
1294 | if (!aib || !aib->slsw.v3) | |
1295 | return -ENODATA; | |
1296 | return sprintf(buf, "%i\n", aib->edf3.blto); | |
1297 | } | |
1298 | ||
1299 | static SYSDEV_ATTR(local_time, 0400, etr_local_time_show, NULL); | |
1300 | ||
4a0b2b4d AK |
1301 | static ssize_t etr_utc_offset_show(struct sys_device *dev, |
1302 | struct sysdev_attribute *attr, char *buf) | |
d54853ef MS |
1303 | { |
1304 | struct etr_aib *aib = etr_aib_from_dev(dev); | |
1305 | ||
1306 | if (!aib || !aib->slsw.v3) | |
1307 | return -ENODATA; | |
1308 | return sprintf(buf, "%i\n", aib->edf3.buo); | |
1309 | } | |
1310 | ||
1311 | static SYSDEV_ATTR(utc_offset, 0400, etr_utc_offset_show, NULL); | |
1312 | ||
1313 | static struct sysdev_attribute *etr_port_attributes[] = { | |
1314 | &attr_online, | |
1315 | &attr_stepping_control, | |
1316 | &attr_state_code, | |
1317 | &attr_untuned, | |
1318 | &attr_network, | |
1319 | &attr_id, | |
1320 | &attr_port, | |
1321 | &attr_coupled, | |
1322 | &attr_local_time, | |
1323 | &attr_utc_offset, | |
1324 | NULL | |
1325 | }; | |
1326 | ||
1327 | static int __init etr_register_port(struct sys_device *dev) | |
1328 | { | |
1329 | struct sysdev_attribute **attr; | |
1330 | int rc; | |
1331 | ||
1332 | rc = sysdev_register(dev); | |
1333 | if (rc) | |
1334 | goto out; | |
1335 | for (attr = etr_port_attributes; *attr; attr++) { | |
1336 | rc = sysdev_create_file(dev, *attr); | |
1337 | if (rc) | |
1338 | goto out_unreg; | |
1339 | } | |
1340 | return 0; | |
1341 | out_unreg: | |
1342 | for (; attr >= etr_port_attributes; attr--) | |
1343 | sysdev_remove_file(dev, *attr); | |
1344 | sysdev_unregister(dev); | |
1345 | out: | |
1346 | return rc; | |
1347 | } | |
1348 | ||
1349 | static void __init etr_unregister_port(struct sys_device *dev) | |
1350 | { | |
1351 | struct sysdev_attribute **attr; | |
1352 | ||
1353 | for (attr = etr_port_attributes; *attr; attr++) | |
1354 | sysdev_remove_file(dev, *attr); | |
1355 | sysdev_unregister(dev); | |
1356 | } | |
1357 | ||
1358 | static int __init etr_init_sysfs(void) | |
1359 | { | |
1360 | int rc; | |
1361 | ||
1362 | rc = sysdev_class_register(&etr_sysclass); | |
1363 | if (rc) | |
1364 | goto out; | |
1365 | rc = sysdev_class_create_file(&etr_sysclass, &attr_stepping_port); | |
1366 | if (rc) | |
1367 | goto out_unreg_class; | |
1368 | rc = sysdev_class_create_file(&etr_sysclass, &attr_stepping_mode); | |
1369 | if (rc) | |
1370 | goto out_remove_stepping_port; | |
1371 | rc = etr_register_port(&etr_port0_dev); | |
1372 | if (rc) | |
1373 | goto out_remove_stepping_mode; | |
1374 | rc = etr_register_port(&etr_port1_dev); | |
1375 | if (rc) | |
1376 | goto out_remove_port0; | |
1377 | return 0; | |
1378 | ||
1379 | out_remove_port0: | |
1380 | etr_unregister_port(&etr_port0_dev); | |
1381 | out_remove_stepping_mode: | |
1382 | sysdev_class_remove_file(&etr_sysclass, &attr_stepping_mode); | |
1383 | out_remove_stepping_port: | |
1384 | sysdev_class_remove_file(&etr_sysclass, &attr_stepping_port); | |
1385 | out_unreg_class: | |
1386 | sysdev_class_unregister(&etr_sysclass); | |
1387 | out: | |
1388 | return rc; | |
1da177e4 LT |
1389 | } |
1390 | ||
d54853ef | 1391 | device_initcall(etr_init_sysfs); |
d2fec595 MS |
1392 | |
1393 | /* | |
1394 | * Server Time Protocol (STP) code. | |
1395 | */ | |
1396 | static int stp_online; | |
1397 | static struct stp_sstpi stp_info; | |
1398 | static void *stp_page; | |
1399 | ||
1400 | static void stp_work_fn(struct work_struct *work); | |
0b3016b7 | 1401 | static DEFINE_MUTEX(stp_work_mutex); |
d2fec595 | 1402 | static DECLARE_WORK(stp_work, stp_work_fn); |
04362301 | 1403 | static struct timer_list stp_timer; |
d2fec595 MS |
1404 | |
1405 | static int __init early_parse_stp(char *p) | |
1406 | { | |
1407 | if (strncmp(p, "off", 3) == 0) | |
1408 | stp_online = 0; | |
1409 | else if (strncmp(p, "on", 2) == 0) | |
1410 | stp_online = 1; | |
1411 | return 0; | |
1412 | } | |
1413 | early_param("stp", early_parse_stp); | |
1414 | ||
1415 | /* | |
1416 | * Reset STP attachment. | |
1417 | */ | |
8f847003 | 1418 | static void __init stp_reset(void) |
d2fec595 MS |
1419 | { |
1420 | int rc; | |
1421 | ||
d7d1104f | 1422 | stp_page = (void *) get_zeroed_page(GFP_ATOMIC); |
d2fec595 | 1423 | rc = chsc_sstpc(stp_page, STP_OP_CTRL, 0x0000); |
4a672cfa | 1424 | if (rc == 0) |
d2fec595 MS |
1425 | set_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags); |
1426 | else if (stp_online) { | |
feab6501 MS |
1427 | pr_warning("The real or virtual hardware system does " |
1428 | "not provide an STP interface\n"); | |
d7d1104f | 1429 | free_page((unsigned long) stp_page); |
d2fec595 MS |
1430 | stp_page = NULL; |
1431 | stp_online = 0; | |
1432 | } | |
1433 | } | |
1434 | ||
04362301 MS |
1435 | static void stp_timeout(unsigned long dummy) |
1436 | { | |
1437 | queue_work(time_sync_wq, &stp_work); | |
1438 | } | |
1439 | ||
d2fec595 MS |
1440 | static int __init stp_init(void) |
1441 | { | |
750887de HC |
1442 | if (!test_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags)) |
1443 | return 0; | |
04362301 | 1444 | setup_timer(&stp_timer, stp_timeout, 0UL); |
750887de HC |
1445 | time_init_wq(); |
1446 | if (!stp_online) | |
1447 | return 0; | |
1448 | queue_work(time_sync_wq, &stp_work); | |
d2fec595 MS |
1449 | return 0; |
1450 | } | |
1451 | ||
1452 | arch_initcall(stp_init); | |
1453 | ||
1454 | /* | |
1455 | * STP timing alert. There are three causes: | |
1456 | * 1) timing status change | |
1457 | * 2) link availability change | |
1458 | * 3) time control parameter change | |
1459 | * In all three cases we are only interested in the clock source state. | |
1460 | * If a STP clock source is now available use it. | |
1461 | */ | |
1462 | static void stp_timing_alert(struct stp_irq_parm *intparm) | |
1463 | { | |
1464 | if (intparm->tsc || intparm->lac || intparm->tcpc) | |
750887de | 1465 | queue_work(time_sync_wq, &stp_work); |
d2fec595 MS |
1466 | } |
1467 | ||
1468 | /* | |
1469 | * STP sync check machine check. This is called when the timing state | |
1470 | * changes from the synchronized state to the unsynchronized state. | |
1471 | * After a STP sync check the clock is not in sync. The machine check | |
1472 | * is broadcasted to all cpus at the same time. | |
1473 | */ | |
1474 | void stp_sync_check(void) | |
1475 | { | |
d2fec595 | 1476 | disable_sync_clock(NULL); |
750887de | 1477 | queue_work(time_sync_wq, &stp_work); |
d2fec595 MS |
1478 | } |
1479 | ||
1480 | /* | |
1481 | * STP island condition machine check. This is called when an attached | |
1482 | * server attempts to communicate over an STP link and the servers | |
1483 | * have matching CTN ids and have a valid stratum-1 configuration | |
1484 | * but the configurations do not match. | |
1485 | */ | |
1486 | void stp_island_check(void) | |
1487 | { | |
d2fec595 | 1488 | disable_sync_clock(NULL); |
750887de | 1489 | queue_work(time_sync_wq, &stp_work); |
d2fec595 MS |
1490 | } |
1491 | ||
750887de HC |
1492 | |
1493 | static int stp_sync_clock(void *data) | |
d2fec595 | 1494 | { |
750887de | 1495 | static int first; |
d2fec595 | 1496 | unsigned long long old_clock, delta; |
750887de | 1497 | struct clock_sync_data *stp_sync; |
d2fec595 MS |
1498 | int rc; |
1499 | ||
750887de | 1500 | stp_sync = data; |
d2fec595 | 1501 | |
750887de HC |
1502 | if (xchg(&first, 1) == 1) { |
1503 | /* Slave */ | |
1504 | clock_sync_cpu(stp_sync); | |
1505 | return 0; | |
1506 | } | |
d2fec595 | 1507 | |
750887de HC |
1508 | /* Wait until all other cpus entered the sync function. */ |
1509 | while (atomic_read(&stp_sync->cpus) != 0) | |
1510 | cpu_relax(); | |
d2fec595 | 1511 | |
d2fec595 MS |
1512 | enable_sync_clock(); |
1513 | ||
d2fec595 MS |
1514 | rc = 0; |
1515 | if (stp_info.todoff[0] || stp_info.todoff[1] || | |
1516 | stp_info.todoff[2] || stp_info.todoff[3] || | |
1517 | stp_info.tmd != 2) { | |
1518 | old_clock = get_clock(); | |
1519 | rc = chsc_sstpc(stp_page, STP_OP_SYNC, 0); | |
1520 | if (rc == 0) { | |
1521 | delta = adjust_time(old_clock, get_clock(), 0); | |
1522 | fixup_clock_comparator(delta); | |
1523 | rc = chsc_sstpi(stp_page, &stp_info, | |
1524 | sizeof(struct stp_sstpi)); | |
1525 | if (rc == 0 && stp_info.tmd != 2) | |
1526 | rc = -EAGAIN; | |
1527 | } | |
1528 | } | |
1529 | if (rc) { | |
1530 | disable_sync_clock(NULL); | |
750887de | 1531 | stp_sync->in_sync = -EAGAIN; |
d2fec595 | 1532 | } else |
750887de HC |
1533 | stp_sync->in_sync = 1; |
1534 | xchg(&first, 0); | |
1535 | return 0; | |
1536 | } | |
d2fec595 | 1537 | |
750887de HC |
1538 | /* |
1539 | * STP work. Check for the STP state and take over the clock | |
1540 | * synchronization if the STP clock source is usable. | |
1541 | */ | |
1542 | static void stp_work_fn(struct work_struct *work) | |
1543 | { | |
1544 | struct clock_sync_data stp_sync; | |
1545 | int rc; | |
1546 | ||
0b3016b7 MS |
1547 | /* prevent multiple execution. */ |
1548 | mutex_lock(&stp_work_mutex); | |
1549 | ||
750887de HC |
1550 | if (!stp_online) { |
1551 | chsc_sstpc(stp_page, STP_OP_CTRL, 0x0000); | |
04362301 | 1552 | del_timer_sync(&stp_timer); |
0b3016b7 | 1553 | goto out_unlock; |
750887de HC |
1554 | } |
1555 | ||
1556 | rc = chsc_sstpc(stp_page, STP_OP_CTRL, 0xb0e0); | |
1557 | if (rc) | |
0b3016b7 | 1558 | goto out_unlock; |
750887de HC |
1559 | |
1560 | rc = chsc_sstpi(stp_page, &stp_info, sizeof(struct stp_sstpi)); | |
1561 | if (rc || stp_info.c == 0) | |
0b3016b7 | 1562 | goto out_unlock; |
750887de | 1563 | |
8283cb43 MS |
1564 | /* Skip synchronization if the clock is already in sync. */ |
1565 | if (check_sync_clock()) | |
1566 | goto out_unlock; | |
1567 | ||
750887de HC |
1568 | memset(&stp_sync, 0, sizeof(stp_sync)); |
1569 | get_online_cpus(); | |
1570 | atomic_set(&stp_sync.cpus, num_online_cpus() - 1); | |
1571 | stop_machine(stp_sync_clock, &stp_sync, &cpu_online_map); | |
1572 | put_online_cpus(); | |
0b3016b7 | 1573 | |
04362301 MS |
1574 | if (!check_sync_clock()) |
1575 | /* | |
1576 | * There is a usable clock but the synchonization failed. | |
1577 | * Retry after a second. | |
1578 | */ | |
1579 | mod_timer(&stp_timer, jiffies + HZ); | |
1580 | ||
0b3016b7 MS |
1581 | out_unlock: |
1582 | mutex_unlock(&stp_work_mutex); | |
d2fec595 MS |
1583 | } |
1584 | ||
1585 | /* | |
1586 | * STP class sysfs interface functions | |
1587 | */ | |
1588 | static struct sysdev_class stp_sysclass = { | |
1589 | .name = "stp", | |
1590 | }; | |
1591 | ||
c9be0a36 AK |
1592 | static ssize_t stp_ctn_id_show(struct sysdev_class *class, |
1593 | struct sysdev_class_attribute *attr, | |
1594 | char *buf) | |
d2fec595 MS |
1595 | { |
1596 | if (!stp_online) | |
1597 | return -ENODATA; | |
1598 | return sprintf(buf, "%016llx\n", | |
1599 | *(unsigned long long *) stp_info.ctnid); | |
1600 | } | |
1601 | ||
1602 | static SYSDEV_CLASS_ATTR(ctn_id, 0400, stp_ctn_id_show, NULL); | |
1603 | ||
c9be0a36 AK |
1604 | static ssize_t stp_ctn_type_show(struct sysdev_class *class, |
1605 | struct sysdev_class_attribute *attr, | |
1606 | char *buf) | |
d2fec595 MS |
1607 | { |
1608 | if (!stp_online) | |
1609 | return -ENODATA; | |
1610 | return sprintf(buf, "%i\n", stp_info.ctn); | |
1611 | } | |
1612 | ||
1613 | static SYSDEV_CLASS_ATTR(ctn_type, 0400, stp_ctn_type_show, NULL); | |
1614 | ||
c9be0a36 AK |
1615 | static ssize_t stp_dst_offset_show(struct sysdev_class *class, |
1616 | struct sysdev_class_attribute *attr, | |
1617 | char *buf) | |
d2fec595 MS |
1618 | { |
1619 | if (!stp_online || !(stp_info.vbits & 0x2000)) | |
1620 | return -ENODATA; | |
1621 | return sprintf(buf, "%i\n", (int)(s16) stp_info.dsto); | |
1622 | } | |
1623 | ||
1624 | static SYSDEV_CLASS_ATTR(dst_offset, 0400, stp_dst_offset_show, NULL); | |
1625 | ||
c9be0a36 AK |
1626 | static ssize_t stp_leap_seconds_show(struct sysdev_class *class, |
1627 | struct sysdev_class_attribute *attr, | |
1628 | char *buf) | |
d2fec595 MS |
1629 | { |
1630 | if (!stp_online || !(stp_info.vbits & 0x8000)) | |
1631 | return -ENODATA; | |
1632 | return sprintf(buf, "%i\n", (int)(s16) stp_info.leaps); | |
1633 | } | |
1634 | ||
1635 | static SYSDEV_CLASS_ATTR(leap_seconds, 0400, stp_leap_seconds_show, NULL); | |
1636 | ||
c9be0a36 AK |
1637 | static ssize_t stp_stratum_show(struct sysdev_class *class, |
1638 | struct sysdev_class_attribute *attr, | |
1639 | char *buf) | |
d2fec595 MS |
1640 | { |
1641 | if (!stp_online) | |
1642 | return -ENODATA; | |
1643 | return sprintf(buf, "%i\n", (int)(s16) stp_info.stratum); | |
1644 | } | |
1645 | ||
1646 | static SYSDEV_CLASS_ATTR(stratum, 0400, stp_stratum_show, NULL); | |
1647 | ||
c9be0a36 AK |
1648 | static ssize_t stp_time_offset_show(struct sysdev_class *class, |
1649 | struct sysdev_class_attribute *attr, | |
1650 | char *buf) | |
d2fec595 MS |
1651 | { |
1652 | if (!stp_online || !(stp_info.vbits & 0x0800)) | |
1653 | return -ENODATA; | |
1654 | return sprintf(buf, "%i\n", (int) stp_info.tto); | |
1655 | } | |
1656 | ||
1657 | static SYSDEV_CLASS_ATTR(time_offset, 0400, stp_time_offset_show, NULL); | |
1658 | ||
c9be0a36 AK |
1659 | static ssize_t stp_time_zone_offset_show(struct sysdev_class *class, |
1660 | struct sysdev_class_attribute *attr, | |
1661 | char *buf) | |
d2fec595 MS |
1662 | { |
1663 | if (!stp_online || !(stp_info.vbits & 0x4000)) | |
1664 | return -ENODATA; | |
1665 | return sprintf(buf, "%i\n", (int)(s16) stp_info.tzo); | |
1666 | } | |
1667 | ||
1668 | static SYSDEV_CLASS_ATTR(time_zone_offset, 0400, | |
1669 | stp_time_zone_offset_show, NULL); | |
1670 | ||
c9be0a36 AK |
1671 | static ssize_t stp_timing_mode_show(struct sysdev_class *class, |
1672 | struct sysdev_class_attribute *attr, | |
1673 | char *buf) | |
d2fec595 MS |
1674 | { |
1675 | if (!stp_online) | |
1676 | return -ENODATA; | |
1677 | return sprintf(buf, "%i\n", stp_info.tmd); | |
1678 | } | |
1679 | ||
1680 | static SYSDEV_CLASS_ATTR(timing_mode, 0400, stp_timing_mode_show, NULL); | |
1681 | ||
c9be0a36 AK |
1682 | static ssize_t stp_timing_state_show(struct sysdev_class *class, |
1683 | struct sysdev_class_attribute *attr, | |
1684 | char *buf) | |
d2fec595 MS |
1685 | { |
1686 | if (!stp_online) | |
1687 | return -ENODATA; | |
1688 | return sprintf(buf, "%i\n", stp_info.tst); | |
1689 | } | |
1690 | ||
1691 | static SYSDEV_CLASS_ATTR(timing_state, 0400, stp_timing_state_show, NULL); | |
1692 | ||
c9be0a36 AK |
1693 | static ssize_t stp_online_show(struct sysdev_class *class, |
1694 | struct sysdev_class_attribute *attr, | |
1695 | char *buf) | |
d2fec595 MS |
1696 | { |
1697 | return sprintf(buf, "%i\n", stp_online); | |
1698 | } | |
1699 | ||
1700 | static ssize_t stp_online_store(struct sysdev_class *class, | |
c9be0a36 | 1701 | struct sysdev_class_attribute *attr, |
d2fec595 MS |
1702 | const char *buf, size_t count) |
1703 | { | |
1704 | unsigned int value; | |
1705 | ||
1706 | value = simple_strtoul(buf, NULL, 0); | |
1707 | if (value != 0 && value != 1) | |
1708 | return -EINVAL; | |
1709 | if (!test_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags)) | |
1710 | return -EOPNOTSUPP; | |
8283cb43 | 1711 | mutex_lock(&clock_sync_mutex); |
d2fec595 | 1712 | stp_online = value; |
8283cb43 MS |
1713 | if (stp_online) |
1714 | set_bit(CLOCK_SYNC_STP, &clock_sync_flags); | |
1715 | else | |
1716 | clear_bit(CLOCK_SYNC_STP, &clock_sync_flags); | |
750887de | 1717 | queue_work(time_sync_wq, &stp_work); |
8283cb43 | 1718 | mutex_unlock(&clock_sync_mutex); |
d2fec595 MS |
1719 | return count; |
1720 | } | |
1721 | ||
1722 | /* | |
1723 | * Can't use SYSDEV_CLASS_ATTR because the attribute should be named | |
1724 | * stp/online but attr_online already exists in this file .. | |
1725 | */ | |
1726 | static struct sysdev_class_attribute attr_stp_online = { | |
1727 | .attr = { .name = "online", .mode = 0600 }, | |
1728 | .show = stp_online_show, | |
1729 | .store = stp_online_store, | |
1730 | }; | |
1731 | ||
1732 | static struct sysdev_class_attribute *stp_attributes[] = { | |
1733 | &attr_ctn_id, | |
1734 | &attr_ctn_type, | |
1735 | &attr_dst_offset, | |
1736 | &attr_leap_seconds, | |
1737 | &attr_stp_online, | |
1738 | &attr_stratum, | |
1739 | &attr_time_offset, | |
1740 | &attr_time_zone_offset, | |
1741 | &attr_timing_mode, | |
1742 | &attr_timing_state, | |
1743 | NULL | |
1744 | }; | |
1745 | ||
1746 | static int __init stp_init_sysfs(void) | |
1747 | { | |
1748 | struct sysdev_class_attribute **attr; | |
1749 | int rc; | |
1750 | ||
1751 | rc = sysdev_class_register(&stp_sysclass); | |
1752 | if (rc) | |
1753 | goto out; | |
1754 | for (attr = stp_attributes; *attr; attr++) { | |
1755 | rc = sysdev_class_create_file(&stp_sysclass, *attr); | |
1756 | if (rc) | |
1757 | goto out_unreg; | |
1758 | } | |
1759 | return 0; | |
1760 | out_unreg: | |
1761 | for (; attr >= stp_attributes; attr--) | |
1762 | sysdev_class_remove_file(&stp_sysclass, *attr); | |
1763 | sysdev_class_unregister(&stp_sysclass); | |
1764 | out: | |
1765 | return rc; | |
1766 | } | |
1767 | ||
1768 | device_initcall(stp_init_sysfs); |